VIMAL JYOTHI ENGINEERING COLLEGE,CHEMPERI,KANNUR

DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION

ECL 203 LOGIC DESIGN LAB
Experiments
1. Realization of functions using basic and universal gates (SOP and POS forms).
LINK:-https://de-iitr.vlabs.ac.in/digital-electronics-iitr/exp/truth-table-gates/
DATE:18/9/2020.
VIVA QUESTIONS(MCQ)
Q1. The universal gate is ………………
1. NAND gate
2. OR gate
3. AND gate
4. None of the above
Ans. 1
Q2.  The inputs of a NAND gate are connected together. The resulting circuit is ………….
1. OR gate
2. AND gate
3. NOT gate
4. None of the above
Ans. 3
Q3. The NOR gate is OR gate followed by ………………
1. AND gate
2. NAND gate
3. NOT gate
4. None of the above
Ans. 3
Q4. In Boolean algebra, the bar sign (-) indicates ………………..
1. OR operation
2. AND operation
3. NOT operation
4. None of the above
Ans. 3
Q5. A single transistor can be used to build ………….. gates .
1. OR Gate
2. NOT Gate
3. AND Gate
4. NAND Gate
Ans. 3
 2. Design and Realization of half /full adder and subtractor using basic gates and
universal gates.
LINK 1:- https://de-iitr.vlabs.ac.in/digital-electronics-iitr/exp/half-full-adder/
LINK 2:- https://de-iitr.vlabs.ac.in/digital-electronics-iitr/exp/half-full-subtractor/
DATE:-26/08/2020
VIVA QUESTIONS(MCQ)
Q1. If A and B are the inputs of a half adder, the sum is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
Answer: c
Explanation: If A and B are the inputs of a half adder, the sum is given by A XOR B, while the carry
is given by A AND B.
Q2.  For subtracting 1 from 0, we use to take a _______ from neighbouring bits.
a) Carry
b) Borrow
c) Input
d) Output
Answer: b
Explanation: For subtracting 1 from 0, we use to take a borrow from neighbouring bits because
carry is taken into consideration during addition process.
Q3. Let A and B is the input of a subtractor then the output will be ___________
a) A XOR B
b) A AND B
c) A OR B
d) A EXNOR B
Answer: a
Explanation: The subtractor has two outputs BOROW and DIFFERENCE. Since, the difference
output of a subtractor is given by AB’ + BA’ and this is the output of a XOR gate. So, the final
difference output is AB’ + BA’.
Q4. Half-adders have a major limitation in that they cannot __________
a) Accept a carry bit from a present stage
b) Accept a carry bit from a next stage
c) Accept a carry bit from a previous stage
d) Accept a carry bit from the following stages
Answer: c
Explanation: Half-adders have a major limitation in that they cannot accept a carry bit from a
previous stage, meaning that they cannot be chained together to add multi-bit numbers. However,
the two output bits of a half-adder can also represent the result A+B=3 as sum and carry both being
high.
Q5.  How many AND, OR and EXOR gates are required for the configuration of full adder?
a) 1, 2, 2
b) 2, 1, 2
c) 3, 1, 2
d) 4, 0, 1
Answer: b
Explanation: There are 2 AND, 1 OR and 2 EXOR gates required for the configuration of full adder,
provided using half adder. Otherwise, configuration of full adder would require 3 AND, 2 OR and 2
EXOR.
 3. Study of Flip Flops: S-R, D, T, JK and Master Slave JK FF using NAND gates
https://de-iitr.vlabs.ac.in/digital-electronics-iitr/exp/truth-tables-flip-flops/
DATE:-08/09/2020
1. In a JK Flip-Flop, toggle means
(A) Set Q = 1 and Q = 0.
(B) Set Q = 0 and Q = 1.
(C) Change the output to the opposite state.
(D) No change in output.
Ans: C In a JK Flip-Flop, toggle means Change the output to the opposite state

2. One example of the use of an S-R flip-flop is as ___________

a) Transition pulse generator
b) Racer
c) Switch debouncer
d) Astable oscillator
Answer: c
Explanation: The SR flip-flop is very effective in removing the effects of switch bounce,
which is the unwanted noise caused during the switching of electronic devices.

3. Which of the following is correct for a gated D-type flip-flop?

a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH
Answer: a
Explanation: In D flip flop, when the clock is high then the output depends on the input
otherwise reminds previous output. In a state of clock high, when D is high the output Q also
high, if D is ‘0’ then output is also zero. Like SR flip-flop, the D-flip-flop also have an invalid
state at both inputs being 1.
4. In S-R flip-flop, if Q = 0 the output is said to be ___________
a) Set
b) Reset
c) Previous state
d) Current state
Answer: b
Explanation: In S-R flip-flop, if Q = 0 the output is said to be reset and set for Q = 1.
5. The basic latch consists of ___________
a) Two inverters
b) Two comparators
c) Two amplifiers
d) Two adders
Answer: a
Explanation: The basic latch consists of two inverters. It is in the sense that if the output Q = 0
then the second output Q’ = 1 and vice versa.
 4. Multiplexers and De-multiplexers using gates 
LINK1 :-https://de-iitr.vlabs.ac.in/digital-electronics-iitr/exp/multiplexer-demultiplexer/
DATE:-15/09/2020

1. 1. What is a multiplexer?
a) It is a type of decoder which decodes several inputs and gives one output
b) A multiplexer is a device which converts many signals into one
c) It takes one input and results into many output
d) It is a type of encoder which decodes several inputs and gives one output
Answer: b
Explanation: A multiplexer (or MUX) is a device that selects one of several
analog or digital input signals and forwards the selected input into a single
line, depending on the active select lines.
2.  What is the function of an enable input on a multiplexer chip?
a) To apply Vcc
b) To connect ground
c) To active the entire chip
d) To active one half of the chip
Answer: c
Explanation: Enable input is used to active the chip, when enable is high the
chip works (ACTIVE), when enable is low the chip does not work (MEMORY).
However, Enable can be Active-High or Active-Low, indicating it is active
either when it is connected to VCC or GND respectively.
3.  A basic multiplexer principle can be demonstrated through the use of a
___________
a) Single-pole relay
b) DPDT switch
c) Rotary switch
d) Linear stepper
Answer:c c
Explanation: A basic multiplexer principle can be demonstrated through the use
of a rotary switch. Since its behaviour is similar to the multiplexer. There are
around 10 digits out of which one is selected one at a time and fed to the output.
4. Most demultiplexers facilitate which type of conversion?
a) Decimal-to-hexadecimal
b) Single input, multiple outputs
c) AC to DC
d) Odd parity to even parity
Answer: b
Explanation: A demultiplexer sends a single input to multiple outputs, depending
on the select lines. Demultiplexer converts single input into multiple outputs.
5. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be ___________
a) Y0
b) Y1
c) Y2
d) Y3
Answer: d
 5.  Asynchronous Counter: Realization of Mod N counter & Synchronous Counter:
Realization of Mod-N counters.(4 bit Counter)
LINK 1:- https://de-iitr.vlabs.ac.in/digital-electronics-iitr/exp/4bit-synchronous-asynchronous-
counter/index.html

DATE:-22/09/2020
1. Internal propagation delay of asynchronous counter is removed by ____________
a) Ripple counter
b) Ring counter
c) Modulus counter
d) Synchronous counter
Answer: d
Explanation: Propagation delay refers to the amount of time taken in producing an output when
the input is altered. Internal propagation delay of asynchronous counter is removed by
synchronous counter because clock input is given to each flip-flop individually in synchronous
counter.
2. What happens to the parallel output word in an asynchronous binary down counter
whenever a clock pulse occurs?
a) The output increases by 1
b) The output decreases by 1
c) The output word increases by 2
d) The output word decreases by 2
Answer: b
Explanation: In an asynchronous counter, there isn’t any clock input. The output of 1 st flip-flop
is given to second flip-flop as clock input. So, in case of binary down counter the output word
decreases by 1.
3. A 4-bit counter has a maximum modulus of ____________
a) 3
b) 6
c) 8
d) 16
Answer: d
Explanation: In a n-bit counter, the total number of states = 2 n.
Therefore, in a 4-bit counter, the total number of states = 2 4 = 16 states
4. A counter circuit is usually constructed of ____________
a) A number of latches connected in cascade form
b) A number of NAND gates connected in cascade form
c) A number of flip-flops connected in cascade
d) A number of NOR gates connected in cascade form
Answer: c
Explanation: A counter circuit is usually constructed of a number of flip-flops connected in
cascade. Preferably, JK Flip-flops are used to construct counters and registers.
5.What is the maximum possible range of bit-count specifically in n-bit binary counter
consisting of ‘n’ number of flip-flops?
a) 0 to 2n
b) 0 to 2n + 1
c) 0 to 2n – 1
d) 0 to 2n+1/2
Answer: c
Explanation: The maximum possible range of bit-count specifically in n-bit binary counter
consisting of ‘n’ number of flip-flops is 0 to 2 n-1. For say, there is a 2-bit counter, then it will
count till 22-1 = 3. Thus, it will count from 0 to 3