IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO.

2, FEBRUARY 1998 295

A Simple Precharged CMOS Phase Frequency Detector

Henrik O. Johansson

Abstract— We propose a simple precharged CMOS phase

frequency detector (PFD). The circuit uses 18 transistors and has
a simple topology. Therefore, the detector, in a 0.8-m CMOS
process, works up to clock frequencies of 800 MHz according to
SPICE simulations on extracted layout. Further, the detector has
no dead-zone in the phase characteristic which is important in
low jitter applications. The phase and frequency characteristics
are presented and comparisons are made to other PFD’s. The
phase offset of the detector is sensitive to differences of the duty-
cycle between the inputs. Mixed-mode simulations are presented
of the lock-in procedure for a phase-locked loop (PLL) where
the detector is used. Measurements on the detector are presented
for a test-chip with a delay-locked loop (DLL) where the phase
detection ability of the detector has been verified. Fig. 1. Conventional phase frequency detector (conPFD) from [2].

Index Terms— CMOS integrated circuits, delay lock loops,

phase detectors, phase lock loops.

I. INTRODUCTION

A part of a phase-locked loop (PLL) is the phase detector

(PD) [1]. The PD detects the phase difference between
the reference frequency and the controlled slave frequency.
Some PD’s also detect frequency errors, they are then called
phase frequency detectors (PFD’s). A PFD is usually built
with a state machine with memory elements such as flip-flops
[2], [3], Figs. 1 and 2, respectively. We propose a new simple
PFD, ncPFD, which uses two nc-stages [4] and six inverters,
Fig. 3(a).
A drawback with some phase detectors is a dead zone in
Fig. 2. Precharge type phase frequency detector (ptPFD) from [3].
the phase characteristic at the equilibrium point. The dead zone
generates phase jitter since the control system does not change
the control voltage when the phase error is within the dead
zone.
In Section II the ncPFD circuit is described. The phase
and frequency characteristics are discussed in Sections III and
IV, respectively, and comparisons are made to other PFD’s.
Behavioral mixed-mode simulations are made to check the
lock-in properties of the ncPFD detector and these simulations
are shown in Section V. Experiments on the phase detection
abilities of the ncPFD are presented in Section VI.

II. CIRCUIT
The transistor schematic of the ncPFD is shown in Fig. 3(a).
The detector has a 0-rad phase offset. The main part of the
(a) (b)
circuit is the nc stage [4]. Delays (two inverters) are inserted
at the reference and slave inputs in order to remove the dead Fig. 3. (a) The ncPFD in zero degree phase offset version. (b) Modified
version with  rad phase offset.
zone in the phase characteristics around rad phase error. In
Fig. 4, waveforms for the circuit in Fig. 3(a) are shown when
The detector can easily be modified to one with -rad phase
the slave input lags the reference input.
offset, as shown in Fig. 3(b), where one, or in general an odd
Manuscript received March 11, 1997; revised August 21, 1997. number, of inverter(s) are used for the delays.
The author is with Electronic Devices, Department of Physics and Mea-
surement Technology, Linköping University, S-58183 Linköping, Sweden. If the phase detector is used only as a phase detector, i.e., not
Publisher Item Identifier S 0018-9200(98)00732-X. as a frequency detector, the circuit in Fig. 3(a) can be used as
0018–9200/98$10.00  1998 IEEE

Authorized licensed use limited to: VISVESVARAYA NATIONAL INSTITUTE OF TECHNOLOGY. Downloaded on September 19,2020 at 03:58:32 UTC from IEEE Xplore. Restrictions apply.
 296 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998

Fig. 4. Waveforms for the case when slave lags after the reference signal.
The pulse width of the up signal is larger than for the down signal.

Fig. 6. Magnified phase characteristics at zero phase error of the ncPFD

(solid line), conPFD (dashed line), and the ptPFD (dash-dot line) from SPICE
level-2 simulations of extracted layout, VDD = 3:0 V and f = 50 MHz.

Fig. 5. Phase characteristics of the ncPFD (solid line), conPFD (dashed line),
and the ptPFD (dash-dot line) from SPICE level-2 simulations of extracted
layout, VDD = 3:0 V and f = 50 MHz.

a -rad phase detector by switching the up and down signals.

The equilibrium point will then be on the negative slope of the
phase characteristics at rad instead of at the positive slope
at zero, Fig. 5. Similarly, the -rad phase detector, Fig. 3(b),
can be modified to a 0-rad phase detector.
Fig. 7. Phase characteristics for three cases with different duty cycles. The
III. PHASE CHARACTERISTIC reference input duty cycle is 50% for all cases and the slave input has the
duty-cycles 45%, 50%, and 55% for the dashed, solid, and dashed–dotted
The phase characteristic of the proposed ncPFD is shown lines, respectively.
in Fig. 5 together with the characteristics of the conventional
PFD (conPFD) of Fig. 1 [2] and the precharge type PFD
(ptPFD) shown in Fig. 2 [3]. Unlike the conPFD and ptPFD, characteristics. The phase characteristics are checked for three
there is no dead-zone in the characteristics of the ncPFD. A different duty cycles, 45, 50, and 55%.
magnification of the characteristics at zero phase is shown When both the reference and slave have the same duty cycle,
in Fig. 6. The dead zone of the conPFD can be reduced by the phase offset is not affected. There is a dead zone at -rad
inserting delay at the output of the four-input-NAND-gate. But when the duty cycle is less than 50%. A duty cycle of 45%
if delays are inserted in the feedback signals from the up gives a dead zone width of 0.50 rad, 1.6 ns, at rad. This
and down outputs of the ptPFD, the dead zone unfortunately dead zone may result in a metastable state of the control loop.
increases. When the duty cycle is different for the two inputs, the
In an ncPFD, when the PLL is locked, both up and down phase offset will be nonzero, Fig. 7. A duty cycle difference
signals are active. Therefore the phase offset of the PLL of 5% at 50 MHz, i.e., 1 ns, gives a phase offset of
depends on the matching between the up and down currents rad, i.e., 630 ps.
of the charge pump. The phase characteristic of the ncPFD is not affected by
All data in this section are based on simulations of extracted variations of the rise and fall times when they are in the range
layout with SPICE (level-2) when V and of 300 ps up to 600 ps.
MHz unless otherwise stated. The layout was made in a
0.8- m standard CMOS process and the N and P-transistors B. Maximum Operation Frequency
are 2.0 and 4.0 m wide, respectively. The outputs were A maximum operation frequency definition can be found in
connected to 4.0 fF capacitors, and the inputs were driven [3]. The definition is that the maximum operation frequency
with inverters with a tapering factor of one. is one over the shortest period with correct up and down
signals when the inputs have the same frequency and 90
A. Duty-Cycle and Transition-Time Dependence phase difference. This definition is easily applicable on flip-
The output of the ncPFD depends on the pulse-width of flop-based PFD’s where this frequency is easily identified.
the input signals. Hence, the duty cycle will affect the phase Unfortunately, the degradation of the performance of the

Authorized licensed use limited to: VISVESVARAYA NATIONAL INSTITUTE OF TECHNOLOGY. Downloaded on September 19,2020 at 03:58:32 UTC from IEEE Xplore. Restrictions apply.
 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998 297

Fig. 10. Waveforms for the case when the slave has a higher frequency than
the reference signal. The down signal has higher duty cycle than the up signal.

Fig. 8. The width of the dead zones of the ncPFD (solid), ptPFD (dashed),
and conventional PFD (dash-dot) as function of frequency. The frequency
resolution is 100 MHz and the supply voltage is 5.0 V. The plot is based on
SPICE simulations of extracted layout.

Fig. 11. Frequency sensitivity for the ncPFD (solid), ptPFD (dash-dot),
and conPFD (dashed). The plot is based on behavioral simulations with
20 different initial phases for each frequency and the mean-value for each
frequency is plotted. The reference frequency is 50 MHz.

The average frequency sensitivities of the ncPFD, ptPFD,

and conPFD are shown in Fig. 11. The frequency sensitivity
Fig. 9. Maximum frequency as function of supply voltage for the ncPFD
is represented by the rate of change in the control voltage
(solid line), the ptPFD (dash-dot line), and the conPFD (dashed line). The of the loop filter of a PLL when the slave input is driven
frequency resolution is 25 MHz. The plot is based on simulations of extracted by a pulse generator with a fixed frequency instead of the
layout. The layouts are made in a standard 0.8-m CMOS process.
voltage-controlled oscillator (VCO) output. Each frequency
is simulated 20 times with different initial phases, i.e., skew
ncPFD is gradual for increasing frequency and this makes it between the inputs.
hard to find a specific frequency where the circuit starts to The ptPFD has the largest sensitivity, followed by the
malfunction. conPFD, and the ncPFD has the lowest. The sensitivity goes to
Therefore, we define the maximum operation frequency zero as the slave frequency approaches the reference frequency
to be the frequency where the size of the dead zone starts for both the ncPFD and ptPFD. But for the conPFD, the
to deviate significantly from the low-frequency value. This sensitivity is relatively high even for frequencies close to the
definition gives similar results for the flip-flop-based phase reference.
detectors as for the definition in [3], and it is applicable on the In Fig. 12 the sensitivity for the ncPFD is shown with the
ncPFD. An example of how the dead-zone-width varies with mean, minimum, and maximum values from the 20 simulations
the frequency is shown in Fig. 8. for each frequency. Note that the behavior of the minimum and
The maximum speeds for different supply voltages are maximum values are almost random.
plotted in Fig. 9 for the three PFD’s of Figs. 1, 2, and 3(a). For the ncPFD, the minimum absolute value of the sensitiv-
As seen, the maximum speed of the ncPFD and the ptPFD are ity is close to zero for certain frequencies, Fig. 12. Actually,
similar and the conPFD is approximately three times slower. the sensitivity is zero for some frequency ratios and phase
combinations. This is the case also for the ptPFD but not for
the conPFD. The condition for this seems to be that when the
IV. FREQUENCY CHARACTERISTICS frequency ratio of the reference and slave inputs is a rational
A frequency dependent phase detector always has some number and the ratio is in the interval 1/2 to 2, including the
kind of memory. For the ncPFD, the memory consists of the limits, the sensitivity is zero for certain initial phases. We have
two dynamic nodes at the output of the nc-stages. In Fig. 10, no general proof of the previous statement but, for example,
the frequency of the slave input is approximately three times the sensitivity of the ncPFD for as
higher than the reference input frequency, as a result, the down function of initial phase is shown in Fig. 13. The sensitivity is
signal has a higher duty cycle than the up signal. Thus the zero for the phases 0.0, 2.5, and 5.0 ns. This lack of sensitivity
slave frequency should decrease. may lead to false locking for a PLL in operation. However,

Authorized licensed use limited to: VISVESVARAYA NATIONAL INSTITUTE OF TECHNOLOGY. Downloaded on September 19,2020 at 03:58:32 UTC from IEEE Xplore. Restrictions apply.
 298 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998

Fig. 12. Frequency sensitivity for the ncPFD for a number of frequencies. Fig. 14. Lock-in process of a third-order PLL with the ncPFD as phase
The plot is based on behavioral simulations with 20 different initial phases
+
for each frequency. The solid line is the mean value and the “ ” symbols are
frequency detector. The loop filter and PLL data are shown in the upper right
corner.
the minimum and maximum values. The reference frequency is 50 MHz.

language M [6]. The loop filter used ideal R and C models

in circuit mode with analog voltages. The loop filter and PLL
data are shown as an inset in Fig. 14. A lock-in simulation is
shown in Fig. 14. The simulation is done with the presence of
300 ps peak-to-peak phase noise.
Because of the sawtooth-shaped frequency sensitivity of the
ncPFD (for a fixed frequency offset and varied initial phase),
Fig. 13, and the presence of noise, the lock-in time is not
deterministic but random. The lock-in times for 60 simulations
have been analyzed. Most simulations show a lock-in time of
7 s and the largest time is 16 s. There is no upper limit on
the lock-in time. One simulation took approximately 3 cpu-min
on a SPARC 10 workstation.

Fig. 13. Frequency sensitivity for the ncPFD when the slave frequency is VI. EXPERIMENTS
4/5 of the reference frequency. For the initial phases of 0.0, 2.5, and 5.0 ns
the sensitivity is zero. The phase detection properties of the ncPFD have been
verified experimentally with a test chip. The test chip is a line
receiver for serial data that utilizes several parallel samplers
this false locking will not be stable, since a small phase change
to receive bit rates of 2.0 Gb/s [7]. The phase detector was
results in a nonzero sensitivity and drives the loop back to lock.
used in a delay-locked loop (DLL) which generates control
One way to add small phase changes to the simulation is to
signals for the sampling switches used in the line receiver.
include phase noise which is always present in an oscillator.
The ncPFD, Fig. 3(a), was used as a -rad phase detector and
When we add phase noise of approximately 300 ps peak-to-
the delay line was half a wavelength long.
peak to the simulations, the normalized minimum sensitivity
The skew between the reference and slave signals is not
which was zero will increase to approximately 0.01. The
possible to measure directly. This quantity has been measured
improvement is not significant but the sensitivity will be
indirectly through measurement error compensation circuits to
nonzero and positive for all phases. Hence, false locking is
be about 125 ps at MHz. Unfortunately, there is no
avoided. To further enhance the phase noise during the lock in
control of how large the measurement error is.
process, one could use dithering techniques, i.e., add the signal
The circuit blocks used to measure the offset are shown in
from a noise/signal source to the control voltage of the VCO.
Fig. 15. The two clocks that we want to compare come from
the beginning and the end of the delay line. They are fed into
V. BEHAVIORAL MIXED-MODE SIMULATIONS two matched inverter chains where the propagation delay for
In order to understand the sensitivity to frequency errors rising and falling edges are matched against process variations
and lock-in properties of the proposed detector, a complete [8]. The delay from the multiplexer inputs to the oscilloscope
third-order charge pump PLL system was simulated using a screen for the two signal paths are not matched. Two mea-
multilevel mixed-mode simulator, Lsim [5]. The PFD was surements are done to compensate this. One where the delay
represented by a schematic simulated in switch mode. The line input signal goes uninverted through Output buffer 1 and
VCO, phase-noise generator, and charge pump are represented one where the same signal goes inverted through the Output
by behavioral models written in the hardware description buffer 2. The measured skew including the measurement error

Authorized licensed use limited to: VISVESVARAYA NATIONAL INSTITUTE OF TECHNOLOGY. Downloaded on September 19,2020 at 03:58:32 UTC from IEEE Xplore. Restrictions apply.
 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998 299

Fig. 15. DLL, phase offset measurement circuitry, and NMOS transistor to
access the control voltage.
Fig. 16. Oscilloscope screen dump of the drain voltage of an NMOS
transistor with external pull-up resistor where the gate is connected to the
for the measurements will be as follows: control voltage. Four different lock-in procedures are shown. The initial
control voltages are 0.0, 1.0, 2.0, and 3.0 V for the curves from top to
skew inv mux Buf bottom, respectively.

inv mux Buf (1)

skew inv mux Buf VII. CONCLUSIONS
inv mux Buf (2) A new PFD without a dead zone has been proposed.
The circuit topology is simple and has no feedback loops.
where is the real skew and inv and inv are the Simulation results indicate that the circuit can operate up
delays through the four inverters’ long chains for falling and to 800 MHz in 0.8- m CMOS with a 5-V supply. The
rising edges through the left and right chain, respectively. detector’s phase offset depends on the duty cycle of the inputs.
Similarly, inv and inv are for the five inverters’ long Measurements have been performed on the detector when it
chains. And mux and mux are the delays through the was used in a DLL as a phase detector and the functionality
multiplexers. The Buf and Buf are the delays through was verified.
the output-buffers and through the oscilloscope input-channels.
The sum of the skews (1) and (2) is REFERENCES
skew skew inv inv [1] R. E. Best, Phase-Locked Loops, 2nd ed. New York, NY: McGraw-
Hill, 1993.
inv inv (3) [2] N. H. E. Weste and K. Eshragrian, Principles of CMOS VLSI Design,
2nd ed. Reading, MA: Addison Wesley, 1993.
Note that the expression is independent of the mux and Buf [3] H. Kondoh, H. Notani, T. Yoshimura, H. Shibata, and Y. Matsuda,
delays. Hence, theoretically, if the rise and fall delays of the “A 1.5-V 250-MHz to 3.0-V 622-MHz operation CMOS phase-locked
loop with precharge type phase-detector,” IEICE Trans. Electron., vol.
inverter chains are matched properly, there will not be any E78-C, no. 4, pp. 381–388, Apr. 1995.
measurement error. [4] P. Larsson and C. Svensson, “Skew safety and logic flexibility in a true
In Fig. 16 an oscilloscope screen dump with four lock-in single phase clocked system,” in Proc. IEEE Int. Symp. Circuits Syst.,
1995, pp. II:941–944.
procedures is shown. The signal is the drain voltage of an [5] Mentor Graphics, Explorer Lsim User’s Manual. Mentor Graphics
NMOS transistor with an external pull-up resistor and with the Corp., 1992.
[6] Mentor Graphics, M Language User’s Guide. Mentor Graphics Corp.,
gate connected to the control voltage as shown in Fig. 15. The 1991.
lock-in time is less than 200 s. Ideally, the control voltage [7] H. O. Johansson, J. Yuan, and C. Svensson, “A 4 Gsamples/s Line-
should go monotonically to the equilibrium voltage. Therefore, Receiver in 0.8 m CMOS,” in Proc. Symp. VLSI Circuits, 1996, pp.
116–117.
the beating in the lock-in procedure when the initial control [8] M. Shoji, “Elimination of process-dependent clock skew in CMOS
voltage is 3.0 V is unexpected. The reason for this is unknown. VLSI,” IEEE J. Solid-State Circuits, vol. SC-21, pp. 875–880, Oct. 1986.

Authorized licensed use limited to: VISVESVARAYA NATIONAL INSTITUTE OF TECHNOLOGY. Downloaded on September 19,2020 at 03:58:32 UTC from IEEE Xplore. Restrictions apply.