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Beginning FPGA Programming - Partie35.1

This document discusses different methods for implementing multiplexers (MUX) in VHDL, including the WHEN/ELSE statement, WITH/SELECT statement, and CASE statement. It provides code examples and RTL views for a 2-to-4 line MUX implemented with each method. The WHEN/ELSE statement allows priority decoding but requires typing input values multiple times, while WITH/SELECT and CASE statements implement the MUX with a single multiplexer but require the input only be typed once. Process and CASE statements examine all cases simultaneously, unlike software switches that are linear.

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ali alilou
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© © All Rights Reserved
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26 views

Beginning FPGA Programming - Partie35.1

This document discusses different methods for implementing multiplexers (MUX) in VHDL, including the WHEN/ELSE statement, WITH/SELECT statement, and CASE statement. It provides code examples and RTL views for a 2-to-4 line MUX implemented with each method. The WHEN/ELSE statement allows priority decoding but requires typing input values multiple times, while WITH/SELECT and CASE statements implement the MUX with a single multiplexer but require the input only be typed once. Process and CASE statements examine all cases simultaneously, unlike software switches that are linear.

Uploaded by

ali alilou
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Chapter 9 ■ Simplifying Boolean Algebra for FPGA

Listing 9-5.  WHEN ELSE MUX in VHDL Code


library ieee; -- All of the design need ieee library
use ieee.std_logic_1164.all; -- Using std_logic_1164 package

entity when_else_mux is
port (
mux_sel: in std_logic_vector(1 downto 0); -- 2 bit MUX Select
a_input: in std_logic_vector(7 downto 0);
b_input: in std_logic_vector(7 downto 0);
c_input: in std_logic_vector(7 downto 0);
d_input: in std_logic_vector(7 downto 0);
m_output: out std_logic_vector(7 downto 0)
);
end when_else_mux;

architecture behavioral of when_else_mux is


-- Declartions, such as type declarations, constant declarations, signal dtions etc

begin -- architecture behavioral of when_else_combination

m_output <= a_input WHEN mux_sel = "00" ELSE


b_input WHEN mux_sel = "01" ELSE
c_input WHEN mux_sel = "10" ELSE
b_input WHEN mux_sel = "11";
end behavioral;

9.3 Select Signal Assignment—With/Select


Based on several possible values of a single condition_variable, it assigns a value to signal_get_assignment.
You only need to type the condition_variable(a_input) one time in here. You can compare Listings 9-4 and
9-7. Listing 9-7 show that a_input only needs to be typed one time and Listing 9-4 must be typed four times.
The official name for this VHDL with/select assignment is the selected signal assignment.

Listing 9-6.  WITH SELECT VHDL Code Syntax


with condition_variable select signal_get_assignment <=
assign_value_1 when condition_1, -- condition_
variable equal to condition_1
assign_value_2 when condition_2, -- condition_
variable equal to condition_2
assign_value_3 when condition_3, -- condition_
variable equal to condition_3
...
assign_value_n when others;

Listing 9-7 shows the exact same function as Listing 9-1 but using With/Select.

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Chapter 9 ■ Simplifying Boolean Algebra for FPGA

Listing 9-7.  WITH SELECT Combination in VHDL Code


library ieee; -- All of the design need ieee library
use ieee.std_logic_1164.all; -- Using std_logic_1164 package

entity with_select_combination is
port (
a_input: in std_logic_vector(1 downto 0); -- 2 bit inputs
b_output: out std_logic_vector(3 downto 0) -- 4 bit outputs
);
end with_select_combination;

architecture behavioral of with_select_combination is


-- Declartions, such as type declarations, constant declarations, signal dtions etc

begin -- architecture behavioral of when_else_combination

with a_input select b_output <=


"0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when "11";
end behavioral;

Figure 9-5.  RTL view of WITH SELECT combination code Listing 9-7

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Chapter 9 ■ Simplifying Boolean Algebra for FPGA

From the differences between Figure 9-4 and Figure 9-5, you can tell that there is something different
between the two concurrent statements approach. The first one (WHEN/ELSE methods) added a priority
condition in the input. The logic will check condition_1 first. If it passes then the result will send to the
output (the Equal3 condition from Figure 9-4). For the WITH SELECT combination code, it uses MUX to
implement the design without any priority decoding. The WITH/SELECT statement can ONLY depend on
the value of a single expression. WHEN/ELSE statements, however, can depend on the values of multiple
expressions.
Listing 9-8 uses the same example for MUX with a four 8-bit input selection and one 8-bit output, this
time using a select statement. Figure 9-6 shows the RTL of the MUX design using WITH SELECT design.

Listing 9-8.  WHEN ELSE Combination in VHDL Code


library ieee; -- All of the design need ieee library
use ieee.std_logic_1164.all; -- Using std_logic_1164 package

entity with_select_mux is
port (
mux_sel: in std_logic_vector(1 downto 0); -- 2 bit inputs MUX select
a_input: in std_logic_vector(7 downto 0);
b_input: in std_logic_vector(7 downto 0);
c_input: in std_logic_vector(7 downto 0);
d_input: in std_logic_vector(7 downto 0);
m_output: out std_logic_vector(7 downto 0)
);
end with_select_mux;

architecture behavioral of with_select_combination is


begin -- architecture behavioral of when_else_combination

with mux_sel select m_output <=


a_input when "00",
b_input when "01",
c_input when "10",
d_input when "11";
end behavioral;

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Chapter 9 ■ Simplifying Boolean Algebra for FPGA

Figure 9-6.  RTL view of WITH SELECT combination code Listing 9-8

9.4 Process with Case Statement


Case statements are very similar to the WITH SELECT statement. At the start of the case statement is the
selector expression, between the keywords case and is (Listing 9-9). The value of the condition_variable is
used to select which statements to run. The body of the case statement contains a list of alternatives. Each
alternative starts with the keyword when and is followed by one or more condition values and assignment
statements. There MUST be exactly one condition value for each possible value. The last alternative is using
the keyword others, which include, all other condition values that the foregoing alternatives do not cover.

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Chapter 9 ■ Simplifying Boolean Algebra for FPGA

Listing 9-9.  Case Statement in VHDL Code Syntax


case condition_variable is
when condition_value1 => signal_get_assignment <= assign_value_1;
when condition_value2 => signal_get_assignment <= assign_value_2;
when condition_value3 => signal_get_assignment <= assign_value_3;
...
when others => signal_get_assignment <= assign_value_n;
end case;

■■Tip  Remember to add when others at the end of the alternative list.

The case statement is a good example to show the difference between programming software and
designing hardware. In the C programming language, switch case statements are examined from top to
bottom. In VHDL, all the cases are examined at the same time. C programs are limited by the processor only
allowing comparison of a limited number (most of the time it is one) of condition and branch locations. In
hardware design, we can design as many conditions and branches as we want.
Listing 9-10 shows the exact same function as described in Listing 9-1 except here we are using case
statements. The case statements need to be within the process begin and end process keywords. The
process must be sensitive to all the inputs (in this case a_input), because the output of the decoder (b_
output) must change when a_input changes.

Listing 9-10.  Process Case Combination in VHDL Code


library ieee; -- All of the design need ieee library
use ieee.std_logic_1164.all; -- Using std_logic_1164 package

entity case_combination is
port (
a_input: in std_logic_vector(1 downto 0); -- 2 bit inputs
b_output: out std_logic_vector(3 downto 0) -- 4 bit outputs
);
end case_combination;

architecture behavioral of case_combination is

begin -- architecture behavioral of case_combination

process( a_input ) -- process sensitive list: a_input


begin
case a_input is
when "00" => b_output <= "0001";
when "01" => b_output <= "0010";
when "10" => b_output <= "0100";
when "11" => b_output <= "1000";
when others => b_output <= "0000"; -- output default state
end case;
end process;

end behavioral;

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