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Beginning FPGA Programming - Partie34

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44 views

Beginning FPGA Programming - Partie34

h

Uploaded by

ali alilou
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CHAPTER 9

Simplifying Boolean Algebra for


FPGA

Using Boolean algebra to directly describe the combinational logic in VHDL (VHSIC (very high speed
integrated circuit) Hardware Description Language) may not be a good idea for a design that has more than
four inputs. When the combinational logic design has more than four inputs, the “logic” behind the design
tends to become difficult for other designers to understand. Let's do a quick test. Do you know what the code
in Listing 9-1 describes?

Listing 9-1.  Boolean Algebra in VHDL


library ieee; -- All of the design need ieee library
use ieee.std_logic_1164.all; -- Using std_logic_1164 package

entity code_9_1 is
port (
a_input: in std_logic_vector(1 downto 0); -- 2 bit inputs
b_output: out std_logic_vector(3 downto 0) -- 4 bit outputs
);
end code_9_1;

architecture behavioral of code_9_1 is

begin -- architecture behavioral of when_else_combination

b_output(0) <= NOT a_input(0) and NOT a_input(1);


b_output(1) <= a_input(0) and NOT a_input(1);
b_output(2) <= NOT a_input(0) and a_input(1);
b_output(3) <= a_input(0) and a_input(1);

end behavioral;

Listing 9-1 is a 2-to-4 decoder. Table 9-1 shows the decoder function. You can easily understand the
function of the design when you see the contents of Table 9-1. This is why VHDL provides a couple of ways
to make it easier for humans to understand the combinational logic/Boolean algebra design. Some call
these methods “Concurrent statements.” Following are the most frequently used concurrent statements. As a
quick reminder, there are only two types of statements that you will see a lot in FPGA design. One type is the
concurrent statement and the other is the sequential statement which we will discuss more in Chapter 10.

© Aiken Pang and Peter Membrey 2017 159


A. Pang and P. Membrey, Beginning FPGA: Programming Metal, DOI 10.1007/978-1-4302-6248-0_9
Chapter 9 ■ Simplifying Boolean Algebra for FPGA

Table 9-1.  Truth Table for Listing 9-1 Code

a_input(0)) a_input(1) b_output(3 downto 0)


0 0 0 0001
1 1 0 0010
2 0 1 0100
3 1 1 1000

■■Tip  You can use Quartus to show the VHDL in logic gate view. See the following steps.

1.
Save the code from Listing 9-1 into a code_9_1.vhd file and add it to the Quartus
project (Please see Chapter 8 on how to create a project and how to add files)
2.
Set code_9_1.vhd as Top-Level Entity, as shown in Figure 9-1

Figure 9-1.  Set as Top-Level Entity

3.
Click Processing from the menu and click Start compilation (CTRL +L)
4.
After the compilation is done, switch to Hierarchy mode in the Project Navigator
(A in Figure 9-2)

160
Chapter 9 ■ Simplifying Boolean Algebra for FPGA

Figure 9-2.  Locate in RTL viewer

5.
Right-click the code_9_1 design, click Locate Node, and select Locate in RTL
Viewer (B in Figure 9-2)
Figure 9-3 is the RTL Viewer for the gate logic described in Listing 9-1.

Figure 9-3. Listing 9-1 RTL view in gate level

161
Chapter 9 ■ Simplifying Boolean Algebra for FPGA

9.1 Concurrent Statements
In a programming language, program code or statements are processed one statement at a time
(assuming you are using a single-core processor). Each statement needs to wait for the previous statement
to finish. This is good for programming language, which is used to represent a list of instructions for a
processor to execute. It is also easy for humans to write programs like this because we are normally doing
one thing at a time.
VHDL does things differently. Where processors execute statements one at a time, VHDL has the
capability of executing a huge number of statements in parallel. This means that VHDL can run statements
in parallel. Keep in mind that VHDL is used to design real hardware. Running statements (hardware) in
parallel is a piece of cake. If you want to fully unlock the capability of the FPGA (field-programmable gateway
array), then you need to understand the following concurrent signal assignment methods.
In VHDL, most of the concurrent statements exist between begin and end. It is like the code in Listing 9-2.
All four statements are running at the same time. It means that at the same time, b_output(0), b_output(1),
b_output(2), and b_output(3) are updated when a_input(0) and a_input(1) change. The order of these
four statements will NOT create any difference in the final result. These kinds of statements are using
concurrent signal assignment.

Listing 9-2.  Concurrent Statement: Process in VHDL


process(a_input)
begin
b_output(0) <= NOT a_input(0) and NOT a_input(1);
b_output(1) <= a_input(0) and NOT a_input(1);
b_output(2) <= NOT a_input(0) and a_input(1);
b_output(3) <= a_input(0) and a_input(1);

end process;

The following sections introduce three more signal assignment operators used in concurrent
statements: When-Else, With-Select, and Case.

■■Tip The order of concurrent statements will have no impact whatsoever on the final result.

9.2 Conditional Signal Assignment—When/Else


The conditional signal assignment is a concurrent statement that is based on the condition (when/else) to
make the decision of which signals drive the outputs. Listing 9-3 shows what it looks like in code.

Listing 9-3.  When Else VHDL Code Syntax


signal_get_assignment <= assign_value_1 when condition_1 else
assign_value_2 when condition_2 else
assign_value_3 when condition_3 else
...
assign_value_n;

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Chapter 9 ■ Simplifying Boolean Algebra for FPGA

If the first condition (condition_1) is fulfilled, then the assign_value_1 will be assigned to the signal_get_
assignment. If the first condition is not fulfilled and the second condition is fulfilled, then the assign_value_2
will be assigned and drive the output signal_get_assignment. Follow this logic, until all of the conditions
(n-1) are not met, and then assign_value_n will drive the signal_get_assignment. Now let’s see how to use
when/else to do the same thing as the code in Listing 9-1.
Listing 9-4 is an example of using WHEN ELSE to create the same multiplexer as Listing 9-1. Figure 9-4
is the RTL view of the WHEN ELSE design. If you compare it with Figure 9-3, then you will find they are not
the same hardware but similar logic function.

Listing 9-4.  WHEN ELSE Combination in VHDL Code


library ieee; -- All of the design need ieee library
use ieee.std_logic_1164.all; -- Using std_logic_1164 package

entity when_else_combination is
port (
a_input: in std_logic_vector(1 downto 0); -- 2 bit inputs
b_output: out std_logic_vector(3 downto 0) -- 4 bit outputs
);
end when_else_combination;

architecture behavioral of when_else_combination is


-- Declartions, such as type declarations, constant declarations, signal dtions etc

begin -- architecture behavioral of when_else_combination

b_output <= "0001" WHEN a_input = "00" ELSE


"0010" WHEN a_input = "01" ELSE
"0100" WHEN a_input = "10" ELSE
"1000" WHEN a_input = "11" ELSE
"0000" ;
end behavioral;

Figure 9-4.  RTL view of WHEN ELSE combination code in Listing 9-4

There is another example code which is using a WHEN ELSE statement. It is a multiplexer (MUX) with
four 8-bit input selection and one 8-bit output.

163

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