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Beginning FPGA Programming - Partie30.1

This document provides steps to simulate a VHDL logic file in ModelSim: 1. Create a Quartus project and add a new VHDL file with the code from Listing 8-2 to implement boolean algebra example 2. 2. Set the VHDL file as the top-level entity. 3. Start analysis and elaboration in Quartus Prime and check for errors. 4. Launch the RTL simulation tool to simulate the VHDL design.

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ali alilou
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26 views5 pages

Beginning FPGA Programming - Partie30.1

This document provides steps to simulate a VHDL logic file in ModelSim: 1. Create a Quartus project and add a new VHDL file with the code from Listing 8-2 to implement boolean algebra example 2. 2. Set the VHDL file as the top-level entity. 3. Start analysis and elaboration in Quartus Prime and check for errors. 4. Launch the RTL simulation tool to simulate the VHDL design.

Uploaded by

ali alilou
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Chapter 8 ■ Telling the Truth: Boolean Algebra and Truth Tables

8.1.1 Simulation Steps for Boolean Algebra Example 2


It is time to do some simulation of this VHDL logic file. Please take the following steps to create the VHDL file
and simulate it in ModelSim:
1.
Create a Quartus project using the project template (see Chapter 4)
2.
Click File ➤ New… from the Quartus Prime menu to add a new VHDL file
(Figure 8-3).

Figure 8-3.  Add New file to project

3.
Select VHDL File and Click OK (Figure 8-4).

139
Chapter 8 ■ Telling the Truth: Boolean Algebra and Truth Tables

Figure 8-4.  Add New VHDL file in Quartus Project

4.
Copy the code from Listing 8-2 into the new VHDL file and save the file as
boolean_algebra_example2.vhd with the check box Add file to current project
ticked (Figure 8-5).

Listing 8-2.  boolean_algebra_example2.vhd


library ieee; -- All of the design need ieee library
use ieee.std_logic_1164.all; -- Using std_logic_1164 package

entity boolean_algebra_example2 is
port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Result: out std_logic
);
end boolean_algebra_example2;

140
Chapter 8 ■ Telling the Truth: Boolean Algebra and Truth Tables

architecture behavioral of boolean_algebra_example2 is


-- Declarations, such as type declarations, constant declarations, signal declarations etc
signal temp : std_logic;

begin -- architecture behavioral of boolean_algebra_example2

temp <= NOT A AND NOT B ;


Result <= NOT C AND temp;

end behavioral;

Figure 8-5.  Save the VHDL file as boolean_algebra_example2.vhd

5.
In Project Navigator, select Files. Right-click the file boolean_algebra_example.
vhd and click Set as Top-Level Entity (Figure 8-6).

141
Chapter 8 ■ Telling the Truth: Boolean Algebra and Truth Tables

Figure 8-6.  Set boolean_algebra_example2.vhd as Top-Level Entity

6.
Click Processing ➤ Start ➤ Start Analysis & Elaboration from the Quartus
Prime menu or click the blue triangle with green tick box in the toolbar to start
analysis & elaboration (Figure 8-7). It will not have any warnings or errors in the
message pane (Figure 8-8).

Figure 8-7.  Start Analysis & Elaboration button

142
Chapter 8 ■ Telling the Truth: Boolean Algebra and Truth Tables

Figure 8-8.  Message after Start Analysis & Elaboration finished

7.
Click Tools ➤ Run Simulation Tool ➤ RTL Simulation from the Quartus Prime
menu to start simulation (Figure 8-9). The Select Simulation Language box will
pop up; select VHDL and click OK (Figure 8-10).

Figure 8-9.  Start RTL simulation from Quartus Prime

143

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