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Beginning FPGA Programming - Partie18

This document discusses simulating a VHDL design using the ModelSim simulator. It provides instructions on setting up the simulation using Quartus Prime, generating a test bench template, and running the simulation. Key steps include using the Quartus Prime template writer to generate a test bench, selecting VHDL as the simulation language in ModelSim, and compiling the design files using the vcom command. The simulation allows verifying the design works as intended before programming the FPGA.

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ali alilou
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20 views

Beginning FPGA Programming - Partie18

This document discusses simulating a VHDL design using the ModelSim simulator. It provides instructions on setting up the simulation using Quartus Prime, generating a test bench template, and running the simulation. Key steps include using the Quartus Prime template writer to generate a test bench, selecting VHDL as the simulation language in ModelSim, and compiling the design files using the vcom command. The simulation allows verifying the design works as intended before programming the FPGA.

Uploaded by

ali alilou
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Chapter 4 ■ Hello World!

Figure 4-28.  Implement Finished with warnings

Figure 4-29.  Warning messages are OK to have.

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Chapter 4 ■ Hello World!

We should not have any critical warning like Timing requirements not met. This critical warning is
due to bad, wrong, or incomplete design. If you get a timing requirements not met warning, you should
review your design files.
Congratulations! You’ve compiled your first VHDL design! The next step is to work out whether it
actually works.

4.4 Simulate Design
Once you have completed the hardware design entry, you may want to simulate your design on a PC to gain
confidence that it works exactly as expected before pushing it to your FPGA. Simulation requires a form of
input stimulus and then the FPGA simulator software can determine the corresponding outputs. Design
simulation is important because we can quickly test our designs under different circumstances, which would
either be time-consuming or impossible to test on real hardware.
Altera provides us with industry standard software for simulating and analyzing designs. The name of
the tool is ModelSim. As the name suggests, it allows you to simulate your model/design.
There are two ways to create input stimulus:
• Tcl Script in ModelSim (easy)
• Using a test bench (a bit harder but more flexible)
We will pick the harder method for this example, although we will do it with Quartus Prime’s help.
Let's go build a test bench and run the simulation for our scanner design.
1.
Click Assignments ➤ Settings ➤ EDA Tools Settings\Simulation to open the
simulation settings window. Your setting should look like Figure 4-30.
• Tool name: ModelSim-Altera
• Output directory: simulation/modelsim
• NativeLink settings: None

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Chapter 4 ■ Hello World!

Figure 4-30.  Simulation settings

2.
Create the test bench template: Click Processing ➤ Start ➤ Start Test Bench
Template Writer from the Quartus Prime menu (Figure 4-31). The test bench
template writer is based on your top-level entity module and uses information
from that file to generate a test bench for it. It will show the location of the test
bench file in the processing message tab (Figure 4-32).

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Chapter 4 ■ Hello World!

Figure 4-31.  Quartus Prime Test Bench template writer

■■Tips Each module (entity) should have its own test bench to simulate the module. Each module needs
to be simulated before it can be connected to other modules. This can save you a huge amount of time when
debugging your design later. It also acts like a kind of safeguard for your design.

Figure 4-32.  Generated test bench template and the location of the file show in Processing Message tab

3.
Click Tools ➤ Run Simulation ➤ RTL Simulation to open ModelSim
(Simulation software). It is like Figure 4-33. The first time you run it in a project,
it will ask you to select the simulation language. Select VHDL and click OK
(Figure 4-34).

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Chapter 4 ■ Hello World!

Figure 4-33.  Start the Simulation software—ModelSim-Altera version

Figure 4-34.  Select simulation language—VHDL

4.
ModelSim ALTERA STARTER EDITION should open (Figure 4-35). In the transcript,
you should find the last line is ModelSim➤. Enter the following Tcl command and
hit Enter. Once completed you should see Figure 4-36 in the Transcript log.
• vcom -reportprogress 300 -work BeMicro_MAX10_top.vht

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