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Beginning FPGA Programming - Partie17

1. The document describes the steps to implement a VHDL design in Quartus Prime, including setting the top-level entity, editing the timing constraint file, starting the compilation process, and reviewing the compilation report. 2. Key steps include setting the BeMicro_MAX10_top.vhd file as the top-level entity, commenting out an unused clock in the timing file, and starting compilation by clicking Processing > Start Compilation. 3. The compilation report shows if implementation was successful, indicating logic element and pin usage and possibly containing warnings which are reviewed by clicking the warning icon.

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ali alilou
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55 views

Beginning FPGA Programming - Partie17

1. The document describes the steps to implement a VHDL design in Quartus Prime, including setting the top-level entity, editing the timing constraint file, starting the compilation process, and reviewing the compilation report. 2. Key steps include setting the BeMicro_MAX10_top.vhd file as the top-level entity, commenting out an unused clock in the timing file, and starting compilation by clicking Processing > Start Compilation. 3. The compilation report shows if implementation was successful, indicating logic element and pin usage and possibly containing warnings which are reviewed by clicking the warning icon.

Uploaded by

ali alilou
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Chapter 4 ■ Hello World!

4.3 Implement Design
Don’t worry if the VHDL code doesn’t make sense to you yet; all will be shown in good time. For now, save
the BeMicro_MAX10_top.vhd file and tell Quartus Prime to try to implement it. You can do the following to
implement the design:
1.
Click Hierarchy and select Files in the Project Navigator tab. In Files mode, the
project navigator will show you all the files in the project.
2.
Right-click the BeMicro_MAX10_top.vhd file and click Set as Top-Level Entity
from the context menu (Figure 4-23). This step is very important to ensure
that Quartus Prime picks the right entity (vhdl file) as the top-level file. This is
because Quartus Prime will start to implement the design from the top-level
entity. Sometimes people refer to this as the top module—the top of the design
hierarchy, where submodules are instantiated and linked together (conceptually
similar to the main function in a C program).

Figure 4-23.  Setting top-level entity

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Chapter 4 ■ Hello World!

3.
Double-click the BeMicro_MAX10_top.sdc file which is the timing file for this
project. Add # in the beginning of line 14 which comments out an unused
USER_CLK and adds derive_clock_uncertainty on line 32 (Figure 4-24). This
step can eliminate false warnings from Quartus Prime in the compile time.

Figure 4-24.  Timing constraint file—BeMicro_MAX10_top.sdc

4.
Click the Task tab to switch to the Tasks view. It will look like Figure 4-25.

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Chapter 4 ■ Hello World!

Figure 4-25.  Switch to Tasks view.

5.
To start the implementation process, you can use any of the following methods.
Figure 4-26 highlights the locations.
• Click Processing ➤ Start Compilation
• Press keyboard <Ctrl> + L
• Click the blue “play” triangle icon in the icon bar below the menu bar

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Chapter 4 ■ Hello World!

Figure 4-26.  How to start the implementation of the design

Quartus Prime will change to Figure 4-27 to show the implementation status. The Compilation report
tab will show up in the middle of Quartus Prime. The task list on the left-hand side will start to show each
task status and its finish time. The Stop icon will “light” up and will allow you to stop the process. In the
lower right corner, it will show 100% when it has finished doing the implementation. It may take a while to
map the logic onto the target device and generate timing data. This process should not take more than
15 minutes for this project as it’s a simple design. The time it takes is related to both the complexity of your
design and the specs of the computer you’re using to build it.

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Chapter 4 ■ Hello World!

Figure 4-27.  Implement Design in process

When you see six green ticks show up on the left-hand side of each of the tasks in the Tasks view,
Quartus Prime has successfully completed the implementation. You should also see “100%” in the lower
right corner. Figure 4-28 shows what it should look like. Please spend some time reading the Compilation
report even if you don’t fully understand it at this stage. It shows that the Scanner design used 53 logic
elements and 9 pins.
You may have found some warnings in your report. It is OK to have some warnings when building this
example. (Figure 4-28 shows that my project has three warnings). Let have a look at the warnings by clicking
the yellow warning triangle in Figure 4-29. It shows only warning in the message windows. The first warning
(ID: 292013) is because we are using the free Quartus Prime version. The second and third warnings are a result
of a lot of unused input and output pins which are removed from the design by Write code section step 5a.

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