Computer Organization

Performance,
RISC and CISC

Department of Computer Science

Missouri University of Science & Technology
[email protected]

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Note, this unit will be covered in three

lectures. In case you finish it earlier, then
you have the following options:
1) Take the early test and start CS3889.module7
2) Study the supplement module
(supplement CS3889.module6)
3) Act as a helper to help other students in
studying CS3889.module6
Note, options 2 and 3 have extra credits as noted in course
outline. 2
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{
Glossary of prerequisite topics

No Review
Enforcement Familiar with the topics? CS3889.module6.background
of background Yes
Take Test
At the end give a
No test, record the score,
Pass? Remedial action

{
and impose remedial
Yes
action if not
Glossary of topics successful

No
Familiar with the topics? Take the Module
Yes
Current Module Take Test
No
Pass?
Yes
Options

Lead a group of students in

Study next module? this module (extra credits)?
Study more advanced related
topics (extra credits)?

Extra Curricular activities

 Computer Organization

Performance Metrics
Response Time (Execution time, Latency) — The time
elapse between the start and the completion of an event.

Throughput (Bandwidth) — The amount of work done

in a given time.

Performance — Number of events occurring per unit of

time.

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Performance Metrics
Note execution time is the reciprocal of
performance — lower execution time implies
higher performance.

Note Response time, Throughput, and

Performance are all closely related to each
other.

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Performance Metrics
A system (X) is faster than (Y), if for a
given task, the response time on X is lower
than on Y.

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Performance Metrics — Example

Machine A runs a program in 10 seconds
and machine B runs the same program in 15
seconds. Therefore:
Execution time 15
B
n=
Execution time
= ( 10 ) = 1.5
A

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Performance Metrics
Average Execution time — Equal probability of
running programs in the workload

n
1
∑
n i =1 Timei

Where Timei is the execution time of the ith program

And n is the number of the program in the workload.

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Performance Metrics
Weighted Execution time — unequal mix of
programs in the workload
where weighti is the frequency of the ith gram
in the workload.
n

∑Weight ×Time
i =1
i i

n
Note
∑Weight
i =1
i
=1
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Performance Metrics
Million Instructions Per Second — MIPS is
another performance measure to be used to
evaluate computers.

I
C
MIPS =
6
Execution time * 10

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Performance Metrics
Million Floating Point Operations Per Second
— MFLOPS
is another performance measure to be used to
evaluate computers.
Number of floating point operations in a program
MFLOPS =
Execution time * 106

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Performance Metrics
Response Time (Elapse time) — The latency to
complete a task, including disk accesses,
memory accesses, I/O activities, operating
system overhead, ...

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Performance Metrics
CPU time — The time the CPU is computing.
It is further divided into:
User CPU time — The CPU time spent in the
program,
System CPU time — The CPU time spent in
operating system performing tasks requested by the
program.

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Performance Metrics
The processor of today's computer is driven by
a clock with a constant cycle time (τ).
The inverse of the cycle time is the clock rate
(f).
The size of a program is determined by its
instruction count (Ic) — number of the machine
instructions to be executed.

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Performance Metrics
Let us define the average number of clock
cycle per instruction (CPI) as:

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Performance Metrics
For a given instruction set, one can calculate the
CPI over all instruction types, if the frequencies of
the appearance of the instructions in the program is
known.
CPI depends on the organization/architecture and
the instruction set of the machine.
Clock rate depends on the technology and
organization/architecture of the machine.
Instruction count depends on the instruction set of
the machine and compiler technology.

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Performance Metrics
CPU = CPU * Clock
Ti me Clock cycl es Cycle tim e

CPU
Clock cycl es
CPU =
Ti me Clock
Rate

The CPU time is estimated as

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Performance Metrics — Example

It takes 10 seconds to run a program on
machine A that has a 400 MHz clock rate.
We are intended to build a faster machine that
will run this program in 6 seconds. However,
machine B requires 1.2 times as many clock
cycles as machine A for this program.
Calculate the clock rate of machine B:

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Performance Metrics — Example

=
CPUClockCycle
CpuTime A
A
ClockRate A

10 =
CPUClockCycle A

400 *10 Cycles

6
Second

= 4000 *10
6
CPUClockCycle A
1.2 * CPUClockCycle
CPUTimeB = A
ClockRate B

6
1.2 * 4000 *10
ClockRate = = 800 MHz
B 6
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Performance Metrics — Example

Suppose we have two implementation of the same
instruction set architecture. Computer A has a clock
cycle time of 250 ps and a CPI of 2.0 for some
program, and computer B has a clock cycle time of 500
ps and a CPI of 1.2 for the same program.
Which computer is faster for this program?

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Performance Metrics — Example

 We know that both machines execute the same number of
instructions, say I.

CPU TimeA= CPUClockCyclesA * ClockCycleTimeA

= I * 2.0 * 250 ps = 500 * I ps
CPU TimeB= CPUClockCyclesB * ClockCycleTimeB
= I * 1.2 * 500 ps = 600 * I ps

 Clearly A is faster than B.

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Performance Metrics — Example

 Assume we have the following information for different classes
of operations:
Class Class Class
A B C
CPI 1 2 3

 Also assume the same code segment with different instruction

mix:
Code Sequence Instruction Counts
A B C
1 2 1 2
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2 4 1 1
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Performance Metrics — Example

Refer to the previous example, which code is faster?
CPUClockCycle1 = (2*1) + (1*2) + (2*3) = 10
CPUClockCycle2 = (4*1) + (1*2) + (1*3) = 9
So code sequence 2 is faster, however, note that code
sequence2 has more instructions than code sequence1.

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Performance Metrics
The execution of an instruction requires
going through the instruction cycle. This
involves the instruction fetch, decode,
operand(s) fetch, execution, and store
result(s):

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Performance Metrics
P is the number of processor cycles needed to
decode and execute the instruction, m is the
number of the memory references needed, and k
is the ratio between memory cycle time and
processor cycle time, memory latency.

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Question
With respect to our earlier definition of
CPU time, discuss how the performance can
be improved?

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In response to this question, the CPU time

can be reduced either by reducing the IC
and/or CPI.
Note the performance improvement due to
the advances in technology to reduce τ is
beyond the scope of this discussion.

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Two Design philosophies

IC can be reduced by increasing the
functionality of the system — increasing the
instruction set by allowing hardware support
for more complex instructions.
This design pattern results in the so-called
complex instruction set computer (CISC).

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Two Design philosophies

CPI can be reduce by allowing hardware
support for just simple instructions.
This design pattern results in the so-called
reduced instruction set computer (RISC).

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Two Design philosophies

In an effort to improve the performance one
design philosophy suggest complexity and the
other suggest simplicity!

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Complex Instruction Set Computer

In general, Complex Instruction Set Computer
(CISC) supports:
Relatively large instruction set containing some
complex and time consuming instructions.
Large number of addressing modes.
Large number of instruction formats.

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Reduced Instruction Set Computer

Functions should be kept simple unless there is a
very good reason to do otherwise.
Micro instructions should not be faster than simple
instructions.
Simple decoding and pipelined execution are more
important than program size.
Compiler technology should be used to simplify
instructions rather than to generate complex
instructions.
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Reduced Instruction Set Computer

Common RISC Features
Operations are register-to-register with only LOAD
and STORE instructions to access memory.
The operations and addressing modes are reduced.
Instruction formats are simple and do not cross word
boundaries.
RISC branches avoid pipeline penalties.

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CISC Characteristics
Instruction set usually larger than 100,
Number of addressing modes supported is
usually larger than 4,
Number of instruction formats supported in
usually larger than 4,
Most instructions require multiple cycles for
execution,

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CISC Characteristics
Support of memory-to-memory model of
execution,
Existence of special purpose registers,
Micro-programmed control unit, and
Machine instructions at a relatively high
level, which is close to the level of high
level language statements.

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RISC Characteristics
Most instructions require single cycle for
execution,
Memory is accessed just through LOAD and
STORE instructions,
Hardwired control unit,
Supports relatively few instruction formats and
addressing modes,

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RISC Characteristics
Fixed instruction length format,
Highly pipelined instruction cycle,
Large number of on chip registers,
Instruction set is targeted for a specific
application, and
Use of co-processor for complex operations
requiring hardware support.

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RISC vs. CISC

RISC allows performance improvement
through careful design of the data path, pipeline
and other CPU resources.
RISC offers fewer clock cycles per instruction.
RISC is more suitable for current technology.
RISC might imply specialization.

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RISC vs. CISC

For the same program RISC requires larger
assembly code than CISC.
From software reliability point of view, RISC
has a disadvantage.

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RISC vs. CISC

Back to our original question — based on the
equation

what is a better design philosophy, RISC or CISC?

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Questions
True or False: shorter length instructions imply
faster processor (why)?
Length of the operation code affects the length
of the instructions. Define two schemes which
allows one to reduce the length of the op-code.
Name and explain different factors which affect
the length and format of an instruction.

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