COMPUTER

ORGANISATION AND
ARCHITECTURE
2017 MAY – JUNE OLD QUESTION PAPER

LECTURE: T.MAHARSHI SANAND YADAV

Done By : A .Rahul (5301)
C .Rohith (5303)
G .Sandeep Kumar (5305)
L .Manikanth (5005)
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FACULTY OF ENGINEERING

B.E. 3/4 (ECE) II - Semester (Old) Examination, May / June 2017

Subject: Computer Organization and Architecture
Max. Marks: 75

Note: Answer all questions from Part - A and answer any five questions from Part-B.

PART-A (25 Marks)

1. Show the hardware for Booths multiplier. 2M

2. Derive an algorithm for floating point multiplication. 3M
3. Explain various phases of an instruction cycle. 3M
4. What are the two instructions needed in the basic computer in order to set the E flip-flop. 2M
5. What is the basic difference between a CALL subroutine and program interrupt instructions. 3M
6. Distinguish between RISC and CISC processors. 2M
7. What is the basic advantage of using interrupt initiated data transfer under program control without
an interrupt? 3M
8. Compare and contrast between synchronous and asynchronous communication. 2M
9. How many 128X8 RAM chips needed to provide memory capacity of 2048 bytes? 2M
10. Distinguish between SRAM and associative memory. 3M

PART-B (50 Marks)

11. a) Draw the flow chart for signed addition/subtraction and also draw the hardware required for that
7M
b)What are the difficulties of floating point representation? 3M

12. a) Explain timing and control unit of the general purpose computer. 5M
b) What is the program interrupt? Explain interrupt cycle in the computer. 5M

13. a) Draw the space time diagram for a four-segment pipeline showing the time it takes to process five
tasks. 6M
b) Explain various addressing modes in the general purpose computer. 4M

14. a) What are the different modes in DMA transfer? Explain operation of each mode. 5M
b) Explain CPU-IOP communication. 5M

15. Explain various address mapping techniques of the cache memory. 10M

16. a) Draw the flow chart for fixed point division algorithm. 5M
b) Explain Daisy-chain interrupt priority scheme. 5M

17. Write short notes on

a)stack organization 2M
b) Array processor 5M
c) Memory hierarchy 3M

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PART-A (25 Marks)

Q1) Show the hardware for Booths multiplier? (2M)
A)
It consists of an n-bit adder, control logic and four registers A, B, Q and Q-1.Multiplier and
Multiplicand are loaded into register Q and register B respectively Register A & Q-1 are initially
set to 0. The n-bit adder performs addition, inputs of adders comes from multiplicand and
content of register A. In case of addition, Add/Sub line is 0, therefore, Cin= 0 and multiplicand is
directly applied as a second input to the n-bit adderIn case of subtraction, Add/sub line is 1,
therefore Cin= 1 and multiplicand is complemented and then applied to the n-bit adder. As a
result, the 2’s complement of the multiplicand is added to the contents of register A.

Q2) Derive an algorithm for floating point multiplication?(3M)

A)
Assuming that the operand are already in the IEEE 754 format performing the floating
point multiplication
Result=R=X*Y=(-1)xs(Xm*2xe)*((-1)ys(Ym^2ye)
Involves the following steps:
1)If one or both operand are equal to zero , return the result as zero, otherwise
2)Compute the sign of the result Xs XOR Ys
3)Compute the mantissa of the result:
 Multiply the mantissa : Xm*Ym
 Round the result to the allowed number of mantissa bits
4)Compute the exponent of the result:
Ressult exponent =biased exponent(X0+biased exponent (Y) – bias
5)Normalize if needed ,by shifting mantissa right ,incrementing result exponent.
6)Check result exponent for overflow/underflow:
 If larger than maximum exponent allowed return exponent overflow
 If smaller than minimum exponent allowed return exponent underflow.

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Q3)Explain various phases of an instruction cycle?(3M)

A)
Instruction Cycle:
A program residing in the memory unit of a computer consists of a sequence of instructions.
These instructions are executed by the processor by going through a cycle for each instruction.
In a basic computer, each instruction cycle consists of the following phases:
1. Fetch instruction from memory.

2. Decode the instruction.

3. Read the effective address from memory.

4. Execute the instruction.

Fetch Instruction

Execute The Decode

Instruction
Instruction
INSTRUCTION CYCLE
Read Address From
The Memory

Q4)What are the two instructions needed in the basic computer

in order to set the E flip-flop. 2?(2M)
A)
The two instructions needed in the basic computer in order to set the E Flip-Flop are

Clear E

Complement E

Q5)What is the basic difference between a CALL subroutine and

program interrupt instructions?(3M)

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A)

SUBROUTINUE INTERRUPT
 Initiated by execution of some  Initiated by some external or
instruction. Internal signal.
 Address of subroutine determined  Address of the interrupt service
from the address part of the routine determined by the hardware.
instruction.  Interrupt procedure stores all
 Only the value of the PC stored before information to describe the state of
branching to the subroutine. the CPU.
 Call occurs at the specific and  Can ask for notice without prior
predetermined locations in the main Notice.
routine.
 Software initiated.  Hardware initiated.

Q6). Distinguish between RISC and CISC processors?(2M)

A)

BASIS FOR RISC CISC

COMPARISON

Emphasis on Software Hardware

Includes Single clock Multi-clock

Instruction-set size Small Large

Instruction formats fixed (32-bit) format Varying formats (16-64 bits

each instruction).

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Addressing modes used Limited to 3-5 12-24

General purpose registers 32-192 8-24

used

Cycles Per Instruction Single cycle for all instructions and CPI between 2 and 15.

an average CPI < 1.5.

Q7). What is the basic advantage of using interrupt initiated

data transfer under program control without an interrupt?(3M)
A)In the interrupt initiated data transfer, the processor verifies the request and transfer the
control ISR to perform the task and its resumes back with the useful task while, the processor
has to waste its time by performing all the task, for example when a print command is given in
the interrupt initiated , it gives control over to ISR and resumes the work back where as without
interrupt the processor has to wait unless the print document is transferred to the printer.

Q8)Compare and contrast between synchronous and

asynchronous communication.?(2M)
A)

Basics For Synchronous Asynchronous

Comparision Transmission transmission
Meaning Transmission starts with the block It uses start bit and stop bit
header which holds a sequence of preceding and following a character
bits. respectively.
Transmission Sends data in the form of blocks Sends 1 byte or character at a time
manner or frames
Synchronization Present with the same clock Absent
pulse.
Synchronization Present with the same clock Absent
pulse.
Cost Expensive Economical

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Examples Chat Rooms, Video Conferencing, Letters, emails, forums, etcetera.

Telephonic Conversations,
etcetera.

Q9)How many 128X8 RAM chips needed to provide memory

capacity of 2048 bytes?(2M)
A) Now,
1 RAM Chip = 128 Byte
Thus, N RAM Chips = 2048 Bytes

Cross Multiplying the equations

128 * n = 2048

Thus, n = 16
Therefore total number of chips required to provide the storage capacity of 2048 Bytes is
16 Chips

Q10) Distinguish between SRAM and associative memory?(3M)

A)

S.NO RAM MEMORY ASSOCIATIVEMEMORY(CAM)

1. RAM stands for Random Access It stands for Content Addressable Memory.

Memory.

2. In RAM, the user supplies a In associative memory, the user supplies data

memory address and RAM word and associative memory searches its entire

returns data word stored at the memory.

address.

3. The price of RAM is low as It is expensive than RAM.

compared to Associative

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memory.

4. It is used to store running It is widely used in database management system.

applications(programs) and

program’s data for performing

operation.

5. This is suitable for algorithm This is suitable for parallel search.

based search via PRAM. PRAM

stands for Parallel-RAM.

6. If the data word is found, RAM If the data word is found, It returns the list of

returns the data word. addresses where that data word was located.

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PART-B (50 Marks)

Q11)a)Draw the flow chart for signed addition/subtraction and
also draw the hardware required for that?(7M)
A) FLOW CHART
Subtract Operation Add Operation

Minuend is A Augend is A
Subtrahend is B Addend is b

=0 =1 =1 =0
As+Bs As+Bs
As=Bs As=Bs As=Bs
As=Bs
EA A+B+1
AVF 0 EA A+B

=0 =1
E Avf e
A<B A>B

=0 =0
A A
A

A A+1
As As
As 0

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HARDWARE DESIGN

Bs B Register

Mode Control
Complementer
AVF
Input

E Parralel Adder Carry

S
Output Load
A Register
As Carry Sum

We designate the magnitude of the two numbers by A and B. Where the signed numbers are
added or subtracted, we find that there are eight different conditions to consider, depending
on the sign of the numbers and the operation performed

When the signs of A and B are same, add the two magnitudes and attach the sign of result is
that of A. When the signs of A and B are not same, compare the magnitudes and subtract the
smaller number from the larger. Choose the sign of the result to be the same as A, if A > B or
the complement of the sign of A if A < B. If the two magnitudes are equal, subtract B from A and
make the sign of the result will be positive

 The signs use an exclusive OR gate where if the output is 0, then the signs are the same.
 Hence , add the magnitude of the same signed numbers . If the sum is an overflow, then
a carry is stored in E where E=1 and transferred to the flip-flop AVF, add-overflow.
 Otherwise, the signs are opposite and subtraction is initiated and stored in A.
 NO overflow is occurred with subtraction so AVF is cleared.
 If E=1 , then A >/ B.

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 However, If A=0 ,then A=B and the sign is made positive.

 If E=0. Then A<B and sign for A is complemented.

Q11)b)What are the difficulties of floating point representation?(3M)

A)
1)You can only represent numbers of the form y + x / 2 i .

2)Other fractions (rationals) have repeating bit representations

3)Irrationals have infinite, non-repeating representations

4)IEEE Floating Point has Clear Mathematical Properties Represents numbers of the form ±M ×
2E .

5)Can reason about operations independent of implementation: as if computed with perfect

precision and then rounded.

12. a) Explain timing and control unit of the general purpose

computer?(5M)
A)
• CPU is partitioned into Arithmetic Logic Unit (ALU) and Control Unit (CU)
• The function of control unit is to generate relevant timing and control signals to all operations
in the computer.
• It controls the flow of data between the processor and memory and peripherals
• The control unit directs the entire computer system to carry out stored program instructions.
• The control unit must communicate with both the arithmetic logic unit (ALU) and main
memory.
• The control unit instructs the arithmetic logic unit that which logical or arithmetic operation is
to be performed.
• The control unit co-ordinates the activities of the other two units as well as all peripherals
and auxiliary storage devices linked to the computer.
• Control unit generates control signals using one of the two organizations:
1) Hardwired Control Unit
2 )Micro-programmed Control

HARDWIRED CONTROL UNIT:

• It is implemented as logic circuits (gates, flip-flops, decoders etc.) in the hardware
• This organization is very complicated if we have a large control unit.

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• In this organization, if the design has to be modified or changed, requires changes in the
wiring among the various components. Thus the modification of all the combinational circuits
may be very difficult.
• An instruction read from memory is placed in the instruction register (IR).
• The instruction register is divided into three parts: the I bit, operation code, and address part.
• First 12-bits (0-11) to specify an address, next 3-bits specify the operation code (opcode) field
of the instruction and last left most bit specify the addressing mode I. I = 0 for direct address I =
1 for indirect address
INSTRUCTION REGISTER (YR)

15 14 13 12 11 - 0 Other Inputs

3 * 8 Decoder Control Control

Outputs
7 6 5 4 3 2 1 0
D0 Logic
D7
Gate
I
T15
T0

15 14 ……………………2 1 0

4 * 16 Decoder

4 – bit Increment(INR)
Sequence Clear(CLR)
Counter(SC) Clock

• First 12-bits (0-11) are applied to the control logic gates. • The operation code bits (12 – 14)
are decoded with a 3 x 8 decoder.
• The eight outputs ( D0 through D7) from a decoder goes to the control logic gates to perform
specific operation.
• Last bit 15 is transferred to a I flip-flop designated by symbol I

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• The 4-bit sequence counter SC can count in binary from 0 through 15.
• The counter output is decoded into 16 timing pulses T0 through T15. • The sequence counter
can be incremented by INR input or clear by CLR input synchronously.
• For example: Consider the case where SC is incremented to provide timing signals T0, T1, T 2 ,
T3, and T4 in sequence. At time T4 , SC is cleared to 0 if decoder output D3 is active. This is
expressed symbolically by the statement: D3 T4 : SC ← 0
• The timing diagram shows the time relationship of the control signals.

T0 T1 T2 T3 T4 T0

CLOCK

T0

T1

T2

T3

T4

D3

CLR
SC

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ADVANTAGES:
• Hardwired Control Unit is fast because control signals are generated by combinational
circuits.
• The delay in generation of control signals depends upon the number of gates.
DISADVANTAGES:
• More is the control signals required by CPU; more complex will be the design of control unit.
• Modifications in control signal are very difficult. That means it requires rearranging of wires in
the hardware circuit.
• It is difficult to correct mistake in original design or adding new feature in existing design of
control unit.

Q12)b) What is the program interrupt? Explain interrupt cycle in the

computer?(5M)
A) Program Interrupt:
An interrupt is a signal from a device attached to a computer or from a program within the
computer that requires the operating system to stop and figure out what to do next. Almost all
personal (or larger) computers today are interrupt-driven - that is, they start down the list of
computer instructions in one program (perhaps an application such as a word processor) and
keep running the instructions until either (A) they can't go any further or (B) an interrupt signal
is sensed. After the interrupt signal is sensed, the computer either resumes running the current
program or begins running another program.

Interrupt Cycle:
An instruction cycle (sometimes called fetch-and-execute cycle, fetch-decode-execute cycle, or
FDX) is the basic operation cycle of a computer. It is the process by which a computer retrieves
a program instruction from its memory, determines what actions the instruction requires, and
carries out those actions. This cycle is repeated continuously by the central processing unit
(CPU), from bootupto when the computer is shut down.

Execute Fetch Interrupt

Check the
Fetch Next Execute interrupt ;process
START Instruction Instruction the interrupt

HALT
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START

LOAD ADDRESS TO THE

PC

LOAD PC CONTENT
TO THE MAR

UPDATE PC TO NEXT
ADDRESS

LOAD DATA
REQUIRED TO MDR

MAR CONTENTS TO
CIR

DECODE CIR
CONTENTS

YES
SET PC TO VALUE FROM
JUMP JUMP INSTRUCTION

NO
EXECUTE INSTRUCTION

NO YES SERVICE
INTERRUPT INTERRUPT
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 After the execute cycle is completed, a test is made to determine if an interrupt was
enabled (e.g. so that another process can access the CPU)
 If not, instruction cycle returns to the fetch cycle
 If so, the interrupt cycle might performs the following tasks: (simplified...)
 move the current value of PC into MBR
 move the PC-save-address into MAR
 move the interrupt-routine-address into PC
 move the contents of the address in MBR into indicated memory cell
 continue the instruction cycle within the interrupt routine
 after the interrupt routine finishes, the PC-save-address is used to reset the value of PC
and program execution can continue

Q13)a) Draw the space time diagram for a four-segment pipeline

showing the time it takes to process five tasks?(6M)

A)

CLOCK

INPUT

S 1
R1
S 2
R2
S 3
R3
S 4
R4

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1 2 3 4 5 6 7 8

FI DA FO EX
No
FI DA FO EX
Of

Task FI DA FO EX
FI DA FO EX
FI DA FO EX
NO Of Segments

FIG : SPACE-TIME DIAGRAM

• Any operation that can be decomposed into a series of suboperations of the
same complexity can be implemented by pipelining.
• We define a task as the total operation that performing when going through
the entire pipeline.
• Given a k-segment pipeline with a clock cycle of tp that is used to execute n
tasks.
– The first task requires ktp to complete the operation.
– The remaining tasks are completed one per clock cycle, requiring an additional
(n-1)tp
. – The total execution time is (k + n-1)tp
 A non pipelined unit would require ntn to complete these tasks.
 The speedup is the ratio S = ntn (k + n – 1)tp
 The formula for No of Cycles is K+(N-1)
 In the pipelining one task starts from the first clock pulse and the next task starts form
the 2nd clock pulse and in the next task starts from the 3rd clock pulse and goes on…
 Here we can get to know that in pone task 4 segment would be completed
 In the next instruction again the four segments starts form the 2 segment of the first
task.
 In the same way the 3rd instruction starts at the 2nd segment of the 2nd task.
 In the same way the 4th tasks starts from the 2nd segment of the task 3.
 In the same way the 5th task starts again from the 2nd segment of the task 4.
 In this way we can get to know one thing that in the pipelining the clock pulse can be
used in the appropriate way which makes the efficient way of using clock pulses.

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 So in the 4 segment pipeline with 5 tasks , total of 8 clock pulses.

Q13)b) Explain various addressing modes in the general purpose

computer?(4M)

A) Types Of Addressing Modes:

Various types of addressing modes are:
1 Implied and Immediate Addressing Modes
2 Direct or Indirect Addressing Modes
3 Register Addressing Modes
4 Register Indirect Addressing Mode
5 Auto-Increment and Auto-Decrement Addressing Modes
6 Displacement Based Addressing Modes

1) a)Implied Addressing Mode:

Implied Addressing Mode also known as "Implicit" or "Inherent" addressing mode is the
addressing mode in which, no operand(register or memory location or data) is specified in the
instruction.

b)Immediate Addressing Mode:

In Immediate Addressing Mode operand is specified in the instruction itself. .In other words an
immediate mode instruction has an operand field rather than an address field, which contain
actual operand to be used in conjunction with the operand specified in the instruction.That is,
in this mode, the format of instruction is:
INSTRUCTION

OPCODE OPERAND
2)a) Direct Addressing Mode:
Direct Addressing Mode is also known as “Absolute Addressing Mode”.In this mode the address
of data(operand) is specified in the instruction itself.That is, in this type of mode, the operand
resides in memory and its address is given directly by the address field of the instruction.

b)Indirect Addressing Mode:

In this mode, the address field of instruction gives the memory address where on, the operand
is stored in memory.That is, in this mode, the address field of the instruction gives the address
where the “Effective Address” is stored in memory. i.e., EA=(A)

3.Register Addressing Mode:

In Register Addressing Mode, the operands are in registers that reside within the CPU.That is,
in this mode, instruction specifies a register in CPU, which contain the operand.It is like Direct

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Addressing Mode, the only difference is that the address field refers to a register instead of
memory location. i.e., EA=R

INSTRUCTION
OPCODE R REGISTER

R OPERAND

4.Register Indirect Addressing Mode:

In Register Indirect Addressing Mode, the instruction specifies a register in CPU whose
contents give the operand in memory.In other words, the selected register contain the address
of operand rather than the operand itself.That is, i.e., EA=(R)

INSTRUCTION
REGISTER
OPCODE R
REGISTER MEMORY
1000 OPERAND
R 1000

5)a) Auto-increment Addressing Mode:

Auto-increment Addressing Mode are similar to Register Indirect Addressing Mode except that
the register is incremented after its value is loaded (or accessed) at another location like
accumulator(AC).That is, in this case also, the Effective Address is equal to EA=(R)

b) Auto-increment Addressing Mode:

Auto-increment Addressing Mode are similar to Register Indirect Addressing Mode except
that the register is incremented after its value is loaded (or accessed) at another location like
accumulator(AC).That is, in this case also, the Effective Address is equal to EA=(R)

6.Displacement Based Addressing Modes:

Displacement Addressing Modes requires that the instruction have two address fields, at least
one of which is explicit means, one is address field indicate direct address and other indicate
indirect address.That is, value contained in one addressing field is A, which is used directly and

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the value in other address field is R, which refers to a register whose contents are to be added
to produce effective address.

14.a)What are the different modes in DMA transfer? Explain

operation of each mode?(5M)
A) DMA Controller: Data Transfer Modes:
The DMA controller functions as a bus master and bus slave. It performs data transfer operationsIn I/O
data transfer, data is transferred by using microprocessor. The microprocessor will read data from I/O
device and then will write data to memory.In this case, there are two operations for single data transfer.
If the data is less then microprocessor will not waste its time transferring data from I/O to memory or
back.But suppose data is huge then the transfer rate from I/O to memory or back will slow down
because of microprocessor intervention.In such case, to speed up the process of transferring the data,
I/O should have direct access to memory.It can have Direct Memory Access (DMA) but under
supervision. The device which supervises data transfer is named as DMA controller.
DMA controlled input/output is further divided into the following categories:
1. Burst or Block Transfer DMA-
o It is the fastest DMA mode.
o In this mode, two or more data bytes are transferred continuously.
o The microprocessor is disconnected from the system bus during DMA transfer
i.e. the microprocessor cannot execute its own program during this transfer.
o N number of DMA cycles are added into the machine cycles of the
microprocessor where N is number of bytes to be transferred.
o In this mode, the DMA controller sends HOLD signal to the microprocessor and
waits for HLDA signal.
o After receiving HLDA signal, the DMA controller gains control of the system bus
and execute a DMA cycle to transfer one byte.
o After transferring one byte, it increments memory address, decrements counter
and transfers next byte.
o In this way, it transfers all data bytes between memory and I/O devices. After
transferring all data bytes, the DMA controller disables HOLD signal and enters in
to slave mode.
2. Cycle Steal or Single Byte Transfer DMA-
o In cycle steal transfer only one byte of data is transferred at a time.
o This type of DMA is slower than burst DMA.
o In this mode, only one DMA cycle is added between two machine cycles of the
microprocessor, hence the instruction execution speed of the microprocessor is
reduced slightly.
o In this mode the DMA controller sends HOLD signal to the microprocessor and
waits for HLDA signal.
o After receiving HLDA signal, the DMA controller gains control of the system bus
and execute only one DMA cycle.

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o After transferring one byte, it disables HOLD signal and enters into slave mode.
o The microprocessor then gains control of the system bus and executes next
machine cycle. If the count is not zero and next data is available then the DMA
controller sends HOLD signal to the microprocessor and transfers next byte of
data block.
3. Transparent or Hidden DMA Transfer-
o The microprocessor executes some states during which it floats the address and
data buses.
o During these states, the microprocessor is isolated from the system bus.
o The DMA controller transfers data between memory and I/O devices during
these states. This operation is transparent to microprocessor.
o This is the slowest DMA transfer. In this mode, the instruction execution speed
of microprocessor is not reduced. But the transparent DMA requires logic to
detect the states when the microprocessor is floating the buses.

Q14)b) Explain CPU-IOP communication.?(5M)

A)
Intel 8089 is an I/O support processor for Intel 8086-based systems. Itconsists of two
independent DMA channels. Corresponding to each channelthere is an I/O address
register(IOAR) and a data word count register (DC),just as in any DMA controller. In
addition,there is a program counter (PC)and other registers that are used in executing IOP
programs. The CPU viewsthe 8089 as two independent IOPs since the two DMA channels can
executedifferent I/O programs concurrently.

The IOP is interfaced to the 8086 system bus using a bus interface unit,as shown in Fig.
6.39. There is a 20-bit arithmetic-logic unit (ALU) that isused for address computations and an
assemble/disassemble unit that isused to change a 16-bit data unit into two 8-bit units and vice
versa, duringthe 8- and 16-bit data transfers. In Fig. 6.39, the IOP is attached to a 20-bit
Input/Output 33 data/address bus onto which all the other peripheral devices and
systemmemory are attached. The address and data are time-multiplexed on the20-bit
data/address bus. It is possible to configure a system with a separate I/O bus between the IOP
and the peripheral devices as shown in Fig. 6.40,thereby reducing the traffic on the system bus.
If such a local I/O bus is used, the IOP programs can be stored in the local memory attached to
the localbus, thereby further reducing the traffic on the system bus.

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Figure 6.39 CPU-8089 IOP interface

Figure 6.41 shows the memory organization needed for the CPU/IOP communications.
Corresponding to each DMA channel in the IOP, there is a channel control block (CB) consisting
of a pointer to that channel’s para-meter block (PB), a channel status word, and a channel
command word. The PB pointer points to the PB of the channel, which contains a pointer to the
I/O program and all the required parameters for the I/O program. These parameterscorrespond
to the device addresses, memory buffer addresses, and so on.
The CPU first tests the channel through the status word, establishes
the command word and parameters in the PB, and commands the channelto start the I/O
through the ATTENTION CHANNEL signal. The336 Chapter 6 CHANNEL SELECT is used to select
one of the two channels. Once the I/O is complete, the channel produces an interrupt for the
CPU.

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CHANNEL SELECT

CHANNEL Attn IOP

CPU
INTERRUPT

BUS

CONTROLLER

SYSTEM I/O
BUS DEVICES

MEMORY
IOP BUS

Figure 6.40 CPU-IOP interface with separate I/O bus

The CPU uses its IN and OUT (if the IOP is configured in the I/Oaddress space) or MOVE
instructions (if the IOP is configured for memorymapped I/O) to establish command word and
PB to sense the status of theIOP. The IOP instruction set consists of mainly data transfer
instructionsthat move data between its internal registers and the system bus. It can
Input/Output 337 perform fixed-point arithmetic (add, increment, and decrement) and has a
limited set of program control instructions. The IOP supports memory to memory block
transfers in addition to the data transfer between I/O devices and the memory.

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Figure 6.41 Main memory organization for Intel 8089

Q15) Explain various address mapping techniques of the cache

memory?(10M)
A)
Cache Mapping:There are three different types of mapping used for the purpose of
cache memory which are as follows: Direct mapping, Associative mapping, and Set-Associative
mapping. These are explained below.
1)Direct Mapping –
The simplest technique, known as direct mapping, maps each block of main memory into only
one possible cache line. or
In Direct mapping, assigne each memory block to a specific line in the cache. If a line is
previously taken up by a memory block when a new block needs to be loaded, the old block is
trashed. An address space is split into two parts index field and a tag field. The cache is used to
store the tag field whereas the rest is stored in the main memory. Direct mapping`s
performance is directly proportional to the Hit ratio.
i = j modulo m

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where
i=cache line number
j= main memory block number
m=number of lines in the cache
For purposes of cache access, each main memory address can be viewed as consisting of three
fields. The least significant w bits identify a unique word or byte within a block of main
memory. In most contemporary machines, the address is at the byte level. The remaining s bits
specify one of the 2s blocks of main memory. The cache logic interprets these s bits as a tag of
s-r bits (most significant portion) and a line field of r bits. This latter field identifies one of the
m=2r lines of the cache.

MAIN MEMORY TAG WORD-OFFSET

CACHE MEMORY
TAG LINE-OFFSET WORD-OFFSET

MAIN MEMORY PAGES

SET(0)

BLOCK FRAME SET(1)

DATA
CACHE

CONTROL
SET((S-1)
LOGIC

CPU

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2)Associative Mapping –
In this type of mapping, the associative memory is used to store content and addresses of the
memory word. Any block can go into any line of the cache. This means that the word id bits are
used to identify which word in the block is needed, but the tag becomes all of the remaining
bits. This enables the placement of any word at any place in the cache memory. It is considered
to be the fastest and the most flexible mapping form.

MAIN MEMORY

SET(0)

BLOCK FRAME

………
BLK(0) BLK(1) ……. BLK(N-1)

CACHE
CPU
CONTROL

LOGIC

3)Set-associative Mapping –
This form of mapping is an enhanced form of direct mapping where the drawbacks of direct
mapping are removed. Set associative addresses the problem of possible thrashing in the direct
mapping method. It does this by saying that instead of having exactly one line that a block can
map to in the cache, we will group a few lines together creating a set. Then a block in memory
can map to any one of the lines of a specific set..Set-associative mapping allows that each word
that is present in the cache can have two or more words in the main memory for the same
index address. Set associative cache mapping combines the best of direct and associative cache
mapping techniques.
In this case, the cache consists of a number of sets, each of which consists of a number of lines.
The relationships are

m=v*k

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i= j mod v
where
i=cache set number
j=main memory block number
v=number of sets
m=number of lines in the cache number of sets
k=number of lines in each set

MAIN MEMORY TAG WORD-OFFSET

CACHE MEMORY
TAG SET-OFFSET WORD-OFFSET

MAIN MEMORY
BLK(N-1)

BLK(0) BLOCK FRAME

………..
SET(0) ………..
………..
………..
……….. SET(N-1)
………..

CACHE CPU

CONTROL

LOGIC
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16 a) Draw the flow chart for fixed point division

algorithm.(5M)
A)
BR DIVISOR

AC DIividend

=0
BR
=0
Divide by
=0
0
AC

=0
QR 0 QS AS+BS
Q 0
SC N-1

EA A+B +1

1 E
0

A>=B A<B

A A+B A A+B
Shr A
A a+1

a a+b +1
a a + bias
q a

Divide Magnitude Of Mantissa As In Fixed Point Numbers

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Q16)b) Explain Daisy-chain interrupt priority scheme?(5M)

A) The daisy-chaining method involves connecting all the devices that can request an interrupt
in a serial manner. This configuration is governed by the priority of the devices. The device with
the highest priority is placed first followed by the second highest priority device and so on. The
given figure depicts this arrangement.

Processor Data Bus

VAD 1 VAD 2 VAD 3

DEVICE 1 DEVICE 2 DEVICE 3

To Next Device
P1 P1 P0 P1 P0
P0

CPU
Interrupt Request
INT

Interrupt Acknowledge

INT ACK

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WORKING:
There is an interrupt request line which is common to all the devices and goes into the CPU.

When no interrupts are pending, the line is in HIGH state. But if any of the devices raises an
interrupt, it places the interrupt request line in the LOW state.

The CPU acknowledges this interrupt request from the line and then enables the interrupt
acknowledge line in response to the request.

This signal is received at the PI(Priority in) input of device 1.

If the device has not requested the interrupt, it passes this signal to the next device through its
PO(priority out) output. (PI = 1 & PO = 1)

However, if the device had requested the interrupt, (PI =1 & PO = 0)

The device consumes the acknowledge signal and block its further use by placing 0 at its
PO(priority out) output.

The device then proceeds to place its interrupt vector address(VAD) into the data bus of CPU.

The device puts its interrupt request signal in HIGH state to indicate its interrupt has been taken
care of.

NOTE: VAD is the address of the service routine which services that device.

If a device gets 0 at its PI input, it generates 0 at the PO output to tell other devices that
acknowledge signal has been blocked. (PI = 0 & PO = 0)

Hence, the device having PI = 1 and PO = 0 is the highest priority device that is requesting an
interrupt. Therefore, by daisy chain arrangement we have ensured that the highest priority
interrupt gets serviced first and have established a hierarchy. The farther a device is from the
first device, the lower its priority.

17. Write short notes on

a)Stack organization(2M) b) Array processor(5M)
c) Memory hierarchy?(3M)

A)a)
STACK ORGANISARION:
Stack is a storage structure that stores information in such a way that the last item stored is the

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first item retrieved. It is based on the principle of LIFO (Last-in-first-out). The stack in digital
computers is a group of memory locations with a register that holds the address of top of
element. This register that holds the address of top of element of the stack is called Stack
Pointer.
Stack Operations:

The two operations of a stack are:

1. Push : Inserts an item on top of stack.
2. Pop : Deletes an item from top of stack
.
Implementation of Stack
In digital computers, stack can be implemented in two ways:

1. Register Stack

2. Memory Stack

Register Stack:
A stack can be organized as a collection of finite number of registers that are used to
store temporary information during the execution of a program. The stack pointer (SP) is
a register that holds the address of top of element of the stack.

Memory Stack:
A stack can be implemented in a random access memory (RAM) attached to a CPU. The
implementation of a stack in the CPU is done by assigning a portion of memory to a stack
operation and using a processor register as a stack pointer. The starting memory location of
the stack is specified by the processor register as stack pointer.

A) b) Vector(Array) Processor and its Types:

Array processors are also known as multiprocessors or vector processors. They
perform computations on large arrays of data. Thus, they are used to improve the
performance of the computer.

There are basically two types of array processors:

1 Attached Array Processors
2 SIMD Array Processors

1)Attached Array Processors:

An attached array processor is a processor which is attached to a general purpose
computer and its purpose is to enhance and improve the performance of that computer

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in numerical computational tasks. It achieves high performance by means of parallel

processing with multiple functional units.

General purpose Attached Array

I/O Interface
Copmuter Processor

Main Local Memory

High speed memory to Memory bus
Memory

2)SIMD Array Processors:

SIMD is the organization of a single computer containing multiple processors operating
in parallel. The processing units are made to operate under the control of a common
control unit, thus providing a single instruction stream and multiple data streams.
A general block diagram of an array processor is shown below. It contains a set of
identical processing elements (PE's), each of which is having a local memory M. Each
processor element includes an ALU and registers. The master control unit controls all
the operations of the processor elements. It also decodes the instructions and
determines how the instruction is to be executed.
The main memory is used for storing the program. The control unit is responsible for
fetching the instructions. Vector instructions are send to all PE's simultaneously and
results are returned to the memory.
The best known SIMD array processor is the ILLIAC IV computer developed by
the Burroughs corps. SIMD processors are highly specialized computers. They are

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only suitable for numerical problems that can be expressed in vector or matrix form and
they are not suitable for other types of computations.

PE1 m1
Master Control
Unit

PE2 m2

MAIN
MEMORY
PEn mn

A)c)Memory Hierarchy in Computer Architecture:

The memory hierarchy design in a computer system mainly includes different storage devices.
Most of the computers were inbuilt with extra storage to run more powerfully beyond the main
memory capacity. The following memory hierarchy diagram is a hierarchical pyramid for
computer memory. The designing of the memory hierarchy is divided into two types such as
primary (Internal) memory and secondary (External) memory.

Registers:
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Usually, the register is a static RAM or SRAM in the processor of the computer which is used for
holding the data word which is typically 64 or 128 bits. The program counter register is the most
important as well as found in all the processors. Most of the processors use a status word
register as well as an accumulator.

Register
Memory

Cache
Memory

Main Memory

Magnetic Disks

Magnetic Tape

Cache Memory
Cache memory can also be found in the processor, however rarely it may be another IC
(integrated circuit) which is separated into levels. The cache holds the chunk of data which are
frequently used from main memory. When the processor has a single core then it will have two
(or) more cache levels rarely. Present multi-core processors will be having three, 2-levels for
each one core, and one level is shared.

Main Memory

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The main memory in the computer is nothing but, the memory unit in the CPU that
communicates directly. It is the main storage unit of the computer. This memory is fast as well
as large memory used for storing the data throughout the operations of the computer. This
memory is made up of RAM as well as ROM

Magnetic Disks
The magnetic disks in the computer are circular plates fabricated of plastic otherwise metal by
magnetized material. Frequently, two faces of the disk are utilized as well as many disks may be
stacked on one spindle by read or write heads obtainable on every plane. All the disks in
computer turn jointly at high speed. The tracks in the computer are nothing but bits which are
stored within the magnetized plane in spots next to concentric circles. These are usually
separated into sections which are named as sectors.

Magnetic Tape
This tape is a normal magnetic recording which is designed with a slender magnetizable
covering on an extended, plastic film of the thin strip. This is mainly used to back up huge data.
Whenever the computer requires to access a strip, first it will mount to access the data. Once
the data is allowed, then it will be unmounted. The access time of memory will be slower within
magnetic strip as well as it will take a few minutes for accessing a strip.

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