Finalproject

Section 18
CPRE 281
Final Project
Circuit for checking if a list of numbers is sorted
Introduction
The goal of this project was to registers and register files to first allow you to enter a list of eight
numbers. Once they have been entered, you could change the mode from initialization to
checking m
ode. In checking mode, the board will go through the values in the registers 0-7
while checking that they are progressing in ascending order (in other words: it is increasing).
Register and 4-bit register

The integral part of this project is the register. Figure 1 shows how it was designed.
Figure 1: One Bit Register

That register was then made into a symbol file. When I arranged the registers in the fashion
shown in Figure 2, and by using the BUS tool, I got a four-bit register. The four-bit register is
useful because you can enter values from 0 to F (Hexadecimal) which can then be entered into
a SevenSegDecoder.
Figure 2: 4bit Register
Comparator and 4-bit Comparator

To determine which numbers were more than the others I needed to make a 4-bit comparator.
I first designed a 2-bit Comparator in verilog. After that I went ahead and made a symbol out of
it and designed a 4-bit comparator (Figure 4).
Figure 3: 2-bit Comparator

Figure 4: 4-bit Comparator
8 to 1 4-bit Multiplexer
The 8 to 1 4bit Multiplexer is needed to have two distinct reading ports. The inputs of the
Multiplexer is the output of the registers. Depending on the select lines, the read port will output
the value from certain register. Figure 5 shows how I designed 8 to 1 4-bit Multiplexer.
Figure 5: 8 to 1 4bit Multiplexer

3 to 8 / 2 to 4 decoder
To allow the user to determine the write address, a 3 to 8 decoder was necessary as it is
one-hot encoded. I first made a 2 to 4 decoder which when arranged like Figure 6 gives and 3 to
8 decoder. *although it says ‘encoder’ in the image, it is a decoder.
Figure 6: 3 to 8 Decoder
Select Line Generator for RP and RQ

Our two read ports are called ‘RP’ and ‘RQ’. I needed ‘RP’ to read the outputs of register0 to
register6. So I just developed a counter that would count from 0-6 which would feed into ‘RP’s
select lines and make sure that our output is from register 0-6. Figure 7 shows the Next State
Logic (NSL) for that goal.
Figure 7: Next State Logic for RP

After making a symbol for the NSL, I plugged it into Figure 8. As we can see the Select
Generator will continuously output values from 0-6 with ‘RP0’ being the third bit ,‘RP1’ being the
second bit and ‘RP2’ being the first bit.
Figure 8: Select Generator for RP (SRP)
For the select lines for ‘RQ’, I need it to go from 1-7. For that made a symbol of Figure 8 and
then used a 4-bit adder.
Figure 9: 4-bit adder Figure 10: Full Adder

By using a 4-bit adder, I could simply a (0001) to SRP’s output, which will make it go from 1 to 7.
Figure 11 shows how I converted SRP into SRQ.
Figure 11: Select Generator for RQ (SRQ)
Clock Generator
The clock generator for both NSL’s shown above was kept in the project to make sure that it
was consistent for both NSL’s.
Figure 12

Small yet Essential Contributors
With this section I would like to go through some of the smaller components that made a lot of
difference in the overall working of the circuit.
Seven Seg Block
Figure 13 shows the block diagram I made just for the Seven Segment
Displays. By making this into a symbol it made it much easier to keep
track of what is going on.
Figure 13: Seven Seg Block
Mode Change
Write at the start of the project (Figure 14) there is an ‘enable’ for the decoder that allows the
user to input the data at a particular address. I simply put a ‘not’ gate in front of it so that at the
start, it will be in initialization mode. When the switch assigned for the enable is turned it will
therefore deactivate the initialization mode. Connected to the enable are the necessary
components for checking mode.
Location of Anomaly
One of the tasks for the assignment is that if the inputted numbers are not in increasing order,
we should output where the NSL found the number that isn't increasing. Right at the bottom of
Figure 14, I used three ‘and’ gates and connected the output of SRQ with out of the comparator
if the values aren’t increasing. Therefore, if the values aren’t increasing the location will be
displayed on LED’s.
Figure 14: Full Project file
Conclusion
In Conclusion, this was a very difficult project that took a lot of time and effort. But overall the
circuit that I made works perfectly, and it is made in a way that is pretty easy to explain to
someone else.

Appendix 1
Appendix 2

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Section 18

Register and 4-bit register

Figure 1: One Bit Register

Figure 2: 4bit Register

Comparator and 4-bit Comparator

Figure 3: 2-bit Comparator

Figure 5: 8 to 1 4bit Multiplexer

Select Line Generator for RP and RQ

Figure 7: Next State Logic for RP

Figure 8: Select Generator for RP (SRP)

Figure 9: 4-bit adder Figure 10: Full Adder

Figure 11: Select Generator for RQ (SRQ)

Seven Seg Block

Figure 13: Seven Seg Block

Figure 14: Full Project file

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