Interconnect Limits on Gigascale Integration

(GSI) in the 21st Century

JEFFREY A. DAVIS, RAGURAMAN VENKATESAN, ALAIN KALOYEROS,
MICHAEL BEYLANSKY, SHUKRI J. SOURI, KAUSTAV BANERJEE, MEMBER, IEEE,
KRISHNA C. SARASWAT, FELLOW, IEEE, ARIFUR RAHMAN, MEMBER, IEEE,
RAFAEL REIF, FELLOW, IEEE, AND JAMES D. MEINDL, FELLOW, IEEE

Invited Paper

Twenty-first century opportunities for GSI will be governed in Keywords—Crosstalk, epitaxial growth, interconnections, mod-
part by a hierarchy of physical limits on interconnects whose levels eling, scattering, technology forecasting, thin films, thin-film tran-
are codified as fundamental, material, device, circuit, and system. sistors, transmission lines, wafer bonding, wiring.
Fundamental limits are derived from the basic axioms of electro-
magnetic, communication, and thermodynamic theories, which im-
mutably restrict interconnect performance, energy dissipation, and I. INTRODUCTION
noise reduction. At the material level, the conductor resistivity in-
creases substantially in sub-50-nm technology due to scattering The International Technology Roadmap for Semiconduc-
mechanisms that are controlled by quantum mechanical phenomena tors (ITRS) projects that by 2011 over one billion transis-
and structural/morphological effects. At the device and circuit level, tors will be integrated into a single monolithic die [1]. The
interconnect scaling significantly increases interconnect crosstalk
and latency. Reverse scaling of global interconnects causes induc- wiring system of this billion-transistor die will deliver power
tance to influence on-chip interconnect transients such that even to each transistor, provide a low-skew synchronizing clock to
with ideal return paths, mutual inductance increases crosstalk by latches and dynamic circuits, and distribute data and control
up to 60% over that predicted by conventional RC models. At the signals throughout the chip. The resulting design and mod-
system level, the number of metal levels explodes for highly con- eling complexity of this GSI multilevel interconnect network
nected 2-D logic megacells that double in size every two years
such that by 2014 the number is significantly larger than ITRS is enormous such that over 10 coupling inductances and
projections. This result emphasizes that changes in design, tech- capacitances throughout a nine-to-ten-level metal stack must
nology, and architecture are needed to cope with the onslaught of be managed. A seminal paper [2] focuses on the transistor
wiring demands. One potential solution is 3-D integration of tran- limits for a GSI system; therefore, this paper will address the
sistors, which is expected to significantly improve interconnect per- limits that on-chip interconnects place on a GSI system de-
formance. Increasing the number of active layers, including the use
of separate layers for repeaters, and optimizing the wiring network, sign in the 21st century.
yields an improvement in interconnect performance of up to 145% Interconnect limits potentially threaten to decelerate
at the 50-nm node. or halt the historical progression of the semiconductor
industry because the miniaturization of interconnects,
Manuscript received February 15, 2000; revised October 1, 2000. unlike transistors, does not enhance their performance.
J. A. Davis, R. Venkatesan, and J. D. Meindl are with the Department Scaling transistors to the nanometer regime is plagued
of Electrical and Computer Engineering, Georgia Institute of Technology, with many challenges, such as drain-induced-barrier
Atlanta, GA 30332 USA.
A. Kaloyeros and M. Beylansky are with the Center for Advanced Thin lowering (DIBL), quantum mechanical gate tunneling,
Film Technology and Department of Physics, The State University of New mobility degradation, and reliability problems due to
York (SUNY) at Albany, Albany, NY USA. random placement of dopant atoms in a host silicon
S. J. Souri, K. Banerjee, and K. C. Saraswat are with the Department
of Electrical Engineering, Stanford University, Stanford, CA 94305-9505 lattice [1], but once overcome MOSFET channel scaling
USA. will enhance intrinsic gate delay [1]. For instance, scaling
A. Rahman and R. Reif are with the Department of Electrical Engineering MOSFET channel length from 1000 to 100 nm to 35
and Computer Science, Massachusetts Institute of Technology, Cambridge,
MA 02139 USA. nm dramatically reduces the intrinsic MOSFET switching
Publisher Item Identifier S 0018-9219(01)02068-0. time as seen in Table 1. Scaling interconnects into the

0018–9219/01$10.00 © 2001 IEEE

PROCEEDINGS OF THE IEEE, VOL. 89, NO. 3, MARCH 2001 305

Table 1
Interconnect and Transistor Scaling Properties

nanometer regime is also plagued with many challenges, II. FUNDAMENTAL LIMITS
such as resistivity degradation, material integration issues, This discourse on interconnect limits begins through ex-
high-aspect ratio via and wire coverage, planarity control, amination of several of the most basic principles that govern
and reliability problems due to electrical, thermal, and the physical world. The limits discussed in this section are
mechanical stresses in a multilevel wire stack [1], and immutable and are unchanged through the use of advanced
once these challenges are overcome, minimum inter- materials, sophisticated device structures, inventive circuit
connect scaling will still degrade interconnect delay. techniques, or novel instruction set architectures. These
For example, Table 1 also illustrates that the intrinsic limits, therefore, are defined as fundamental and will irre-
interconnect delay of a 1-mm length interconnect at the vocably limit interconnect performance, energy dissipation,
35-nm technology node overwhelms the transistor delay and signal integrity in the 21st century.
by two orders of magnitude.
A potential solution to this interconnect dilemma is to re-
A. Performance Limits
verse scale longer semiglobal and global interconnects such
that they have “fat” cross-sectional dimensions [3], [4]. This The role of GSI global interconnects is to transmit binary
strategy enhances interconnect performance, but at the ex- switching events that are generated from constituent compu-
pense of wire density. For example, to balance the intercon- tational elements. The fundamental limit, therefore, on inter-
nect delay of a 1-mm interconnect length with the transistor connect performance is set by the shortest delay between a
switching delay, the wire size at the 35-nm generation must binary switching event in a transmitter and a binary transi-
be almost five times larger than the minimum lithographic tion detected at a receiver. To determine the shortest possible
size as seen in Table 1. Because die area is directly related to delay, the communication channel connecting the transmitter
cost, the area penalties of the reverse scaled strategies could to the receiver is assumed to be a perfect noise-free lossless
hinder the exponential reduction in cost per function that interconnect.
has propelled semiconductor technology over the past sev- The maximum transmission speed is limited by the speed
eral decades. of an electromagnetic wave propagating in free space and
The central thesis of this paper is that in the 21st century is a well-known quantity derived from Maxwell’s equations
opportunities for GSI will be governed in part by a hierarchy [7]. Assuming that free space surrounds a lossless intercon-
of physical limits on interconnects whose levels are codified nect, then the Helmholz equations, which are derived from
as fundamental, material, device, circuit, and system [2], [6]. Maxwell’s equations, describe the propagation of electric
In Section II, fundamental limits are derived from the basic and magnetic fields. A key result obtained from the Helmholz
axioms of electromagnetic, communication, and thermody- equation is that the free-space wave propagation speed is
namic theories. In Section III, material limits are determined given by
by the transformation of bulk properties of metallic inter-
connects as they are scaled into the nanometer regime. In (1)
Section IV, device limits deal directly with the problems of
interconnect miniaturization and provide a rationale for re-
where and are, respectively, the permeability and the
verse-scaling strategies. New metrics for crosstalk with and
permittivity of free space. The latency in communicating
without on-chip inductive effects are presented. At the cir-
a binary transition event from the transmitter to the receiver
cuit level in Section V, the impact of transistor driver output
must be greater than
resistance on interconnect performance and crosstalk is in-
vestigated. Finally, in Section VI, system limits imposed by
reverse-scaled multilevel interconnect networks are investi- (2)
gated using a compact wire-length distribution model to pre-
dict the wiring requirements of future GSI products. Wire where is the transmission distance.
area limits of reverse-scaled multilevel networks in a two-di- This fundamental limit is clearly represented in the recip-
mensional (2-D) planar transistor process are projected, and rocal length squared versus time delay plane as seen in Fig. 1
the opportunity for three-dimensional (3-D) integration of after [2]. The region to the left of the line with a slope of neg-
transistors is rigorously explored to help alleviate intercon- ative two in logarithmic scaling in this plane is a forbidden
nect delay and density problems. region of interconnect operation.

306 PROCEEDINGS OF THE IEEE, VOL. 89, NO. 3, MARCH 2001

 nect bus is set by the quantization of charge. The minimum
switching potential of a single electron interconnect is set at

[V] (5)

C. Noise Limits
In digital circuits an important metric of a binary transition
is its potential swing, and in the presence of thermal noise this
potential is perturbed from its nominal value. The best metric
for this perturbation is the standard deviation of thermal noise
voltage across a resistor, which is derived by Nyquist [2] to
be

(6)

Fig. 1. Fundamental performance limit set by the electromagnetic where

propagation in free space. Boltzmann’s constant ( J/K);
temperature ( K);
bandwidth of the receiver;
B. Energy Limits
resistance of the interconnect load.
The second fundamental limit is based upon Shannon’s The most statistically significant deviation of the potential at
communication theorem for the maximum capacity of a com- the end of the line is defined by (6). The interconnect noise
munication channel. The expression for the maximum ca- floor, therefore, is set by the thermal noise fluctuation across
pacity of a communication channel with a white Gaussian a load with a resistance equal to the characteristic impedance
thermal noise source is given by [8] of free space. Assuming that is the reciprocal receiver
bandwidth, this fundamental limit is
(3)
(7)

where
maximum channel capacity measured in bits/s;
III. MATERIAL LIMITS
average signal power of the input;
Johnson thermal noise power delivered to a matched Device feature sizes are crossing a critical physical
load [8]; threshold below which the performance of extremely narrow
bandwidth of the receiver; interconnect lines is controlled primarily by: 1) the proper-
Boltzmann’s constant ( J/K); ties of their surfaces and interfaces, as driven by one- and
temperature ( 300 K) [8]. two-dimensional scattering effects; and 2) the characteristics
Assuming that the average energy per bit is , of their impurity and defect densities, as governed by the
then solving for in (3) gives type and distribution of grain boundaries, dislocations, and
junctions. This transition represents a major show stopper
in the successful development of the material and process
(4) (M&P) technologies necessary to ensure maximum signal
transmission in sub-50-nm device nodes through reduced
Setting the derivative of (6) equal to zero or resistance capacitance ( ) time delay. In particular, the
and employing L’Hospital’s rule gives physics of resistivity behavior in extremely fine conductor
lines represents a daunting and potentially insurmountable
challenge that needs to be understood and resolved in order
(7)
to ensure the extendibility of today’s chip architecture below
the 50-nm device node.
Note that is tantamount to calculating the energy In this respect, the resistivity of thin-film conductors is
transfer of an infinitely long bit or a single binary transition. given by [9], [10]
If the energy transferred during a binary transmission on an
interconnect is less than , then the binary transition (thin film) (thermal) (extrinsic) (8)
cannot be differentiated from thermal noise regardless of ad-
vanced error-correcting encoding techniques. where (thermal) is the contribution due to electron–phonon
This energy also sets a lower limit on low-swing intercon- “coupling” (i.e., electronic interactions with thermally in-
nect buses. In the limit, the smallest swing of an intercon- duced lattice vibrations), and (extrinsic) is the contribution

DAVIS et al.: INTERCONNECT LIMITS ON GSI IN THE 21st CENTURY 307

 More specifically, Fig. 4(a) displays the island-like sur-
face morphology of a thinner, 35-nm-thick TCVD Cu film on
TaN . In contrast, Fig. 4(b) shows an appreciably smoother
surface morphology for a thicker, 60-nm-thick, TCVD Cu
on the same liner material. The islands become increasingly
discontinuous with further reduction in film thickness. Their
boundaries act as progressively higher potential barriers, thus
leading to a gradual rise in resistivity. Finally, below a crit-
ical thickness, a matrix of completely disconnected nuclei is
formed, with the associated resistivity becoming infinite. The
value of this critical thickness is strongly dependent on the
mechanisms of Cu film nucleation and growth, as driven by
the nature and characteristics of thin-film formation in CVD,
sputtering, and ECD processing, and the surface chemistry,
Fig. 2. Resistivity r (thin film) as function of thickness for
blanket (unpatterned) polycrystalline Cu films by: (a) TCVD morphology, and texture of the underlying liner material.
from the source precursor Cu (hfac)(tmvs), (b) collimated Over the years, various theoretical treatments were only
sputtering, and (c) electrochemical deposition (ECD). Due to
the significantly reduced Cu thickness investigated, experimental
partially successful at modeling the dependence of resistivity
resistivity values were corrected for liner contributions by on surface roughness for ultrathin metallic films [14]. In par-
using the suitable approximation (from [4]): Cu(thin film) = ticular, Elsom et al. [15] developed a numerical model for the
4:53t[R R =(R 0 R )] Where t; R , and R
rise in resistivity as function of decreased thickness for Cu
represent, respectively, the thickness of the Cu layer, the effective
resistance of the Cu/liner stack, and the resistance of the liner. films with island-like morphology. Unfortunately, the model
was limited to cases where the island size was larger than the
bulk mean free path for electron scattering in Cu, a limita-
from electron scattering by impurities, defects, grain bound-
tion that severely restricts the applicability of the model to
aries, and film surface and interface, as given by
sub-50-nm interconnect lines, as discussed below.
Elimination of surface roughness induced scattering
(extrinsic) (defect) (impurity) (grain boundary) effects requires the development of M&P solutions that
(surface/interface) (9) combine the ability to “nanoengineer” film morphology
and texture, with the implementation of predictive models
For illustration purposes, Fig. 2 plots the resistivity using comprehensive theoretical treatments, to grow epi-
(thin film) as function of thickness for blanket (unpatterned) taxial Cu/liner interconnect stacks with atomically smooth
polycrystalline copper thin films deposited on 9-nm-thick surfaces and interfaces. These solutions include the iden-
tantalum nitride (TaN ) by [11]: 1) thermal chemical tification of epitaxial “zero thickness” liner materials that
vapor deposition (TCVD) from the source precursor are closely lattice-matched to Cu, and the development
Cu (hfac)(tmvs), where hfac hexafluoroacetylacetonate of atomically tailored, interfacially controlled processing
and tmvs trimethylvinylsilane; 2) collimated sputtering; methodology, such as atomic layer CVD technologies. They
and 3) electrochemical deposition (ECD). As expected, also involve the use of atomically engineered zero-thickness
the total resistivity (thin film) in all three cases was interfacial layers, such as surfactants, which act as a “wet-
observed to increase with decreasing film thickness, with ting” layer that ensures the availability of a high density of
the rate of increase exhibiting significant dependence on surface nucleation sites and reduces the nucleation barrier
the deposition technique due to morphological and textural to Cu formation. The desired outcome is to eliminate
differences between the corresponding three types of Cu island-type morphology through the achievement of a Frank
films. van der Merve, layer by layer, Cu growth [16].
The increased resistivity with thickness reduction is at- For illustration purposes, Fig. 5 plots the resistivity as
tributed in part to surface roughness induced scattering ef- function of thickness for blanket polycrystalline Cu thin
fects [12], which are caused predominantly by the island-like films on TaN and indium-seeded TaN . The two sets of
morphology of polycrystalline Cu films, i.e., films where sur- Cu films were grown using identical processing conditions.
face roughness is on the order of or larger than film thick- The use of indium (In) as surfactant led to a significant
ness [13]. These effects tend to play an increasingly more reduction in total resistivity as compared to the case where
pronounced role as the polycrystalline film becomes thinner. no In was employed. This behavior is attributed to the role
This trend is documented in Fig. 3, which displays the rel- of the surfactant layer in reducing the activation barrier
ative surface roughness (surface grain size), plotted as per- to Cu nucleation and growth, leading to films with appre-
cent of film thickness, for TCVD-grown polycrystalline Cu ciably smoother surface morphology, as documented in
films deposited on tantalum nitride and tungsten nitride [11]. the FIB-SEM micrographs of Fig. 6. The selection of a
In this study, surface grain size and associated root-mean- surfactant must, however, satisfy a stringent set of require-
square surface roughness were determined by atomic force ments, including that its thickness must be restricted to a
microscopy (AFM) and focused-ion-beam scanning electron few monolayers in order to maximize space availability
microscopy (FIB-SEM). for the actual copper conductor. In addition, it must be

308 PROCEEDINGS OF THE IEEE, VOL. 89, NO. 3, MARCH 2001

Fig. 3. Relative surface roughness (surface grain size), plotted as percent of film thickness, for
TCVD-grown polycrystalline Cu films deposited on tantalum nitride and tungsten nitride.

concentrations within the Cu matrix and must not induce

any unacceptable increase in the overall effective resistance
of the resulting Cu alloy [17].
Apart from surface roughness induced scattering, the in-
creased resistivity with thickness reduction is also caused
by surface and interface induced scattering phenomena. The
latter become predominant in films where the thickness is
on the order of or smaller than the bulk mean free path
for electron scattering in the corresponding metal [18]. As
can be seen in Table 2 [8], which displays the bulk mean
free path for selected metals of interest, surface scattering
effects are expected to become predominant in sub-50-nm
Cu lines. Interestingly, the resulting rise in the overall resis-
tivity of progressively narrower conducting lines could po-
tentially produce equivalent conductivity characteristics in
aluminum, tungsten, and copper-based interconnects. This
possibility could have significant implications in terms of the
selection of most appropriate material systems for gigascale
metallization schemes.
A number of theoretical treatments have already been de-
veloped for the effects of grain boundary and surface scat-
tering on thin-film resistivity [14], [15], [18]. Sambles com-
bined key elements of these treatments, which are almost uni-
versally based on the semiclassical scattering model, into a
comprehensive expression for the general case of a film with
different roughness profiles at its surface and interface. In
this expression, the ratio of bulk resistivity to thin-film resis-
tivity is given by
Fig. 4. FIB-SEM micrographs of the surface morphology of: (a)
35-nm-thick TCVD Cu films on TaN and (b) 60-nm-thick TCVD
Cu on the same liner material.
(bulk) (thin film) (10)

The first term accounts for grain boundary scattering with

mechanically, thermally, and structurally stable under typ-
ical semiconductor fabrication flows, and preferably retain (11)
its as-deposited chemical and compositional integrity. In
the case a Cu alloy is formed, however, the inclusion of where is the grain boundary reflection coefficient and
the surfactant material must be limited to extremely small is the average grain size. The second term is known as

DAVIS et al.: INTERCONNECT LIMITS ON GSI IN THE 21st CENTURY 309

 Table 2
Electron Mean Free Paths for Selected Metals of Interest
(From [18])

Fig. 5. Resistivity as function of thickness for blanket

polycrystalline Cu thin films on: (a) TaN and (b) In-seeded
TaN .

Fig. 7. Comparison of experimental Cu resistivity profiles versus

thickness for TCVD Cu on TaN with predictions of the Sambles
semiclassical scattering model and percolation theory.

tion in surface scattering effects requires the development of

M&P solutions that maximize specular electron scattering.
The model was found to be in excellent agreement with
experimental resistivity measurements for film thickness
above 50 nm, as shown in Fig. 7. This agreement was
achieved by using a grain boundary reflection coefficient
of 0.27. This value is low and implies that the TCVD
Cu films are pure and dense, with the contribution to film
resistivity from grain boundary induced scattering effects
being minimal. The model was in serious disagreement
with the experiment for film thickness below 50 nm. This
discrepancy is expected and is attributed to the fact that
a basic assumption in the derivation of the semiclassical
model is that surface roughness is smaller than film thick-
ness. Clearly, this assumption is not applicable to ultrathin
Cu films, which are characterized by a more “island-like”
Fig. 6. FIB-SEM micrographs of the surface morphology of morphology. As a result, percolation theory was successfully
TCVD Cu films on: (a) TaN and (b) In-seeded TaN .
applied to model resistivity behavior in sub-50-nm Cu lines.
Percolation theory is a statistical theory that describes the
the Fuchs modified term and accounts for surface scattering properties of any given randomly assembled system near the
effects. In this term, is the probability for specular electron point where it changes from a macroscopically disconnected
scattering from the film surface and interface, while and to a connected one [19]. This point is called a percolation
are the roughness profiles of, respectively, the surface and threshold and the overall system properties are expected
interface. The coefficient is the ratio of film thickness to to change drastically near this threshold. This approach
the mean free path . The model thus predicts that the reduc- is highly applicable to the case of ultrathin conductors,

310 PROCEEDINGS OF THE IEEE, VOL. 89, NO. 3, MARCH 2001

especially in view of the random character of island forma-
tion and grain agglomeration that is typically observed in
thin-film growth. Percolation theory describes the resistivity
of such an ultrathin conductor system as a random resistor
network. The obvious choice for a percolation threshold
in this case is the critical thickness ( ), above which the
film becomes continuous. Film resistivity drops sharply
near the critical thickness where Cu islands merge together
and form a backbone for electron transport. Several system
properties are found to obey the so-called scaling laws near
the percolation threshold. In particular, the scaling law for
system resistivity states that resistivity is proportional to the
difference between the fraction of a substrate area covered
by the film and the critical substrate area coverage at the
percolation threshold [20].
It has been shown that in case of random nucleation area
coverage is proportional to film thickness, so the final ex-
pression for film resistivity is given by
Fig. 8. Scaling effects on interconnect time delay limits.
(thin film) (bulk) (12)
where
where is a critical exponent, which is equal to 1.3 for 2-D distributed resistance per unit length;
systems. As shown in Fig. 7, this value of the critical ex- distributed ground capacitance per unit length;
ponent yielded excellent fit with the experimental data. The interconnect length;
fit yielded a value of 29.7 nm for the critical thickness , speed of electromagnetic wave propagation.
which is highly consistent with experimental observations, Using a simple parallel plate model for the parasitic capac-
thus providing additional proof to the accuracy of the perco- itance per unit length of the interconnect, the interconnect
lation theory fit. delay in (13) becomes
Subsequent theoretical modeling efforts will center on an-
alytical and numerical calculations of surface scattering in (14)
finite-size topographies with emphasis on one-dimensional
(1-D) to 2-D crossover effects. Resulting findings will be where
coupled to experimental resistivity measurements in ultra- resistivity of the conductor;
narrow conducting lines to establish baseline metrics for the permittivity of the insulator;
dependence of 2-D grain boundary and surface scattering be- thickness of the metal conductor;
havior on device feature size. The net projected outcome is dielectric thickness.
the development and optimization of M&P solutions that can The interconnect latency metric in (14) clearly reveals the
grow epitaxial Cu/liner interconnect stacks with atomically scaling properties of global interconnects. Ideal scaling of
smooth surfaces and interfaces, while maximizing specular all wire dimensions, including length, results in no reduc-
electron surface scattering in ultranarrow interconnect lines. tion in delay. Furthermore, because transistor numbers and
die sizes are increasing with each new technology genera-
IV. DEVICE LIMITS tion, global interconnect lengths are increasing, which re-
Interconnect device limits in this section will probe the in- sults in significant interconnect performance degradation [3].
herent attributes of wires free from the effects of transistors. Scaling effects on interconnect latency have been rigorously
To investigate interconnect device limits in the 21st century, investigated [2], [3] and are illustrated most effectively in
basic interconnect structures are presented in this section to the reciprocal length squared versus time delay plane seen
elucidate performance and noise limits on interconnects. in Fig. 8 after [2]. The diagonal in this plane is a locus of
constant distributed product, and interconnect operation
A. Performance Limits is forbidden to the left of each locus for interconnects with
1) Resistance and Capacitance (RC) Effects: Unlike a smaller cross-sectional dimension . This plot re-
the transistor, interconnect performance is not enhanced veals that reverse scaling of interconnects of global intercon-
through miniaturization. This result is presented most nect dimensions reduces interconnect latency [3],
succinctly using a distributed network to model a single [4].
global on-chip interconnect. The latency of this intercon- 2) Inductance Effects: Reverse-scaling methodologies
nect is given by the distributed time delay (assuming reduce delay, but at gigahertz clock frequencies re-
) as verse-scaling necessitates the inclusion of self-inductance in
global signal interconnects, clock lines, and power distribu-
(13) tion networks. Inductance introduces unique challenges for

DAVIS et al.: INTERCONNECT LIMITS ON GSI IN THE 21st CENTURY 311

each type of interconnect. For example, variations in return
path currents for each leg of a balanced clock tree (BCT)
network produces variation in interconnect delay and reflec-
tion characteristics [21]. Inductance in power distribution
networks produces voltage transients that are dependent
on the number of simultaneously switched devices. As
representative of on-chip inductance issues, this analysis
will concentrate on the influence of inductance on global
signal interconnects. For global clock and signal intercon-
nects, gigahertz chip designers must provide controlled
current return paths to reduce on-chip inductive effects. To
investigate aggressive interconnect limits, therefore, perfect
return path currents are assumed in this paper using ideal
ground planes.
Assuming negligible skin effect, the telegrapher’s equa-
tion describes the transient voltage along a single intercon-
nect. On-chip interconnect modeling is complicated by the Fig. 9. Comparison of distributed rc and distributed rlc model for
fact that high-density global wires must include both induc- a global interconnect with Z = 266:5 W, r = 37:87 W/cm, L =
tance and resistance such that neither quantity is a perturba- 3:6 cm, R = 0.
tion to a well-known or solution. The complete so-
lution to the telegrapher’s equation, therefore, is succinctly interconnect device with the inclusion of inductance can be
and efficiently given by a series of modified Bessel functions approximated by
in

(17)

where is a step function. Inductance effects for this

(15) interconnect become significant when
(18)
where
The effect of inductance on a high-speed global intercon-
nect is illustrated by comparing the transient response of an
on-chip copper interconnect ( m)
using distributed models with the compact distributed
model in (15). As seen in Fig. 9, the distributed model
does not capture transient reflections and underestimates the
time delay of this aggressive on-chip interconnect design.
Moreover, significant overshoot at the end of this intercon-
nect is not predicted with distributed models. Overshoot
in this aggressively scaled interconnect in Fig. 9 is almost
70% higher than the supply voltage.

B. Crosstalk Limits
(16) 1) Resistance and Capacitance ( ) Effects: Even
in high-speed GSI multilevel interconnect networks, dis-
where is a th-order modified Bessel function, is the tributed models are still needed to determine the
interconnect length, is time, , , and are the distributed transient behavior of local and semiglobal interconnects
inductance, resistance, and capacitance per unit length, re- and, therefore, are used to investigate the limits on crosstalk
spectively, is the reflection coefficient at the source, is for shorter high-speed interconnects. Local interconnects,
the current reflection number given by which make up the majority of on-chip interconnects [25],
, the notation is defined as the decimal trunca- will continue to scale to minimum feature size dimensions
tion of (i.e., ), and and are determined to maximize wire density. An existing distributed
to obtain the desired accuracy of solution (in the limit they interconnect model with a step-response excitation voltage
both go to infinity) [23]. predicts that the peak crosstalk (at the load of the quiescent
Using a near wave-front approximation to (15) and a dis- line), , between the two parallel wires is length, scaling,
tributed model in [24], the 50% time delay of a single and material independent for homogeneous dielectrics [24].

312 PROCEEDINGS OF THE IEEE, VOL. 89, NO. 3, MARCH 2001

 The finite switching time of a interconnect driver, how-
ever, must be considered to fully understand crosstalk limits
for local and semiglobal interconnects. Using a ramp-re-
sponse ideal voltage source driving an active line parallel
to a quiescent line, the complete solution to this peak noise
voltage at the load end of the quiescent line is given by [26]

(19)

Fig. 10. Effects of interconnect scaling on crosstalk for a

semiglobal interconnect.

where is the mutual capacitance between wires and

is the ground capacitance of each wire. Assuming that the
driver switching time, , is slower than the intercon-
nect step response, in (13), then the peak crosstalk voltage
increases with the square of interconnect length and is given
by

(20)

Using simple parallel plate models for the mutual capaci-

tance transforms (20) into
(21)
The salient observation derived from (21) is the scaling
dependence of peak crosstalk voltage. Fig. 10 illustrates
that minimum scaling of wire dimensions of a 1-mm length
interconnect from 1 m to 50 nm drastically increases peak Fig. 11. Maximum interconnect coupling length of local and
crosstalk at the load end of the quiescent line. For example, semiglobal interconnect at which crosstalk begins to exceed 10%
of switching potential.
for a 1-ns risetime the peak noise voltage to switching
potential ratio increases almost three orders of magnitude
Crosstalk is reduced in the second region when the intrinsic
from approximately 0.0002 to 0.1 when scaling this inter-
driver switching time dominates the step-response intercon-
connect from 1 m to 50 nm. The diagonals in this plot of
nect delay ( ) and is described by (20). As the
peak crosstalk voltage to binary switching potential ratio
MOSFET switching time decreases and intrinsic intercon-
versus source voltage rise time in Fig. 10 are loci of con-
nect delay increases [1] as illustrated in Table 1, crosstalk
stant resistance and mutual capacitance product. The peak
problems will infest the multilevel wiring network and dra-
noise voltage with device level models increases with the
matically increase the number of local and semiglobal inter-
inverse square of the device dimension . Physically
connects with high crosstalk. Fig. 11 illustrates the intercon-
this occurs because minimum wire scaling increases wire
nect length at which the peak noise voltage is 10% of the
resistance, which hinders discharge of crosstalk currents on
supply voltage for each ITRS generation over the next 15
the quiescent line.
years with wire dimensions equal to F, 2F, and 4F. The max-
As seen in Fig. 10, there are two distinct crosstalk regions.
imum coupling length decreases almost an order of magni-
In the first region, crosstalk is at a maximum when the total
tude by 2014, which will drastically increase the number of
interconnect delay is limited by the intrinsic step-response
interconnects with significant crosstalk.
interconnect delay (i.e., ) and is described in [24]
2) Inductance Effects: With the advent of multigigahertz
and given by
clock frequencies, another serious challenge for the GSI de-
signer is on-chip interconnect inductance. Just as with in-
(22)
terconnect performance, this parasitic has its greatest effect

DAVIS et al.: INTERCONNECT LIMITS ON GSI IN THE 21st CENTURY 313

on reverse-scaled high-speed global interconnects. To deter-
mine aggressive crosstalk limits on inductance for the device
level, just as in the previous section, an ideal ground plane
is used to provide a low-impedance path for return currents.
In addition, it is also assumed that the finite switching time
of a MOSFET only slightly affects long global interconnect
crosstalk and, therefore, is ignored.
Assuming negligible skin effect, the telegraphers equation
for two symmetric lines is used to describe the transient re-
sponse along two coupled interconnects and is given by

Fig. 12. Nonlinear length dependence of crosstalk for various

driver resistance of 0.0
, 35.8
, and 71.6
.

(23)
interconnects, (25) reveals that providing ground planes suf-
ficiently close to interconnect structures can be an effective
where strategy for controlling crosstalk. For local, semiglobal, and
voltage along the active line; global interconnects, further reduction in crosstalk can be
voltage along the quiescent line; achieved by increasing wire spacing.
self-inductance of each line;
mutual inductance between each line. V. CIRCUIT LIMITS
Empirical expressions for the capacitance [27] and induc-
tance matrices [28] are used for parasitic estimation. The To gain insight into interconnect circuit limits, simple
transient response along the quiescent line is calculated using models that retain only the essence of the problem under
the compact distributed expression attack are engaged. To this end, a transistor is modeled
as an equivalent resistance in series with an ideal voltage
source that drives an active interconnect in isolation or in
proximity to an identical quiescent wire. In addition, the
limits to reducing circuit delay and crosstalk are determined
(24)
through the use of ideal current return paths for each
where is defined in (15). interconnect structure. Such assumptions clearly elucidate
Effects of mutual inductance pose significant limitations the effects of source resistance on interconnect performance
on peak crosstalk reduction. Using (22) and (24), Fig. 12 and crosstalk. The key conclusion of this section is that
shows the length dependence of crosstalk with and without transistor output resistance exacerbates interconnect circuit
the inclusion of inductance on two coupled lines with delay and crosstalk.
negligible source impedance ( ). Using the dis- A. Circuit Delay Limits
tributed models with a step-response voltage in [24] the
crosstalk is length independent; however, with the inclusion The effects of delay can be approximated using a near
of inductance a strong nonlinear length dependence of wave-front approximation to a Bessel function expansion
crosstalk emerges as seen in Fig. 12. For , the similar to (15) and a distributed model after [24].
distributed crosstalk is roughly 60% higher than that Uniting these two models and assuming that the wire
predicted by models. The expression for this maximum capacitance dominates the transistor input capacitance
crosstalk voltage with the inclusion of inductance, which is ( ), the approximate time for the transient voltage
derived from (24), is given by [23] of an interconnect load to reach is given by

(25)

(26)
The peak crosstalk is approximately times
larger than predicted by a distributed model in [24].
where and is the equivalent transistor output
To help control crosstalk gigahertz interconnect network
impedance. The 90% (i.e., ) interconnect latency
ground planes or dedicated ground wires maybe necessary
limit for a very “fat” global wire ( ) is given by
for the suppression of unpredictable crosstalk caused by in-
ductance. For distributed and high-speed global (27)

314 PROCEEDINGS OF THE IEEE, VOL. 89, NO. 3, MARCH 2001

Fig. 13. Circuit limits for distributed rc models. Fig. 14. RC circuit limits on peak crosstalk.
which is approximately valid only when the
the ability of the quiescent line to quickly discharge crosstalk
. The detrimental effects of driver
currents.
resistance on the interconnect latency are elucidated in the
For high-speed global interconnects where the finite
reciprocal length square versus time delay plane after [2] in
driver rise time is negligible and the cumulative interconnect
Fig. 13. The circuit limit in Fig. 13 approaches the speed of
resistance is on the order of the lossless characteristic
a propagating electromagnetic wave when
impedance of the interconnect, inductive effects must be
(28) included to fully understand the effects of driver resis-
tance on interconnect circuit limits. The central thesis of
where the approximation holds for very small values of the this section is partially violated with high-speed global
wire resistance. In general, the driver resistance that mini- lines because increasing the driver resistance suppresses
mizes both wire delay ( ) and overshoot is given by inductive effects. For example, using a complete solution
to telegrapher’s equation without skin effect, a complete
(29) series solution similar to (24) is used to plot the peak
crosstalk voltage at the end of a quiescent line in Fig. 12
which is valid as long as . Once this con- ( ). The extra driver resistance
dition is violated, time-of-flight operation is unachievable suppresses crosstalk in the nonlinear inductance region,
because the line resistance significantly attenuates fasting but has negligible effects in the resistance limited region
rising “ ” transients, and the ideal driver resistance for min- ( ). The penalty for adding extra source resistance,
imum delay approaches zero. however, is a possible increase in interconnect circuit delay
of the active line.
B. Crosstalk Limits
For interconnect circuits in a GSI multilevel network that VI. SYSTEM LIMITS
have a delay that is dominated by the driver switching time,
System limits are the most nebulous and difficult to project
the extra driver resistance increases the peak noise voltage
because of the difficulty in generic modeling of future GSI
at the end of a quiescent line according to the following ap-
processors. However, a stochastic interconnect distribution
proximation:
model, which has been verified with real microprocessors
(30) [25], is used in this section to explore the limitations that
reverse-scaled multilevel interconnect networks impose on
Using (30) for the condition when and the model in a GSI system.
[24] for , this crosstalk limit using distributed
models is plotted in Fig. 14 for , A. 2-D Integration Limits
and . The region crosstalk remains approx- Using a complete wire length distribution in [25] and
imately unchanged as predicted by [24, (22)]. Increasing the the ITRS [1] provides a unique opportunity to project
source resistance in the region, however, substan- the number of metals levels for highly connected logic
tially increases peak crosstalk at the load end of a quiescent megacells. A highly connected logic block is defined as a
line. In the latter region, larger driver resistance increases statistically homogeneous array of logic gates in which a
peak crosstalk voltage because extra resistance diminishes well-established empirical relationship know as Rent’s Rule

DAVIS et al.: INTERCONNECT LIMITS ON GSI IN THE 21st CENTURY 315

Fig. 15. Projection of the number of metal levels over the next 15 years with the assumption that
historical trends remain.

describes the input–output (I/O) requirements of arbitrarily saturating the maximum number of highly connected gates
sized megacells. The wiring distribution of a 2-D megacell at a value around 10 M keeps the number of metal levels
is based upon Rent’s Rule [29] and is given in [25]. per megacell to a controllable number through 2014. Without
The complete wiring distribution along with interconnect significant changes to traditional microprocessor or ASIC
performance and noise models are used to construct the ar- 2-D transistor technologies, design methodologies, or archi-
chitecture on a GSI multilevel wiring network. In this net- tectures, Fig. 15 suggests that interconnect limits could un-
work it is assumed that interconnects on adjacent metal levels dermine Moore’s law.
in a multilevel network are routed orthogonally. The wire di-
mensions on each orthogonal wiring pair are calculated to B. 3-D Integration Opportunities
insure that the latency of the longest interconnect does not
exceed 90% of the clock period, and each pair of levels is oc- Interconnect delays are increasingly dominating IC per-
cupied with interconnects by equating the required intercon- formance due to increases in chip size and reduction in the
nect area to the available interconnect area. To determine the minimum feature size [30]. In spite of new materials like
absolute limits on system signal integrity, it is assumed that Cu with low- dielectric interconnect delay is expected to
ultrahigh-speed designs have low-impedance ground planes be substantial below 130-nm technology node, thereby se-
that are inserted between each orthogonal pair of wire levels verely limiting chip performance [31]. Therefore, the need
to control the vast number of coupling inductances in an un- exists for alternative technologies to overcome this problem.
shielded GSI multilevel interconnect network. One such promising technique is 3-D ICs with multiple ac-
This stochastic wiring distribution is used to illustrate the tive Si layers. 3-D integration (schematically illustrated in
limitations of historical approaches to microprocessor and Fig. 16) to create multilayer Si ICs is a concept that can
ASIC design. Starting with the assumption that one million significantly alleviate interconnect delay problems, increase
highly connected logic gates are contained in a logic mega- transistor packing density and reduce chip area. Each Si layer
cell for 1999, the number of metal levels is projected over the in the 3-D structure can have multiple layers of interconnect.
next 15 years by doubling the number of highly connected Each of these layers are connected together with vertical in-
logic gates in a megacell every two years. Logic megacell terlayer interconnects (VILICs) and common global inter-
areas for projected designs are calculated by using the pro- connects as shown schematically in Fig. 16. In a 3-D struc-
jected transistor densities, minimum feature size, and clock ture a large number of long horizontal interconnects com-
frequencies outlined in the ITRS [1]. As seen in Fig. 15, monly used in 2-D structures can be replaced by short ver-
the number of required metal levels approaches unrealistic tical interconnects. Additionally, the 3-D architecture offers
values beyond 2005. In fact, the number of projected levels at extra flexibility in system design, placement, and routing.
2014 is almost an order of magnitude larger than the number For instance, logic gates on a critical path can be placed very
of levels prescribed by the ITRS at 2014. As an alternative to close to each other using multiple active layers. This would
Moore’s Law scaling, for example, Fig. 15 also shows that result in reduced chip footprint leading to a significant reduc-

316 PROCEEDINGS OF THE IEEE, VOL. 89, NO. 3, MARCH 2001

 Fig. 17. A three-tier interconnection structure.

modeling the optimal distribution of the metal interconnect

lines.
To better understand how a 3-D design will affect
the amount of metal wires required for interconnections
we applied a stochastic approach for estimating wiring
requirements derived for a 2-D structure [25], [34] and
modified it for 3-D ICs to quantify effects on interconnect
delay. Using a three-tier interconnection structure
(local, semiglobal, and global), illustrated in Fig. 17, the
semiglobal tier pitch that minimizes the wire limited chip
area is determined. The maximum interconnect length
on any given tier is determined by the interconnect delay
criteria. The methodology presented in [25] can be extended
Fig. 16. (a) Schematic representation of 3-D integration based on easily to derive the wire-length distribution of a 3-D IC. The
wafer-bonding approach. Device layer 1, Dl1, is generally a bulk
Si layer; device layer 2, Dl2, can be a thinned Si or SOI layer. (b) wire-length distribution and the interconnect delay criteria
Alternative approach to 3-D integration based on recrystallization or can be used for tradeoff analysis between 2-D and 3-D
epitaxial growth. ICs. The 3-D interconnect scheme being considered for our
analysis is shown in Fig. 16(a).
tion in delay and can greatly enhance the performance a) Wire-length distribution: In deriving the 3-D
of logic circuits [32], [33]. This technology can also be ex- wire-length distribution, instead of a hierarchical partitioning
ploited to build systems on a chip, by placing circuits with approach [35], we use a nonhierarchical partitioning [25].
different voltage and performance requirements in different Since it is not apparent how Rent’s parameters should change
layers. One such example is to have logic circuits in the first as 2-D integrated circuits are mapped into three dimensions,
Si layer and then have memory circuits in the second layer to we assume that the same Rent’s parameters are applicable to
realize distributed memory systems in a microprocessor. both 2-D and 3-D implementation of an integrated circuit. A
1) Performance Estimation of 3-D ICs: A 3-D solution more elaborate description of this methodology is described
seems an obvious answer to the interconnect delay problem. elsewhere [33], [36]. To derive the point-to-point wire-length
Since chip size directly affects the interconnect delay, there- distribution of an integrated circuit of random logic networks
fore by creating a second active layer, the total chip footprint with transistors, the integrated circuit is partitioned into
can be reduced, thus shortening critical interconnects and re- logic gates, where ; is a function of the average
ducing their delay. In modern logic circuits the chip size is fan-in (f.i.) and fan-out (f.o.) in the system [4]. The average
not just limited by the cell size, but also limited by how much separation between the adjacent logic gates is called gate pitch,
metal is required to connect the cells. The transistors on the and it is equal to ,where is the diearea.
silicon surface are not actually packed to maximum density Following the methodology presented in [25], the point-to-
but are spaced apart to allow metal lines above to connect one point wire-length distribution of 3-D IC is given by
transistor or one cell to another. The metal required on a chip (31)
for interconnections is determined not only by the number of
gates, but also by other factors such as architecture, average where
fan-out, number of I/O connections, routing complexity, etc. normalization constant;
Therefore, it is not obvious that by using a 3-D structure, the number of gate pairs separated by length ;
chip size will be reduced. In this work we study the possible number of point-to-point interconnects be-
effects of 3-D integration on chip area and performance by tween these gate pairs.

DAVIS et al.: INTERCONNECT LIMITS ON GSI IN THE 21st CENTURY 317

Fig. 18. Wire-length distribution of 2-D and 3-D integrated circuits Fig. 19. Wire-length distribution of 2-D and 3-D integrated circuits
for symmetrical interconnect schemes, f l N
( ). is the number of for asymmetrical interconnect schemes, f l N
( ). is the number
device layers. of device layers.

The value of is estimated such that the total number of We assume all the logic gates drive average length wires,
point-to-point interconnects in a 2-D or 3-D IC is conserved. while one logic gate drives a chip-edge length wire [4]. We
is estimated by taking into account the equidistant assume the chip area is interconnect limited, and it is esti-
gate pairs located within a device layer and between device mated by equating the available chip area with the required
layers [33]. is estimated by applying Rent’s rule chip area [34]. The available chip area is a function of the
where the source and sink gate pairs, connected by a wire, number of device layers, the chip/die size, total number of in-
can be located on the same or different device layers [33]. In terconnect layers, and the wiring efficiency in each intercon-
our analysis, two limiting cases of the 3-D wire-length dis- nect layer. The required chip area is the product of the wiring
tribution are considered. In the symmetric interconnection pitches and the total wire length of local, semiglobal and
scheme, for any source logic gate, the sink logic gate can global wires. The wiring efficiency model presented in [4]
be located on the same or other device layers, and there is a can be extended to estimate the wiring efficiency of 3-D ICs.
comparable number of interconnections between gate pairs To make a fair comparison between different 2-D and 3-D
on the same and different device layers. In the asymmetric technologies, we introduce a cost/complexity function. We
interconnection scheme, we assume the number of intercon- define a cost function, c.f. , where is the number
nections between the logic gates on different device layers of interconnect levels per device layer, and is
is negligible compared to the number of interconnections the number of interdevice layer bonding steps, and is the
within the device layers. number of device layers. For example, in a 2-D IC c.f. 6
The wire-length distributions for homogeneous random implies that there are six interconnect levels. For the same
logic networks in 2-D and 3-D ICs are shown in Figs. 18 cost function in a 3-D IC with two device layers, there are
and 19. In a 3-D IC, as more device layers are added, the five interconnect levels/device layer and one bonding step.
wire-length distribution becomes narrower resulting in fewer The input parameters of our analysis are presented in
and shorter semiglobal and global wires. In both 3-D in- Table 3. These parameters are consistent with the technology
terconnect schemes, the average and total wire lengths are requirement for microprocessors in 0.18- m technology
shorter. However, a symmetric interconnection scheme re- node [37]. The clock frequency is estimated by keeping
sults in shorter average and total wire lengths compared to the total chip area, , fixed and applying the cost
an asymmetric interconnection scheme. constraint. The simulation results are shown in Fig. 20. The
b) Simulation results: Using the wire-length distri- improvement in clock frequency in a 3-D IC results from
bution and the interconnect delay criteria, some interesting the reduction in interconnect delay of the average length
tradeoff analysis can be performed between 2-D and 3-D and chip-edge length wires due to their shorter wire-lengths
ICs. For example: 1) chip area can be estimated for fixed and larger wiring pitch. The total wire length in a 3-D IC
clock frequency; 2) clock frequency can be estimated for is shorter than that of a 2-D IC. Since the wiring area is
fixed chip area; or 3) number of interconnect levels can be proportional to , for comparable
estimated for fixed chip area and clock frequency. Simula- available wiring area, the wiring pitch in a 3-D IC can be
tion results of some of these tradeoff analyses are presented increased to reduce the interconnect delay. In a 3-D IC,
here. due to the constant cost function, c.f. , fewer
To estimate the clock frequency, we use a critical path interconnect levels per device layer are available as more
model that has a logic depth of 15. The logic gates are ap- device layers are integrated. Wiring area is also reduced
proximated by NAND gates with fan-in and fan-out of three. due to the via blockage of VILICs. Based on our modeling

318 PROCEEDINGS OF THE IEEE, VOL. 89, NO. 3, MARCH 2001

Table 3
Input Parameters for Random Logic Network/Microprocessor
Applications [37]

Fig. 21. Simulation results of total chip area for fixed clock
frequency and cost constraint. The total chip area is given by
NzAc, where Nz is the number of device layers and Ac is the die
area.

Fig. 20. Clock frequency of 2-D and 3-D IC as a function of

number of device layers for fixed chip area and cost function
constraints. Simulation results of clock frequency are presented
for both with and without repeaters inserted in the long wire. The
width/length ratio of the transistors in the critical path is five.

approach, there is an optimum number of device layers that Fig. 22. Interconnect delay limits IC performance with scaling.
can be integrated profitably to improve the clock frequency. Moving repeaters to upper active tiers reduces interconnect delay by
For the example being considered, it appears to be three to 9%. 3-D (two active layers) shows significant delay reduction (64%).
Increasing the number of metal levels in 3-D reduces interconnect
four. delay by a further 35%.
To estimate the impact of 3-D integration on chip area, an-
other set of tradeoff analyses can be performed. In this case
the clock frequency and the cost function are kept constant,
and the total chip area is estimated. The required chip area of similar analysis can be carried out for other approaches to
2-D and 3-D ICs for 450-MHz clock frequency, and c.f. 6 3-D integration as well.
is shown in Fig. 21. Assuming the interconnect delay is pro- Interconnect delay as a function of technology is calcu-
portional to - , for similar interconnect lated (Fig. 22) using data projected by the NTRS for 2-D
delay constraint, since the wire length in a 3-D IC is shorter, ICs. Also shown are delays for 3-D ICs with two active
the wiring pitch can be reduced. Both the shorter wire length layers, where wire pitches are increased to match the 2-D IC
and the flexibility to reduce the wiring pitch for fixed clock areas, calculated using the 3-D chip area estimation model
frequency constraint lead to the lower chip area in a 3-D IC. described above. Interconnect delay is reduced by 64% as a
The analysis presented so far was for a 180-nm 3-D tech- result. In all these calculations the number of metal levels is
nology for a fixed cost function. Next we extend this analysis conserved between 2-D and 3-D ICs. This assumption can
to study the effect of scaling the technology to smaller feature be relaxed such that each active layer in 3-D ICs may have
size, increasing the number available metal layers and active its own associated lower metal tiers with a universal global
Si layers. In the next set of analyses, the 3-D interconnect tier used for connecting the active-layer networks. The total
scheme being considered is shown in Fig. 16(b). However, number of metal layers is thus increased in this 3-D case.

DAVIS et al.: INTERCONNECT LIMITS ON GSI IN THE 21st CENTURY 319

 substrate is to deposit polysilicon and fabricate thin-film
transistors (TFT). To enhance the performance of TFTs,
an intense laser or electron beam is used to induced re-
crystallization of the polysilicon. This technique however
may not be very practical for 3-D devices because of the
high temperature involved during melting of the polysilicon
and also due to difficulty in controlling the grain size
variations. Beam recrystallized polysilicon films also suffer
from lower carrier mobilities and unintentional impurity
doping. However, high- performance TFTs fabricated using
low temperature processing, and even low-temperature
single-crystal Si TFTs have been recently demonstrated
[39], [40] that can be employed to fabricate advanced 3-D
circuits.
Processed Wafer Bonding: Another alternative is
Fig. 23. Signal delay for multiple active Si layers normalized to
single layer delay for worst case scenario, shown for 50-nm node.
to bond two fully processed wafers, on which chips are
fabricated on the surface including some interconnects,
such that the chips completely overlap [41]. Vias are etched
to electrically connect both chips after metallization. A
In estimating chip area, the metal requirement is calcu- backside of the bonded pair can be back-etched to allow
lated from the obtained wire-length distribution. The total for further processing or the bonding of more pairs in this
metallization requirement is appropriately divided among vertical fashion. Other advantages of this technology lie
the available metal layers in the corresponding technology. in the similar electrical properties of devices on all active
Thus in the example shown in Fig. 17, the local tier has levels and the independence of processing temperature since
three metal layers, the semiglobal one and the global two. all chips can be fabricated separately and later bonded. The
However, the chip area is determined by the resulting area of major limitation of this technique is its lack of precision
the local tier as it is the most densely packed. Consequently, (best case alignment m), which restricts the interchip
higher tiers are routed within a larger area. The resulting communication to global metal lines. However, for appli-
delays are also shown in Fig. 22. At the 50-nm node the cations where each chip is required to perform independent
delay improvement is an additional 35%. processing before communicating with its neighbor this
Fig. 23 compares the interconnect delay for up to five ac- technology can prove attractive.
tive layers for the 50-nm node. In this calculation only 10% Silicon Epitaxial Growth: Another technique for
of the interblock wires are assumed vertical and the number forming additional Si layers is to etch a hole in a passivated
of metal layers is conserved. Delay is shown to improve with wafer and epitaxially grow a single crystal Si seeded from
an increase in the number of active layers, however, with di- open window in the ILD. The silicon crystal grows vertically
minishing returns. This is due to the increase in the remaining and then laterally, to cover the ILD [42]. In principle,
lateral interblock wires as a fraction of the total wiring re- the quality of these fabricated devices can be as good as
quirement with increasing number of active layers. those fabricated underneath on the wafer surface since the
2) 3-D Technology Options: Although the concept of grown layer is single crystal with few defects. However,
3-D integration was demonstrated as early as in 1979 [38], it the high temperatures (1000 C) involved in this process
largely remained a research curiosity, since IC performance cause significant degradation in the quality of devices
was device limited. However, with the growing menace of on lower layers. Also this technique cannot be used over
delay in recent times, this technology is being viewed metallization layers. Low-temperature silicon epitaxy using
as a potential alternative that can not only maintain chip ultrahigh-vacuum chemical vapor deposition (UHV-CVD)
performance well beyond the 130-nm node, but also inspire has been recently developed [43]. However, this process is
a new generation of circuit design concepts. Presently, there not very attractive for batch processing.
are several possible fabrication technologies that can be used Solid Phase Crystallization (SPC): As an alternative
to realize multiple layers of active area (single crystal Si or to high-temperature epitaxial growth, low-temperature
recrystallized poly-Si) separated by interlayer dielectrics deposition and crystallization of amorphous silicon, which
(ILDs) for 3-D circuit processing. A brief description of passivates the lower active layer devices, can be employed.
these alternatives is given below. The choice of a particular The amorphous film can be randomly crystallized to form
technology for fabricating 3-D circuits will depend on the a polysilicon film. TFT performance can be enhanced by
requirements of the system, since the circuit performance is eliminating grain boundaries. For this purpose, local crys-
strongly influenced by the electrical characteristics of the tallization can be induced using low-temperature processes
fabricated devices as well as on the manufacturability and such as using patterned seeding of Germanium [44], or by
process compatibility with the relevant 2-D technology. using metal-induced lateral crystallization (MILC) [45],
Beam Recrystallization: A very popular method for [46]. This technique offers the flexibility of creating multiple
fabricating a second silicon layer on top of an existing active layers that are compatible with current processing

320 PROCEEDINGS OF THE IEEE, VOL. 89, NO. 3, MARCH 2001

environments, and recent results prove the feasibility of high-speed synchronous die-edge-length interconnects. In
building high-performance TFTs at low processing temper- addition, the absolute minimum energy per binary transition
atures that can be compatible with lower level metallization for reduced swing low-power interconnects is limited to
[47]. MILC, for example, can be used to build repeaters according to Shannon’s communication theorem.
above metal lines. It is found that the electrical character- At the material level, the resistivity of wire conductors in-
istics of these TFTs are approaching the single crystal SOI creases substantially in sub-50-nm technology. This increase
devices [48]. is primarily controlled by the scattering mechanisms due to
3) Concerns in 3-D Circuits: the properties of the surfaces and interfaces of copper films,
a) Thermal issues: An extremely important issue in as driven by 1- and 2-D scattering effects. This limit requires
3-D ICs is heat dissipation [49]. Thermal effects are already the development and optimization of M&P solutions that can
known to significantly impact interconnect and device reli- grow epitaxial Cu/liner interconnect stacks with atomically
ability in present 2-D circuits. The problem is expected to smooth surfaces and interfaces, while maximizing spec-
be exacerbated by the reduction in chip size, assuming that ular electron surface scattering in ultranarrow sub-50-nm
same power generated in a 2-D chip will now be generated interconnect lines. At the device level, both minimum
in a smaller 3-D chip, resulting in a sharp increase in the and reverse scaling strategies have a pronounced effect on
power density. Analysis of thermal problems in 3-D circuits interconnect crosstalk limits. Minimum interconnect scaling
is therefore necessary to comprehend the limitations of this significantly increases crosstalk on many GSI local and
technology, and also to evaluate the thermal robustness of semiglobal interconnects, and it is shown that the coupling
different 3-D technology options. length at which significant crosstalk ( ) occurs could
It is well known that most of the heat energy generated decrease by an order of magnitude over the next 15 years.
in integrated circuits arises due to transistor switching. This Reverse scaling of global interconnects causes inductance
heat is typically conducted through the silicon substrate to to significantly influence on-chip interconnect transients.
the package and then to the ambient by a heat sink. With Even with ideal return path conditions, mutual inductance
multilayer device designs, devices in the upper layers will increases crosstalk by up to 60% over that predicted by
also generate a significant fraction of the heat. Furthermore, conventional models. At the circuit level, transistor
all the active layers will be insulated from each other by driver output impedance in distributed interconnects
layers of dielectrics (LTO, HSQ, polyimide, etc.), which typ- circuits only exacerbates interconnect performance and
ically have much lower thermal conductivity than Si [50], crosstalk limits for semiglobal and local interconnects.
[51]. Hence, the heat dissipation issue can become even more When inductance is important ( ), careful
acute for 3-D ICs and can cause degradation in device per- driver design helps reduce overshoot and inductive crosstalk,
formance and reduction in chip reliability due to increased but potentially at the cost of excess circuit delay. Finally,
junction leakage, electromigration failures, and acceleration at the system level the continued historical approaches
of other failure mechanisms. However, initial analysis indi- to chip design are scrutinized. Using 2-D integration of
cates that thermal problems in 3-D circuits can be alleviated transistors and technology projections from the ITRS, the
by optimizing the interconnect capacitance, chip frequency number of metal levels explodes for highly connected logic
and the area. megacells that double in size every two years. Beyond
b) Interconnect capacitance and crosstalk: In 3-D de- 2005, the number of metal levels predicted with a stochastic
vices an additional electrical coupling between the top layer wiring distribution model reaches unattainable values such
metal of the first active layer and the devices on the second that by 2014 the number of metal levels is almost an order
active layer would be present [52]. This needs to be addressed of magnitude larger than what is projected by the ITRS.
at the circuit design stage. However, for deep submicrom- This result emphasizes that substantial changes in design
eter technologies, the aspect ratio of interconnects is approx- methodologies, technologies, and architectures are needed
imately 1.5–2. Thus, line-to-line capacitance is the dominant to cope with the onslaught of wiring demands. One possible
portion of the overall capacitance. Therefore, the presence solution to this problem that is highlighted in this paper is
of an additional silicon layer on top of a metal level will not the feasibility of 3-D integration of transistors. It has been
affect the capacitance per unit length of these lines. For tech- demonstrated that interconnect performance is significantly
nologies with very small aspect ratio, the change in intercon- improved by using 3-D ICs. By increasing the number of ac-
nect capacitance due to the presence of an additional silicon tive layers, including the use of separate layers for repeaters,
layer would be significant, as reported in [52]. and optimizing the wiring network, these results predict an
improvement in interconnect performance of up to 145% at
the 50-nm node. This modeling is also conservative, leaving
VII. CONCLUSION
room for further improvement, as optimization of logic
Twenty-first century interconnect limits are codified into block placement and connectivity is considered. Some of
fundamental, material, device, circuit and system limits. the major concerns for 3-D circuits are power dissipation
At the fundamental level, electromagnetic wave velocity and the associated thermal effects and additional complexity
will limit the performance of overly aggressive designs of introduced in fabrication technology.

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322 PROCEEDINGS OF THE IEEE, VOL. 89, NO. 3, MARCH 2001

 Jeffrey A. Davis received the B.E.E., M.S.E.E, Michael Beylansky received the B.S degree in chemistry from Moscow
and Ph.D. degrees in electrical engineering from University, Russia, in 1988, and the Ph.D degree in physical chemistry from
the Georgia Institute of Technology in 1993, the University of Illinois, Chicago, in 1998.
1997, and 1999, respectively. From 1988 to 1993, he worked at Moscow State University on synthesis
He joined the faculty at Georgia Tech as an and surface analysis of type IV-VI semiconductor heterostructures. He did
Assistant Professor in 1999. He is currently his post-doctoral work on copper interconnects at the Center for Advanced
serving as the Co-Program Chair for the 2001 Technology at the State University of New York (SUNY) at Albany. He
System Level Interconnect Prediction Workshop joined IBM Corporation Microelectronics Division, East Fishkill, NY, in
and is the Faculty Chair for the ECE stu- 2000, where he is Staff Engineer/Scientist in DRAM thin-film process de-
dent–faculty committee at Georgia Tech. He has velopment.
coauthored more than 30 conference and journal
publications during the past five years. His current research interests are in
the areas of high-speed interconnect modeling and optimization, high-speed
interconnect networks, optimal multilevel interconnect architectures, and
interconnect-centric design methodologies for future GSI processors.
Dr. Davis received the best student paper award at the 1999 International
Interconnect Technology Conference.

Shukri J. Souri received the B.A. degree in en-

gineering science from Oxford University, U.K.,
and the M.S. degree in electrical engineering
from Stanford University, Stanford, CA, in 1992
and 1994, respectively. He is currently pursuing
the Ph.D. degree from the Electrical Engineering
Department, Stanford University.
From 1994 to 1997, he was a Member of Tech-
nical Staff with the Corporate Research Division
of Raychem Corporation, Menlo Park, CA, where
Raguraman Venkatesan was born in Sindri, Bi- he worked on electroceramic semiconducting and
harstate, India, in 1976. He received the B.Tech. ferroelectric materials and devices for circuit protection applications. His re-
and M.S. degrees in electrical engineering from search interests include 3-D IC performance modeling and interconnect net-
the Indian Institute of Technology, Bombay, and work architecture. He has also worked on 3-D integration using advanced
the Georgia Institute of Technology, Atlanta, in seeding and crystallization techniques. He co-invented a number of U.S.
1998 and 2000, respectively. patents and has several publications in his areas of interest.
He is currently a Ph.D. student in the Gigas-
cale Integration Group at the Georgia Institute
of Technology. His research interests include
designing optimal multilevel wiring networks
and inductance modeling.

Kaustav Banerjee (Member, IEEE) received the

Ph.D. degree in electrical engineering and com-
puter sciences from the University of California,
Berkeley, in 1999.
Since March 1999, he has been with Stanford
University, Stanford, CA, as a Research Asso-
ciate at the Center for Integrated Systems. He
Alain Kaloyeros received the Ph.D. degree in also works as a technical consultant in the EDA
experimental condensed matter physics from the industry. His research interests include signal in-
University of Illinois, Urbana-Champaign, in tegrity, reliability and performance optimization
1987. issues in high-performance VLSI and high-fre-
He is Professor of Physics and Executive Di- quency (RF) mixed-signal applications. He is also interested in all aspects
rector of the University of Albany Institute for of integrated heterogeneous circuits and systems including System-on-Chip
Materials and its affiliated centers, including the designs. At Stanford, Dr. Banerjee leads an interdisciplinary research team
New York State Center for Advanced Tin Film of ten doctoral students. As part of the MARCO Interconnect Focus Center
Technology (CAT), the New York State Center of at Stanford, he is actively involved in the research of 3-D ICs. He is also
Excellence in Nanoelectronics, NanoFab 200 and involved in several collaborative research initiatives with other leading
the Energy and Environmental Technologies Ap- Universities. He co-advises doctoral students in the Electrical Engineering
plications Center (EETAC). He was also recently appointed Founding Dean Departments of the University of Southern California, Los Angeles, and
of the School of NanoSciences and Materials at UAlbany. He has authored the Swiss Federal Institute of Technology, Lausanne, Switzerland. He
and coauthored more than 100 articles and contributed to seven books on has held several summer research positions at the Semiconductor Process
topics pertaining to the science and technology of advanced semiconductor and Device Center of Texas Instruments Inc., Dallas, during 1993-1997.
and optoelectronics thin film materials, vapor phase processes, and high-res- He has authored or coauthored more than 40 research publications in
olution X-ray, electron, and photon-based characterization and metrology. archival journals and refereed international conferences and has presented
He holds nine U.S. patents. numerous invited talks and tutorials. At present, he serves on the organizing
Dr. Kaloyeras is a past recipient of the NSF Presidential Young Investi- committee of the International Symposium on Quality Electronic Design
gator (PYI) Award, the NSF Research Initiation Award (RIA), the Albany (ISQED), and on the technical program committees of the EOS/ESD
Foundation Academic Laureate Award, and the Citizen of the University Symposium, ISQED, and the International Reliability Physics Symposium
Award. (IRPS).

DAVIS et al.: INTERCONNECT LIMITS ON GSI IN THE 21st CENTURY 323

 Krishna C. Saraswat (Fellow, IEEE) received Rafael Reif (Fellow, IEEE) received the in-
the B.E. degree in Electronics and Telecommu- geniero electrico degree from Universidad de
nications in 1968 from Birla Institute of Tech- Carabobo, Valencia, Venezuela, in 1973, and the
nology and Science, Pilani, India, and the M.S. M.S. and Ph.D. degrees in electrical engineering
and Ph.D. degrees in electrical engineering from from Stanford University, Stanford, CA, in 1975
Stanford University, Stanford, CA, in 1969 and and 1979, respectively.
1974, respectively. From 1973 to 1974, he was an Assistant Pro-
During 1969-1970, he worked on microwave fessor at Universidad Simon Bolivar, Caracas,
transistors at Texas Instruments, Dallas, and Venezuela. In 1978, he became a Visiting As-
since 1971, he has been with Stanford Uni- sistant Professor at the Department of Electrical
versity, Stanford, CA, where he is presently a Engineering, Stanford University. In 1980, he
Professor of Electrical Engineering and Associate Director of the NSF/SRC joined the Massachusetts Institute of Technology, Cambridge, MA, where
Engineering Research Center for Environmentally Benign Semiconductor he is currently a Professor in the Department of Electrical Engineering,
Manufacturing. During 1996-97 he was the Director of the Integrated Cir- and Computer Science, and the Associate Department Head for Electrical
cuits Laboratory at Stanford. He is working on a variety of problems related Engineering. Professor Reif was the Director of MIT’s Microsystems
to new and innovative materials, device structures, and process technology Technology Laboratories (MTL) for the period 1990–1999. He is presently
of silicon devices and integrated circuits. His special areas of interest are working on future interconnect technologies, and on environmentally
thin-film MOS transistors (TFTs) on insulator for 3-D multilayer ICs, benign replacement chemistries for microelectronics fabrication.
thin-film technology for VLSI interconnections and contacts, process Dr. Reif held the Analog Devices Career Development Professorship of
and equipment modeling, ultrathin MOS gate dielectrics, rapid thermal MIT’s Department of Electrical Engineering and Computer Science, and
processing, and development of tools and methodology for simulation and was awarded the IBM Faculty Fellowship of MIT’s Center for Materials Sci-
control of a manufacturing technology. His group has developed several ence and Engineering from 1980 to 1982. He also received a United States
simulators for process, equipment and factory performance simulations, Presidential Young Investigator Award in 1984. He is a Member of Tau Beta
such as SPEEDIE for etch and deposition simulation, SCOPE for IC factory Pi, the Electrochemical Society, and the American Physical Society.
performance simulations, and a thermal simulator for RTP equipment
design. Currently, he is also involved in the development of an interconnect
process simulator. He has authored or coauthored more than 350 technical
papers. James D. Meindl (Fellow, IEEE) received the
Prof. Saraswat is a Member of The Electrochemical Society and The Ma- Ph.D. degree in electrical engineering from
terials Research Society. He received the Thomas D. Callinan Award by The Carnegie Mellon University, Pittsburgh, PA.
Electrochemical Society in May 2000 for his contributions to the dielectric He is the Director of the Joseph M. Pettit
science and technology. He was co-editor of the IEEE TRANSACTIONS ON Microelectronics Research Center and has been
ELECTRON DEVICES during 1988–1990. the Joseph M. Pettit Chair Professor of Micro-
electronics at Georgia Institute of Technology
since 1993. He was Senior Vice President for
Academic Affairs and Provost of Rensselaer
Polytechnic Institute from 1986 to 1993. He was
with Stanford University from 1967 to 1986 as
Arifur Rahman (Member, IEEE) was born in the John M. Fluke Professor of Electrical Engineering, Associate Dean for
Dhaka, Bangladesh. He received the B.S. degree Research in the School of Engineering, Director of the Center for Integrated
from Polytechnic University, NY, in 1994 and Systems, Director of the Electronics Laboratories and Founding Director
the M.S. degree from the Massachusetts Institute of the Integrated Circuits Laboratory.
of Technology (MIT), Cambridge, MA, in 1996, Dr. Meindl is a Fellow of the American Association for the Advancement
both in electrical engineering. Currently, he is of Science and a Member of the American Academy of Arts and Sciences
pursuing the Ph.D. degree at MIT. and the National Academy of Engineering and its academic advisory board.
His Ph.D. dissertation work is in modeling He received a Benjamin Garver Lamme Medal from ASEE, an IEEE Edu-
system performance and technology require- cation Medal, an IEEE Solid-State Circuits Medal, and an IEEE Beatrice K.
ments of three-dimensional integrated circuits. Winner Award. He has also been awarded the IEEE Electron Devices So-
His research interests are device physics and ciety’s J. J. Ebers Award, the Hamerschlag Distinguished Alumnus Award,
interconnect modeling. Carnegie Mellon University, the 1999 SIA University Research Award, and
Mr. Rahman is a Member of Tau Beta Pi. the IEEE Third Millennium Medal.

324 PROCEEDINGS OF THE IEEE, VOL. 89, NO. 3, MARCH 2001