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K.L.N. College of Engineering Microprocessor Objective Type Questions

This document contains 25 multiple choice questions related to microprocessors and the Intel 8085 microprocessor. Specifically, it tests knowledge about software interrupts, non-maskable interrupts, stack usage, machine cycles for instructions, the function of the program counter, assembly language instructions, carry flag behavior, interrupt prioritization, available registers, I/O mapping, reset behavior, address decoding, microprocessor software, timing states, EEPROM properties, machine/instruction cycles, characteristics that make the 8085 an 8-bit processor, the program counter register, microprocessor components, differences between mnemonic and machine codes, data bus width, memory addressing, addressing the first memory location, the purpose of the ALE signal, and maximum interfaced I

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63 views

K.L.N. College of Engineering Microprocessor Objective Type Questions

This document contains 25 multiple choice questions related to microprocessors and the Intel 8085 microprocessor. Specifically, it tests knowledge about software interrupts, non-maskable interrupts, stack usage, machine cycles for instructions, the function of the program counter, assembly language instructions, carry flag behavior, interrupt prioritization, available registers, I/O mapping, reset behavior, address decoding, microprocessor software, timing states, EEPROM properties, machine/instruction cycles, characteristics that make the 8085 an 8-bit processor, the program counter register, microprocessor components, differences between mnemonic and machine codes, data bus width, memory addressing, addressing the first memory location, the purpose of the ALE signal, and maximum interfaced I

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K.L.N.

COLLEGE OF ENGINEERING
MICROPROCESSOR
Objective Type Questions

1. The number of software interrupts in 8085 is ____ 


(a) 5 (b) 10 (c) 9 (d) 8
2. In 8085, example for non maskable interrupts is
(a)TRAP (b) RST 6.5 (c) INTR (d) RST 5.5
3. Which stack is used in 8085?
(a) FIFO (b) LIFO (c) FILO (d) LILO
4. How many and which types of machine cycles are needed to execute PUSH PSW by an Intel
8085 microprocessor?
(a) 2, Fetch and Memory write (b) 3, Fetch and 2 Memory write
(c) 3, Fetch and 2 Memory read (d) 3, Fetch, Memory read and
Memory write
5. Which one of the following statements for Intel 8085 is correct?
(a) Program counter (PC) specifies the address of the instruction last executed
(b) PC specifies the address of the instruction being executed
(c) PC specifies the address of the instruction to be executed
(d) PC specifies the number of instructions executed so far
6. Which one of the following 8085 assembly language instructions does not affect the contents of
the accumulator ?
(a) CMA (b) CMP B (c) DAA (d) ADD B
7. Carry flag is not affected after the execution of
(a) ADD B (b) SBB B (c) INR B (d) ORA B
8. Three devices P, Q and R have to be connected to an 8085 microprocessor. Device P has the
highest priority and device R has the lowest priority. L1 this context, which of the following is the
correct assignment of interrupt inputs?
(a) P uses TRAP, Q uses RST 5.5 and R uses RST 6.5
(b) P uses RST 5.5, Q uses RST 6.5 and R uses RST 7.5
(c) P uses RST 7.5, Q uses RST 6.5 and R uses RST 5.5
(d) P uses RST 5.5, Q uses RST 6.5 and R uses TRAP
9. Which register is not available for user in microprocessor?
(a) W (b) D (c) Z (d) Both a & c
10. In 8085 microprocessor how many I/O devices can be interfaced in I/O mapped I/O
technique?
(a) Either 256 input devices or 256 output devices. (b) 256 I/O devices.
(c) 256 input devices & 256 output devices. (d) 512 input-output devices.
11. In a microprocessor system, suppose. TRAP, HOLD, RESET Pin got activated at the same
time, while the processor was executing some instructions, then it will first respond to
(a) TRAP (b) HOLD (c) RESET (d) None
12. The ________ ensures that only one IC is active at a time to avoid a bus conflict caused by two
ICs writing different data to the same bus.
(a) control bus (b) control instructions (c)address decoder (d)CPU
13. The software used to drive microprocessor-based systems is called:
A. Assembly language B. Firmware
C. Machine language code D.BASIC interpreter instructions
14. In which T-state does the CPU sends the address to memory or I/O and the ALE signal
For demultiplexing
(A) T1. (B) T2. (C) T3. (D) T4.
15. Which of the following is true with respect to EEPROM?
(A) Contents can be erased byte wise only. B) Contents of full memory can be erased
together.
(C) Contents can be erased using ultra violet rays (D) contents cannot be erased
16. Which of the following statement is true?
(A) The group of machine cycle is called a state.
(B) A machine cycle consists of one or more instruction cycle.
(C) An instruction cycle is made up of machine cycles and a machine cycle is
made up of number of states.
(D) None of the above
17. Why 8085 processor is called an 8 bit processor?
a) Because 8085 processor has 8 bit ALU. b) Because 8085 processor has 8 bit data bus. c) a & b.
18. The register in the 8085A that is used to keep track of the memory address of the next op-code
to be run in the program is the:
A. Stack pointer B. program counter C. Instruction pointer D. Accumulator
19. Which of the following are the three basic sections of a microprocessor unit?
A. operand, register, and arithmetic/logic unit (ALU)
B. control and timing, register, and arithmetic/logic unit (ALU)
C. control and timing, register, and memory
D. arithmetic/logic unit (ALU), memory, and input/output
20. What is the difference between a mnemonic code and machine code?
A. There is no difference.
B. Machine codes are in binary, mnemonic codes are in shorthand English.
C. Machine codes are in shorthand English, mnemonic codes are in binary.
21. How many bits are used in the data bus?
A. 7 B. 8 C. 9 D. 16

22. A Micro processor with a 16 – bit address bus is used in a linear memory selection
configuration address bus lines are directly used as chip selects of memory chips with four
memory chips. The maximum addressable memory space is
a) 64K
b) 16 K
c) 8K
d) 4K
23. The memory address of the last location of a 1K byte memory chip is given as OFBFFH what
will be the address of the first location ?
a) OF817H
b) OF818H
c) OF8OOH
d) OF801H
24. What is the purpose of using ALE signal high ?
a) To latch low order address from bus to separate A0 – A7
b) To latch data Do – D 7 from bus go separate data bus
c) To disable data bus latch
25. The maximum number of I\o devices can be interfaced with 8085 in the I\o mapped I\o
technique are
a) 128
b) 256
c) 64
d) 1024

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