Virtex-6: FPGA Data Sheet: DC and Switching Characteristics

Virtex-6 FPGA Data Sheet:
DC and Switching Characteristics

DS152 (v3.6) March 18, 2014 Product Specification
Virtex-6 FPGA Electrical Characteristics

Virtex®-6 FPGAs are available in -3, -2, -1, and -1L speed grades, with -3 having the highest performance. Virtex-6 FPGA
DC and AC characteristics are specified in commercial, extended, industrial, and military temperature ranges. Unless noted,
the Virtex-6Q FPGA DC and AC characteristics are equivalent to the commercial specifications. Except for the operating
temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed
grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade
commercial device). However, only selected speed grades and/or devices are available in the extended, industrial, or military
temperature ranges.
All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters
included are common to popular designs and typical applications.
Available device and package combinations can be found at:
• DS150: Virtex-6 Family Overview
• DS155: Defense-Grade Virtex-6Q Family Overview
This Virtex-6 FPGA data sheet, part of an overall set of documentation on the Virtex-6 FPGAs, is available on the Xilinx
website at: www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_devices/fpga/virtex-6.html.
Virtex-6 FPGA DC Characteristics

Table 1: Absolute Maximum Ratings (1)
Symbol Description Range Units
Internal supply voltage relative to GND –0.5 to 1.1 V
VCCINT
For -1L devices: Internal supply voltage relative to GND –0.5 to 1.0 V
VCCAUX Auxiliary supply voltage relative to GND –0.5 to 3.0 V
VCCO Output drivers supply voltage relative to GND –0.5 to 3.0 V
VBATT Key memory battery backup supply –0.5 to 3.0 V
VFS External voltage supply for eFUSE programming(2) –0.5 to 3.0 V
VREF Input reference voltage –0.5 to 3.0 V
VIN(3) 2.5V or below I/O input voltage relative to GND(4) (user and dedicated I/Os) –0.5 to VCCO + 0.5 V
VTS Voltage applied to 3-state 2.5V or below output(4) (user and dedicated I/Os) –0.5 to VCCO + 0.5 V
TSTG Storage temperature (ambient) –65 to 150 °C
TSOL Maximum soldering temperature(5) +220 °C
Tj Maximum junction temperature(5) +125 °C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
2. When not programming eFUSE, connect VFS to GND.
3. 2.5V I/O absolute maximum limit applied to DC and AC signals.
4. For I/O operation, refer to UG361:Virtex-6 FPGA SelectIO Resources User Guide.
5. For soldering guidelines and thermal considerations, see UG365:Virtex-6 FPGA Packaging and Pinout Specification.
© 2009–2014 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Zynq, Artix, Kintex, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx in the
United States and other countries. All other trademarks are the property of their respective owners.
DS152 (v3.6) March 18, 2014 www.xilinx.com

Product Specification 1
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 2: Recommended Operating Conditions

Symbol Description Min Max Units
Internal supply voltage relative to GND for all devices except -1L devices. 0.95 1.05 V
For -1L commercial temperature range devices: internal supply voltage relative 0.87 0.93 V
VCCINT to GND, Tj = 0°C to +85°C
For -1L industrial temperature range devices: internal supply voltage relative to GND, 0.91 0.97 V
Tj = –40°C to +100°C
VCCAUX Auxiliary supply voltage relative to GND 2.375 2.625 V
VCCO(1)(2)(3) Supply voltage relative to GND 1.14 2.625 V
2.5V supply voltage relative to GND GND – 0.20 2.625 V
VIN
2.5V and below supply voltage relative to GND GND – 0.20 VCCO + 0.2 V
Maximum current through any pin in a powered or unpowered bank when forward – 10 mA
IIN(5)
biasing the clamp diode.
VBATT(6) Battery voltage relative to GND 1.0 2.5 V
VFS(7) External voltage supply for eFUSE programming 2.375 2.625 V
Junction temperature operating range for commercial (C) temperature devices 0 85 °C
Junction temperature operating range for extended (E) temperature devices 0 100 °C
Tj
Junction temperature operating range for industrial (I) temperature devices –40 100 °C
Junction temperature operating range for military (M) temperature devices –55 125 °C
Notes:
1. Configuration data is retained even if VCCO drops to 0V.
2. Includes VCCO of 1.2V, 1.5V, 1.8V, and 2.5V.
3. The configuration supply voltage VCC_CONFIG is also known as VCCO_0.
4. All voltages are relative to ground.
5. A total of 100 mA per bank should not be exceeded.
6. VBATT is required only when using bitstream encryption. If battery is not used, connect VBATT to either ground or VCCAUX.
7. During eFUSE programming, VFS must be within the recommended operating range and Tj = +15°C to +85°C. Otherwise, VFS can be
connected to GND.

Table 3: DC Characteristics Over Recommended Operating Conditions (1)(2)

Symbol Description Min Typ Max Units
VDRINT Data retention VCCINT voltage (below which configuration data might be lost) 0.75 – – V
VDRI Data retention VCCAUX voltage (below which configuration data might be lost) 2.0 – – V
IREF VREF leakage current per pin – – 10 µA
IL Input or output leakage current per pin (sample-tested) – – 10 µA
CIN(3) Die input capacitance at the pad – – 8 pF
Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V 20 – 80 µA
IRPU
IRPD Pad pull-down (when selected) @ VIN = 2.5V 3 – 80 µA
IBATT Battery supply current – – 150 nA
n Temperature diode ideality factor – 1.0002 – n
r Series resistance – 5 – Ω
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. Maximum value specified for worst case process at 25°C.
3. This measurement represents the die capacitance at the pad, not including the package.

Important Note
Typical values for quiescent supply current are specified at nominal voltage, 85°C junction temperatures (Tj). Xilinx
recommends analyzing static power consumption at Tj = 85°C because the majority of designs operate near the high end of
the commercial temperature range. Quiescent supply current is specified by speed grade for Virtex-6 devices. Use the Xilinx
Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate static power consumption
for conditions other than those specified in Table 4.
Table 4: Typical Quiescent Supply Current

Speed and Temperature Grade
Symbol Description Device Units
-3 (C) -2 (C, E, & I) -1 (C & I) -1 (I & M)(2) -1L (C) -1L (I)(1)
ICCINTQ Quiescent VCCINT XC6VLX75T 927 927 927 N/A 656 741 mA
supply current
XC6VLX130T 1563 1563 1563 N/A 1102 1245 mA
XC6VLX195T 2059 2059 2059 N/A 1441 1628 mA
XC6VLX240T 2478 2478 2478 N/A 1733 1957 mA
XC6VLX365T 3001 3001 3001 N/A 2092 2363 mA
XC6VLX550T(3) N/A 4515 4515 N/A 3147 3555 mA
XC6VLX760(3) N/A 5094 5094 N/A 3471 3921 mA
XC6VSX315T 3476 3476 3476 N/A 2409 2721 mA
XC6VSX475T(3) N/A 5227 5227 N/A 3622 4091 mA
XC6VHX250T 2906 2906 2906 N/A N/A N/A mA
XC6VHX255T 2746 2746 2746 N/A N/A N/A mA
XC6VHX380T(4) 4160 4160 4160 N/A N/A N/A mA
XC6VHX565T(5) N/A 5207 5207 N/A N/A N/A mA
XQ6VLX130T N/A 1563 N/A 1563 N/A 1245 mA
XQ6VLX240T N/A 2478 N/A 2478 N/A 1957 mA
XQ6VLX550T(7) N/A N/A N/A 4515 N/A 3555 mA
XQ6VSX315T N/A 3476 N/A 3476 N/A 2721 mA
XQ6VSX475T(7) N/A N/A N/A 5227 N/A 4091 mA

Table 4: Typical Quiescent Supply Current (Cont’d)

-3 (C) -2 (C, E, & I) -1 (C & I) -1 (I & M)(2) -1L (C) -1L (I)(1)
ICCOQ Quiescent VCCO XC6VLX75T 1 1 1 N/A 1 1 mA
supply current
XC6VLX130T 1 1 1 N/A 1 1 mA
XC6VLX195T 1 1 1 N/A 1 1 mA
XC6VLX240T 2 2 2 N/A 2 2 mA
XC6VLX365T 2 2 2 N/A 2 2 mA
XC6VLX550T(3) N/A 3 3 N/A 3 3 mA
XC6VLX760(3) N/A 3 3 N/A 3 3 mA
XC6VSX315T 2 2 2 N/A 2 2 mA
XC6VSX475T(3) N/A 2 2 N/A 2 2 mA
XC6VHX250T 1 1 1 N/A N/A N/A mA
XC6VHX255T 1 1 1 N/A N/A N/A mA
XC6VHX380T(4) 2 2 2 N/A N/A N/A mA
XQ6VLX130T N/A 1 N/A 1 N/A 1 mA
XQ6VLX240T N/A 2 N/A 2 N/A 2 mA
XQ6VSX315T N/A 2 N/A 2 N/A 2 mA

Table 4: Typical Quiescent Supply Current (Cont’d)

-3 (C) -2 (C, E, & I) -1 (C & I) -1 (I & M)(2) -1L (C) -1L (I)(1)
ICCAUXQ Quiescent VCCAUX XC6VLX75T 45 45 45 N/A 45 45 mA
supply current
XC6VLX130T 75 75 75 N/A 75 75 mA
XC6VLX195T 113 113 113 N/A 113 113 mA
XC6VLX240T 135 135 135 N/A 135 135 mA
XC6VLX365T 191 191 191 N/A 191 191 mA
XC6VLX550T(3) N/A 286 286 N/A 286 286 mA
XC6VLX760(3) N/A 387 387 N/A 387 387 mA
XC6VSX315T 186 186 186 N/A 186 186 mA
XC6VSX475T(3) N/A 279 279 N/A 279 279 mA
XC6VHX250T 152 152 152 N/A N/A N/A mA
XC6VHX255T 152 152 152 N/A N/A N/A mA
XC6VHX380T(4) 227 227 227 N/A N/A N/A mA
XQ6VLX130T(6) N/A 75 N/A 75 N/A 75 mA
XQ6VLX240T(6) N/A 135 N/A 135 N/A 135 mA
XQ6VSX315T(6) N/A 186 N/A 186 N/A 186 mA
Notes:
1. Typical values are specified at nominal voltage, 85°C junction temperatures (Tj). -1 and -2 industrial (I) grade devices have the same typical
values as commercial (C) grade devices at 85°C, but higher values at 100°C. Use the XPE tool to calculate 100°C values. -1L industrial
temperature range devices have the values specified in this column.
2. Use the XPE tool to calculate 125°C values for -1M temperature range devices.
3. The -2E extended temperature range (Tj = 0°C to +100°C) is only available in these devices. The -2I temperature range (Tj = –40°C to
+100°C) is available for all other devices except the XC6VHX565T.
4. The XC6VHX380T is available with both -2E and -2I temperature ranges.
5. The XC6VHX565T is only available in the following temperature ranges: -1C, -1I, -2C, and -2E.
6. The XQ6VLX130T, XQ6VLX240T, and XQ6VSX315T are available in -2I, -1I, -1M, and -1LI temperature ranges.
7. The XQ6VLX550T and the XQ6VSX475T are only available in -1I and -1LI temperature ranges.
8. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and
floating.
9. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the XPE or XPower Analyzer
(XPA) tools.
Power-On Power Supply Requirements

Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device initialization. The actual
current consumed depends on the power-on sequence and ramp rate of the power supply.
The recommended power-on sequence for Virtex-6 devices is VCCINT, VCCAUX, and VCCO to meet the power-up current
requirements listed in Table 5. VCCINT can be powered up or down at any time, but power up current specifications can vary
from Table 5. The device will have no physical damage or reliability concerns if VCCINT, VCCAUX, and VCCO sequence cannot
be followed.
If the recommended power-up sequence cannot be followed and the I/Os must remain 3-stated throughout configuration,
then VCCAUX must be powered prior to VCCO or VCCAUX and VCCO must be powered by the same supply. Similarly, for power-
down, the reverse VCCAUX and VCCO sequence is recommended if the I/Os are to remain 3-stated.

The GTH transceiver supplies must be powered using a MGTHAVCC, MGTHAVCCRX, MGTHAVCCPLL, and MGTHAVTT
sequence. There are no sequencing requirement for these supplies with respect to the other FPGA supply voltages. For
more detail see Table 27: GTH Transceiver Power Supply Sequencing. There are no sequencing requirements for the GTX
transceivers power supplies.
Table 5 shows the minimum current, in addition to ICCQ, that are required by Virtex-6 devices for proper power-on and
configuration. If the current minimums shown in Table 4 and Table 5 are met, the device powers on after all three supplies
have passed through their power-on reset threshold voltages. The FPGA must be configured after applying VCCINT, VCCAUX,
and VCCO for the appropriate configuration banks. Once initialized and configured, use the XPE tools to estimate current
drain on these supplies.
Table 5: Power-On Current for Virtex-6 Devices

ICCINTMIN ICCAUXMIN ICCOMIN
Device Units
Typ(1) Typ(1) Typ(1)
XC6VLX75T See ICCINTQ in Table 4 ICCAUXQ + 10 ICCOQ + 30 mA per bank mA
XC6VLX760 See ICCINTQ in Table 4 ICCAUXQ + 40 ICCOQ + 30 mA per bank mA
XC6VSX315T See ICCINTQ in Table 4 ICCAUXQ + 40 ICCOQ + 30 mA per bank mA
XC6VSX475T See ICCINTQ in Table 4 ICCAUXQ + 50 ICCOQ + 30 mA per bank mA
XC6VHX250T See ICCINTQ in Table 4 ICCAUXQ + 40 ICCOQ + 30 mA per bank mA
XQ6VLX130T See ICCINTQ in Table 4 ICCAUXQ + 100 ICCOQ + 30 mA per bank mA
XQ6VSX315T See ICCINTQ in Table 4 ICCAUXQ + 100 ICCOQ + 40 mA per bank mA
XQ6VSX475T See ICCINTQ in Table 4 ICCAUXQ + 100 ICCOQ + 40 mA per bank mA
Notes:
2. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate maximum power-on currents.
Table 6: Power Supply Ramp Time

Symbol Description Ramp Time Units
VCCINT Internal supply voltage relative to GND 0.20 to 50.0 ms
VCCO Output drivers supply voltage relative to GND 0.20 to 50.0 ms
VCCAUX Auxiliary supply voltage relative to GND 0.20 to 50.0 ms

SelectIO™ DC Input and Output Levels

Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended
operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that
all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and
VOH voltage levels shown. Other standards are sample tested.
Table 7: SelectIO DC Input and Output Levels

VIL VIH VOL VOH IOL IOH
I/O Standard
V, Min V, Max V, Min V, Max V, Max V, Min mA mA
LVCMOS25, –0.3 0.7 1.7 VCCO + 0.3 0.4 VCCO – 0.4 Note(3) Note(3)
LVDCI25
LVCMOS18, –0.3 35% VCCO 65% VCCO VCCO + 0.3 0.45 VCCO – 0.45 Note(4) Note(4)
LVDCI18
LVCMOS15, –0.3 35% VCCO 65% VCCO VCCO + 0.3 25% VCCO 75% VCCO Note(4) Note(4)
LVDCI15
LVCMOS12 –0.3 35% VCCO 65% VCCO VCCO + 0.3 25% VCCO 75% VCCO Note(5) Note(5)
HSTL I_12 –0.3 VREF – 0.1 VREF + 0.1 VCCO + 0.3 25% VCCO 75% VCCO 6.3 –6.3
HSTL I(2) –0.3 VREF – 0.1 VREF + 0.1 VCCO + 0.3 0.4 VCCO – 0.4 8 –8
HSTL II(2) –0.3 VREF – 0.1 VREF + 0.1 VCCO + 0.3 0.4 VCCO – 0.4 16 –16
HSTL III(2) –0.3 VREF – 0.1 VREF + 0.1 VCCO + 0.3 0.4 VCCO – 0.4 24 –8
DIFF HSTL I(2) –0.3 50% VCCO – 0.1 50% VCCO + 0.1 VCCO + 0.3 – – – –
DIFF HSTL II(2) –0.3 50% VCCO – 0.1 50% VCCO + 0.1 VCCO + 0.3 – – – –
SSTL2 I –0.3 VREF – 0.15 VREF + 0.15 VCCO + 0.3 VTT – 0.61 VTT + 0.61 8.1 –8.1
SSTL2 II –0.3 VREF – 0.15 VREF + 0.15 VCCO + 0.3 VTT – 0.81 VTT + 0.81 16.2 –16.2
DIFF SSTL2 I –0.3 50% 50% VCCO + 0.3 – – – –
VCCO – 0.15 VCCO + 0.15
DIFF SSTL2 II –0.3 50% 50% VCCO + 0.3 – – – –
VCCO – 0.15 VCCO + 0.15
SSTL18 I –0.3 VREF – 0.125 VREF + 0.125 VCCO + 0.3 VTT – 0.47 VTT + 0.47 6.7 –6.7
SSTL18 II –0.3 VREF – 0.125 VREF + 0.125 VCCO + 0.3 VTT – 0.60 VTT + 0.60 13.4 –13.4
DIFF SSTL18 I –0.3 50% 50% VCCO + 0.3 – – – –
VCCO – 0.125 VCCO + 0.125
DIFF SSTL18 II –0.3 50% 50% VCCO + 0.3 – – – –
VCCO – 0.125 VCCO + 0.125
SSTL15 –0.3 VREF – 0.1 VREF + 0.1 VCCO + 0.3 VTT – 0.175 VTT + 0.175 14.3 –14.3
DIFF SSTL15 –0.3 50% VCCO – 0.1 50% VCCO + 0.1 VCCO + 0.3 – – – –
Notes:
1. Tested according to relevant specifications.
2. Applies to both 1.5V and 1.8V HSTL.
3. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA.
4. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA.
5. Supported drive strengths of 2, 4, 6, or 8 mA.
6. For detailed interface specific DC voltage levels, see UG361:Virtex-6 FPGA SelectIO Resources User Guide.

HT DC Specifications (HT_25)
Table 8: HT DC Specifications
Symbol DC Parameter Conditions Min Typ Max Units
VCCO Supply Voltage 2.38 2.5 2.63 V
VOD Differential Output Voltage for XC devices RT = 100 Ω across Q and Q signals 480 600 885 mV
Differential Output Voltage for XQ devices 480 600 930 mV
Δ VOD Change in VOD Magnitude –15 – 15 mV
VOCM Output Common Mode Voltage RT = 100 Ω across Q and Q signals 440 600 760 mV
Δ VOCM Change in VOCM Magnitude –15 – 15 mV
VID Input Differential Voltage 200 600 1000 mV
Δ VID Change in VID Magnitude –15 – 15 mV
VICM Input Common Mode Voltage 440 600 780 mV
Δ VICM Change in VICM Magnitude –15 – 15 mV
LVDS DC Specifications (LVDS_25)

Table 9: LVDS DC Specifications
VOH Output High Voltage for Q and Q RT = 100 Ω across Q and Q signals – – 1.675 V
VOL Output Low Voltage for Q and Q RT = 100 Ω across Q and Q signals 0.825 – – V
VODIFF Differential Output Voltage (Q – Q), RT = 100 Ω across Q and Q signals 247 350 600 mV
Q = High (Q – Q), Q = High
VOCM Output Common-Mode Voltage for XC devices RT = 100 Ω across Q and Q signals 1.075 1.250 1.425 V
Output Common-Mode Voltage for XQ devices 1.000 1.250 1.425 V
VIDIFF Differential Input Voltage (Q – Q), 100 350 600 mV
VICM Input Common-Mode Voltage 0.3 1.2 2.2 V
Extended LVDS DC Specifications (LVDSEXT_25)

Table 10: Extended LVDS DC Specifications
VOH Output High Voltage for Q and Q RT = 100 Ω across Q and Q signals – – 1.785 V
VOL Output Low Voltage for Q and Q RT = 100 Ω across Q and Q signals 0.715 – – V
VODIFF Differential Output Voltage (Q – Q), RT = 100 Ω across Q and Q signals 350 – 840 mV
for XC devices
Differential Output Voltage (Q – Q), 350 – 850 mV
for XQ devices
VOCM Output Common-Mode Voltage for XC devices RT = 100 Ω across Q and Q signals 1.075 1.250 1.425 V
Output Common-Mode Voltage for XQ devices 1.000 1.250 1.425 V
VIDIFF Differential Input Voltage (Q – Q), Common-mode input 100 – 1000 mV
Q = High (Q – Q), Q = High voltage = 1.25V
VICM Input Common-Mode Voltage Differential input voltage = ±350 mV 0.3 1.2 2.2 V

LVPECL DC Specifications (LVPECL_25)

These values are valid when driving a 100Ω differential load only, i.e., a 100Ω resistor between the two receiver pins. The
VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode
ranges. Table 11 summarizes the DC output specifications of LVPECL. For more information on using LVPECL, see UG361:
Virtex-6 FPGA SelectIO Resources User Guide.
Table 11: LVPECL DC Specifications

Symbol DC Parameter Min Typ Max Units
VOH Output High Voltage VCC – 1.025 1.545 VCC – 0.88 V
VOL Output Low Voltage VCC – 1.81 0.795 VCC – 1.62 V
VICM Input Common-Mode Voltage 0.6 – 2.2 V
VIDIFF Differential Input Voltage(1)(2) 0.100 – 1.5 V
Notes:
1. Recommended input maximum voltage not to exceed VCCAUX + 0.2V.
2. Recommended input minimum voltage not to go below –0.5V.
eFUSE Read Endurance

Table 12 lists the maximum number of read cycle operations expected. For more information, see UG360:Virtex-6 FPGA
Configuration User Guide.
Table 12: eFUSE Read Endurance

Speed Grade
Symbol Description Units
-3 -2 -1 -1L
DNA_CYCLES Number of DNA_PORT READ operations or JTAG ISC_DNA read Read
30,000,000
command operations. Unaffected by SHIFT operations. Cycles
AES_CYCLES Number of JTAG FUSE_KEY or FUSE_CNTL read command 30,000,000 Read
operations. Unaffected by SHIFT operations. Cycles

GTX Transceiver Specifications

GTX Transceiver DC Characteristics
Table 13: Absolute Maximum Ratings for GTX Transceivers(1)
Analog supply voltage for the GTX transmitter and receiver circuits relative to –0.5 1.1 V
MGTAVCC
GND
Analog supply voltage for the GTX transmitter and receiver termination circuits –0.5 1.32 V
MGTAVTT
relative to GND
Analog supply voltage for the resistor calibration circuit of the GTX transceiver –0.5 1.32 V
MGTAVTTRCAL
column
VIN Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage –0.5 1.32 V
VMGTREFCLK Reference clock absolute input voltage –0.5 1.32 V
Notes:
Table 14: Recommended Operating Conditions for GTX Transceivers(1)(2)

Speed PLL
Grade Frequency
-3, -2(3) > 2.7 GHz 1.0 1.03 1.06 V
Analog supply voltage for the GTX transmitter -3, -2(3) ≤ 2.7 GHz 0.95 1.0 1.06 V
MGTAVCC
and receiver circuits relative to GND -1 ≤ 2.7 GHz 0.95 1.0 1.06 V
-1L ≤ 2.7 GHz 0.95 1.0 1.05 V
Analog supply voltage for the GTX transmitter
MGTAVTT All – 1.14 1.2 1.26 V
and receiver termination circuits relative to GND
Analog supply voltage for the resistor calibration
MGTAVTTRCAL All – 1.14 1.2 1.26 V
circuit of the GTX transceiver column
Notes:
1. Each voltage listed requires the filter circuit described in UG366:Virtex-6 FPGA GTX Transceivers User Guide.
2. Voltages are specified for the temperature range of Tj = –40°C to +100°C for all XC devices and Tj = –55°C to +125°C for the XQ devices
3. If a GTX Quad contains transceivers operating with a mixture of PLL frequencies above and below 2.7 GHz, the MGTAVCC voltage supply
must be in the range of 1.0V to 1.06V.
Table 15: GTX Transceiver Supply Current (per Lane) (1)(2)

Symbol Description Typ Max Units
IMGTAVTT MGTAVTT supply current for one GTX transceiver 55.9 mA
Note 2
IMGTAVCC MGTAVCC supply current for one GTX transceiver 56.1 mA
MGTRREF Precision reference resistor for internal calibration termination 100.0 ± 1% tolerance Ω
Notes:
1. Typical values are specified at nominal voltage, 25°C, with a 3.125 Gb/s line rate.
2. Values for currents of other transceiver configurations and conditions can be obtained by using the Xilinx Power Estimator (XPE) or XPower
Analyzer (XPA) tools.

Table 16: GTX Transceiver Quiescent Supply Current (per Lane) (1)(2)(3)
Symbol Description Typ(4) Max Units
IMGTAVTTQ Quiescent MGTAVTT supply current for one GTX transceiver 0.9 mA
Note 2
IMGTAVCCQ Quiescent MGTAVCC supply current for one GTX transceiver 3.5 mA
Notes:
1. Device powered and unconfigured.
2. Currents for conditions other than values specified in this table can be obtained by using the XPE or XPA tools.
3. GTX transceiver quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of
available GTX transceivers.
GTX Transceiver DC Input and Output Levels

Table 17 summarizes the DC output specifications of the GTX transceivers in Virtex-6 FPGAs. Consult UG366:Virtex-6
FPGA GTX Transceivers User Guide for further details.
Table 17: GTX Transceiver DC Specifications

Differential peak-to-peak input External AC coupled ≤ 4.25 Gb/s 125 – 2000 mV
DVPPIN voltage
External AC coupled > 4.25 Gb/s 175 – 2000 mV
Absolute input voltage DC coupled –400 – MGTAVTT mV
VIN
MGTAVTT = 1.2V
Common mode input voltage DC coupled – 2/3 MGTAVTT – mV
VCMIN
MGTAVTT = 1.2V
Differential peak-to-peak output Transmitter output swing is set to – – 1000 mV
DVPPOUT
voltage (1) maximum setting
DC common mode output Equation based MGTAVTT – DVPPOUT/4 mV
VCMOUTDC
voltage.
RIN Differential input resistance 80 100 130 Ω
ROUT Differential output resistance 80 100 120 Ω
TOSKEW Transmitter output pair (TXP and TXN) intra-pair skew – 2 8 ps
CEXT Recommended external AC coupling capacitor(2) – 100 – nF
Notes:
1. The output swing and preemphasis levels are programmable using the attributes discussed in UG366:Virtex-6 FPGA GTX Transceivers User
Guide and can result in values lower than reported in this table.
2. Other values can be used as appropriate to conform to specific protocols and standards.
X-Ref Target - Figure 1
+V P
Single-Ended
N Voltage
0 ds152_01_121509
Figure 1: Single-Ended Peak-to-Peak Voltage

+V
0 Differential
Voltage
–V P–N
ds152_02_121509
Figure 2: Differential Peak-to-Peak Voltage
Table 18 summarizes the DC specifications of the clock input of the GTX transceiver. Consult UG366:Virtex-6 FPGA GTX
Transceivers User Guide for further details.
Table 18: GTX Transceiver Clock DC Input Level Specification

Symbol DC Parameter Min Typ Max Units
VIDIFF Differential peak-to-peak input voltage 210 800 2000 mV
CEXT Required external AC coupling capacitor(1) – 100 – nF
Notes:
GTX Transceiver Switching Characteristics

Consult UG366:Virtex-6 FPGA GTX Transceivers User Guide for further information.
Table 19: GTX Transceiver Performance

Speed Grade
-3 -2 -1 -1L
FGTXMAX Maximum GTX transceiver data rate 6.6 6.6 5.0 5.0 Gb/s
FGPLLMAX Maximum PLL frequency 3.3(1) 3.3(1) 2.7 2.7 GHz
FGPLLMIN Minimum PLL frequency 1.2 1.2 1.2 1.2 GHz
Notes:
1. See Table 14 for MGTAVCC requirements when PLL frequency is greater than 2.7 GHz.
Table 20: GTX Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Speed Grade
-3 -2 -1 -1L
FGTXDRPCLK GTXDRPCLK maximum frequency 150 150 125 100 MHz

Table 21: GTX Transceiver Reference Clock Switching Characteristics

All Speed Grades
Symbol Description Conditions Units
Min Typ Max
FGCLK Reference clock frequency range 62.5 – 650 MHz
TRCLK Reference clock rise time 20% – 80% – 200 – ps
TFCLK Reference clock fall time 80% – 20% – 200 – ps
TDCREF Reference clock duty cycle Transceiver PLL only 45 50 55 %
Clock recovery frequency acquisition – – 1 ms
TLOCK Initial PLL lock
time
Lock to data after PLL has locked – – 200 µs
TPHASE Clock recovery phase acquisition time
to the reference clock
TRCLK
80%
20%
TFCLK
ds152_05_042109
Figure 3: Reference Clock Timing Parameters
Table 22: GTX Transceiver User Clock Switching Characteristics(1)

Speed Grade
-3 -2 -1 -1L
Internal 20-bit data path 330 330 250 250 MHz
FTXOUT TXOUTCLK maximum frequency
Internal 16-bit data path 412.5 412.5 312.5 250 MHz
Internal 20-bit data path 330 330 250 250 MHz
FRXREC RXRECCLK maximum frequency
Internal 16-bit data path 412.5 412.5 312.5 250 MHz
TRX RXUSRCLK maximum frequency 412.5(2) 412.5(2) 312.5 250 MHz
1 byte interface 376 376 312.5 250 MHz
TRX2 RXUSRCLK2 maximum frequency 2 byte interface 406.25 406.25 312.5 250 MHz
4 byte interface 206.25 206.25 156.25 125 MHz
TTX TXUSRCLK maximum frequency 412.5(3) 412.5(3) 312.5 250 MHz
1 byte interface 376 376 312.5 250 MHz
TTX2 TXUSRCLK2 maximum frequency 2 byte interface 406.25 406.25 312.5 250 MHz
4 byte interface 206.25 206.25 156.25 125 MHz
Notes:
1. Clocking must be implemented as described in UG366:Virtex-6 FPGA GTX Transceivers User Guide.
2. 406.25 MHz when the RX elastic buffer is bypassed.
3. 406.25 MHz when the TX buffer is bypassed.

Table 23: GTX Transceiver Transmitter Switching Characteristics

Symbol Description Condition Min Typ Max Units
FGTXTX Serial data rate range 0.480 – FGTXMAX Gb/s
TRTX TX Rise time 20%–80% – 120 – ps
TFTX TX Fall time 80%–20% – 120 – ps
TLLSKEW TX lane-to-lane skew(1) – – 350 ps
VTXOOBVDPP Electrical idle amplitude – – 15 mV
TTXOOBTRANSITION Electrical idle transition time – – 75 ns
TJ6.5 Total Jitter(2)(3) – – 0.33 UI
6.5 Gb/s
DJ6.5 Deterministic Jitter(2)(3) – – 0.17 UI
5.0 Gb/s
4.25 Gb/s
3.75 Gb/s
3.125 Gb/s
TJ3.125L Total Jitter(2)(3) – – 0.35 UI
3.125 Gb/s(4)
DJ3.125L Deterministic Jitter(2)(3) – – 0.16 UI
2.5 Gb/s(5)
1.25 Gb/s(6)
TJ600 Total Jitter(2)(3) – – 0.1 UI
600 Mb/s
DJ600 Deterministic Jitter(2)(3) – – 0.03 UI
TJ480 Total Jitter(2)(3) – – 0.1 UI
480 Mb/s
DJ480 Deterministic Jitter(2)(3) – – 0.03 UI
Notes:
1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to 12 consecutive transmitters (three fully populated GTX Quads).
2. Using PLL_DIVSEL_FB = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
3. All jitter values are based on a bit-error ratio of 1e-12.
4. PLL frequency at 1.5625 GHz and OUTDIV = 1.

Table 24: GTX Transceiver Receiver Switching Characteristics

RX oversampler not enabled 0.600 – FGTXMAX Gb/s
FGTXRX Serial data rate
RX oversampler enabled 0.480 – 0.600 Gb/s
TRXELECIDLE Time for RXELECIDLE to respond to loss or restoration of data – 75 – ns
RXOOBVDPP OOB detect threshold peak-to-peak 60 – 150 mV
Receiver spread-spectrum –5000 – 0 ppm
RXSST Modulated @ 33 KHz
tracking(1)
RXRL Run length (CID) Internal AC capacitor bypassed – – 512 UI
Data/REFCLK PPM offset CDR 2nd-order loop disabled –200 – 200 ppm
RXPPMTOL
tolerance CDR 2nd-order loop enabled –2000 – 2000 ppm
SJ Jitter Tolerance(2)
JT_SJ6.5 Sinusoidal Jitter(3) 6.5 Gb/s 0.44 – – UI
JT_SJ3.125L Sinusoidal Jitter(3) 3.125 Gb/s(4) 0.45 – – UI
JT_SJ2.5 Sinusoidal Jitter(3) 2.5 Gb/s(5) 0.5 – – UI
JT_SJ1.25 Sinusoidal Jitter(3) 1.25 Gb/s(6) 0.5 – – UI
JT_SJ600 Sinusoidal Jitter(3) 600 Mb/s 0.4 – – UI
JT_SJ480 Sinusoidal Jitter(3) 480 Mb/s 0.4 – – UI
SJ Jitter Tolerance with Stressed Eye(2)
3.125 Gb/s 0.70 – – UI
JT_TJSE3.125 Total Jitter with Stressed Eye(7)
5.0 Gb/s 0.70 – – UI
Sinusoidal Jitter with Stressed 3.125 Gb/s 0.1 – – UI
JT_SJSE3.125
Eye(7) 5.0 Gb/s 0.1 – – UI
Notes:
1. Using PLL_RXDIVSEL_OUT = 1, 2, and 4.
2. All jitter values are based on a bit error ratio of 1e–12.
3. The frequency of the injected sinusoidal jitter is 80 MHz.
7. Composite jitter with RX equalizer enabled. DFE disabled.

GTH Transceiver Specifications

GTH Transceiver DC Characteristics
Table 25: Absolute Maximum Ratings for GTH Transceivers(1)
Analog supply voltage for the GTH transmitter, receiver, and common analog –0.5 1.125 V
MGTHAVCC
circuits
MGTHAVCCRX Analog supply voltage for the GTH receiver circuits and common analog circuits –0.5 1.125 V
MGTHAVTT Analog supply voltage for the GTH transmitter termination circuits –0.5 1.32 V
MGTHAVCCPLL Analog supply voltage for the GTH receiver and PLL circuits –0.5 1.935 V
VIN Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage –0.5 1.125 V
VMGTREFCLK Reference clock absolute input voltage –0.5 1.935 V
Notes:
Table 26: Recommended Operating Conditions for GTH Transceivers (1)(2)

Analog supply voltage for the GTH transmitter, receiver, and common analog 1.075 1.1 1.125 V
MGTHAVCC
circuits
Analog supply voltage for the GTH receiver circuits and common analog 1.075 1.1 1.125 V
MGTHAVCCRX
circuits
MGTHAVTT Analog supply voltage for the GTH transmitter termination circuits 1.140 1.2 1.26 V
MGTHAVCCPLL Analog supply voltage for the GTH receiver and PLL circuit 1.710 1.8 1.89 V
Notes:
1. Each voltage listed requires the filter circuit described in UG371:Virtex-6 FPGA GTH Transceivers User Guide.
2. Voltages are specified for the temperature range of Tj = –40°C to +100°C.
Table 27: GTH Transceiver Power Supply Sequencing (1)(2)(3)

Maximum time between powering MGTHAVCC to when MGTHAVCCRX
THAVCC2HAVCCRX 0 5 ms
must be powered.
Minimum time between powering MGTHAVCCRX to when
THAVCCRX2HAVCCPLL 10 – µs
MGTHAVCCPLL can be powered.
Minimum time between powering MGTHAVCCRX to when MGTHAVTT
THAVCCRX2HAVTT 10 – µs
can be powered.
Notes:
1. MGTHAVCCRX must be powered simultaneously or within THAVCC2HAVCCRX of MGTHAVCC, but it must not precede MGTHAVCC.
2. MGTHAVCC and MGTHAVCCRX must be powered before MGTHAVCCPLL and MGTHAVTT. This minimum time is defined by
THAVCCRX2HAVCCPLL and THAVCCRX2HAVTT.
3. At any time, the condition of MGTHAVCC being present and MGTHAVCCRX not being present should not occur for more than the maximum
THAVCC2HAVCCRX.

Figure 4 shows the timing parameters in Table 27.

MGTHAVCC
(1.1V DC)
THAVCC2HAVCCRX
MGTHAVCCRX
(1.1V DC)
THAVCCRX2HAVCCPLL
MGTHAVCCPLL
(1.8V DC)
THAVCCRX2HAVTT
MGTHAVTT
(1.2V DC)
DS152_04_051110
Figure 4: GTH Transceiver Power Supply Power-On Sequencing
Table 28: GTH Transceiver Supply Current

IMGTHAVCC MGTHAVCC supply current for one GTH Quad (4 lanes) 571 Note 2 mA
IMGTHAVCCRX MGTHAVCCRX supply current for a GTH Quad (4 lanes) 254 Note 2 mA
IMGTHAVTT MGTHAVTT supply current for one GTH Quad (4 lanes) 93 Note 2 mA
IMGTHAVCCPLL MGTHAVCCPLL supply current for one GTH Quad (4 lanes) 219 Note 2 mA
MGTRREF Precision reference resistor for internal calibration termination 1000.0 ± 1% tolerance Ω
Notes:
1. Typical values are specified at nominal voltage, 25°C, with a 10.3125 Gb/s line rate.
2. Values for currents other than the values specified in this table can be obtained by using the Xilinx Power Estimator (XPE) or XPower
Analyzer (XPA) tools.
Table 29: GTH Transceiver Quiescent Supply Current(1)(2)

IMGTHAVCCQ Quiescent MGTHAVCC Supply Current for one GTH Quad (4 lanes) 65 Note 4 mA
IMGTHAVCCRXQ Quiescent MGTHAVCCRX Supply Current for one GTH Quad (4 lanes) 17 Note 4 mA
IMGTHAVTTQ Quiescent MGTHAVTT Supply Current for one GTH Quad (4 lanes) 1 Note 4 mA
IMGTHAVCCPLLQ Quiescent MGTHAVCCPLL Supply Current for one GTH Quad (4 lanes) 1 Note 4 mA
Notes:
1. Device powered and unconfigured.
2. GTH transceiver quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of
available GTH transceivers.
4. Currents for conditions other than values specified in this table can be obtained by using the XPE or XPA tools.

GTH Transceiver DC Input and Output Levels

Table 30 summarizes the DC output specifications of the GTH transceivers in Virtex-6 FPGAs. Consult UG371:Virtex-6
FPGA GTH Transceivers User Guide for further details.
Table 30: GTH Transceiver DC Specifications

DVPPIN Differential peak-to-peak input voltage External AC coupled 175 – 1200 mV
Differential peak-to-peak output Transmitter output swing is set to 800 – 1200 mV
DVPPOUT
voltage (1) maximum setting
ROUT Differential output resistance 80 100 120 Ω
TOSKEW Transmitter output pair (TXP and TXN) intra-pair skew – 2 – ps
CEXT Recommended external AC coupling capacitor(2) – 100 – nF
Notes:
1. The output swing and preemphasis levels are programmable using the attributes discussed in UG371:Virtex-6 FPGA GTH Transceivers User
Guide and can result in values lower than reported in this table.
Table 31 summarizes the DC specifications of the clock input of the GTH transceiver. Consult UG371:Virtex-6 FPGA GTH
Transceivers User Guide for further details.
Table 31: GTH Transceiver Clock DC Input Level Specification

≤ 600 MHz 500 – 1600 mV
VIDIFF Differential peak-to-peak input voltage
> 600 MHz 600 – 1600 mV
CEXT Required external AC coupling capacitor – 100 – nF

GTH Transceiver Switching Characteristics

Consult UG371:Virtex-6 FPGA GTH Transceivers User Guide for further information.
Table 32: GTH Transceiver Maximum Data Rate and PLL Frequency Range
Speed Grade
-3 -2 -1
PLL Output Divider = 1 11.182 11.182 10.32 Gb/s
FGTHMAX Maximum GTH transceiver data rate
FGTHMIN Minimum GTH transceiver data rate(1)
FGPLLMAX Maximum GTH PLL frequency 5.591 5.591 5.16 GHz
FGPLLMIN Minimum GTH PLL frequency 4.96 4.96 4.96 GHz
Notes:
1. Lower data rates can be achieved using FPGA logic based oversampling designs.
Table 33: GTH Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Speed Grade
-3 -2 -1
FGTHDRPCLK GTHDRPCLK maximum frequency 70 70 60 MHz
Table 34: GTH Transceiver Reference Clock Switching Characteristics

All Speed Grades
Min Typ Max
-1 speed grade 150 – 645 MHz
FGCLK Reference clock frequency range
-2 and -3 speed grades 150 – 700 MHz
TRCLK Reference clock rise time 20% – 80% – 200 – ps
TFCLK Reference clock fall time 80% – 20% – 200 – ps
TDCREF Reference clock duty cycle CLK 45 50 55 %
Clock recovery frequency acquisition Initial PLL lock – – 2 ms
TLOCK
time
Lock to data after PLL has locked – – 20 µs
TPHASE Clock recovery phase acquisition time
to the reference clock
TRCLK
80%
20%
TFCLK
ds152_05_042109
Figure 5: Reference Clock Timing Parameters

Table 35: GTH Transceiver User Clock Switching Characteristics (1)

Speed Grade
-3 -2 -1
FTXOUT TXUSERCLKOUT maximum frequency 350 350 323 MHz
FRXOUT RXUSERCLKOUT maximum frequency 350 350 323 MHz
16-bit data path 350 350 323 MHz
FTXIN TXUSERCLKIN maximum frequency 40-bit data path 280 280 258 MHz
64B/66B-bit data path 170 170 157 MHz
FRXIN RXUSERCLKIN maximum frequency 40-bit data path 280 280 258 MHz
64B/66B-bit data path 170 170 157 MHz
Notes:
1. Clocking must be implemented as described in UG371:Virtex-6 FPGA GTH Transceivers User Guide.
Table 36: GTH Transceiver Transmitter Switching Characteristics

Symbol Description Condition Min Typ Max Units
TRTX TX Rise time 20%–80% – 50(3) – ps
TFTX TX Fall time 80%–20% – 50(3) – ps
TLLSKEW TX lane-to-lane skew within one GTH Quad – – 300 ps
Transmitter Output Jitter(1)(2)
TJ11.18 Total Jitter 11.181 Gb/s – – 0.280 UI
DJ11.18 Deterministic Jitter – – 0.170 UI
Notes:
1. These values are NOT intended for protocol specific compliance determinations.
2. All jitter values are based on a bit-error ratio of 1e-12.
3. Rise and fall times are specified at the transmitter package balls.

Table 37: GTH Transceiver Receiver Switching Characteristics

RXRL Run length (CID) 8000 – – UI
RXPPMTOL Data/REFCLK PPM offset tolerance –200 – 200 ppm
SJ Jitter Tolerance(1)(2)(3)(4)
JT_SJ11.18 Sinusoidal Jitter 11.18 Gb/s 0.3 – – UI
Notes:
1. These values are NOT intended for protocol specific compliance determinations.
2. All jitter values are based on a bit error ratio of 1e–12.
3. The frequency of the injected sinusoidal jitter is 80 MHz.
4. High-frequency jitter tolerance including 6 db of channel loss at a high frequency of the data rate divided by two.
Ethernet MAC Switching Characteristics

Consult UG368:Virtex-6 FPGA Embedded Tri-mode Ethernet MAC User Guide for further information.
Table 38: Maximum Ethernet MAC Performance

Speed Grade
-3 -2 -1 -1L
FTEMACCLIENT Client interface maximum 10 Mb/s – 8-bit width 2.5(1) 2.5(1) 2.5(1) 2.5(1) MHz
frequency
100 Mb/s – 8-bit width 25(2) 25(2) 25(2) 25(2) MHz
1000 Mb/s – 8-bit width 125 125 125 125 MHz
1000 Mb/s – 16-bit width 62.5 62.5 62.5 62.5 MHz
2000 Mb/s – 16-bit width 125 125 125 N/A MHz
2500 Mb/s – 16-bit width 156.25 156.25 156.25 N/A MHz
FTEMACPHY Physical interface maximum 10 Mb/s – 4-bit width 2.5 2.5 2.5 2.5 MHz
frequency
100 Mb/s – 4-bit width 25 25 25 25 MHz
1000 Mb/s – 8-bit width 125 125 125 125 MHz
2000 Mb/s – 8-bit width 250 250 250 N/A MHz
2500 Mb/s – 8-bit width 312.5 312.5 312.5 N/A MHz
Notes:
1. When not using clock enable, the FMAX is lowered to 1.25 MHz.
2. When not using clock enable, the FMAX is lowered to 12.5 MHz.

Integrated Interface Block for PCI Express Designs Switching Characteristics

More information and documentation on solutions for PCI Express designs can be found at:
http://www.xilinx.com/technology/protocols/pciexpress.htm
Table 39: Maximum Performance for PCI Express Designs

Speed Grade
-3 -2 -1 -1L
FPIPECLK Pipe clock maximum frequency 250 250 250 250 MHz
FUSERCLK User clock maximum frequency 500 500 250 250 MHz
FDRPCLK DRP clock maximum frequency 250 250 250 250 MHz
System Monitor Analog-to-Digital Converter Specification

Table 40: Analog-to-Digital Specifications
Parameter Symbol Comments/Conditions Min Typ Max Units
AVDD = 2.5V ± 5%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 5.2 MHz, Tj = –55°C to 125°C M-Grade, Typical values at Tj=+35°C
DC Accuracy: All external input channels. Both unipolar and bipolar modes.
Resolution 10 – – Bits
Integral Nonlinearity INL – – ±1 LSBs
Differential Nonlinearity DNL No missing codes (TMIN to TMAX) – – ±0.9 LSBs
Guaranteed Monotonic
Unipolar Offset Error (1) Uncalibrated – ±2 ±30 LSBs
Bipolar Offset Error (1) Uncalibrated measured in bipolar mode – ±2 ±30 LSBs
Gain Error Uncalibrated - External Reference – ±0.2 ±2 %
Uncalibrated - Internal Reference – ±2 – %
Bipolar Gain Error (1) Uncalibrated - External Reference – ±0.2 ±2 %
Uncalibrated - Internal Reference – ±2 – %
Total Unadjusted Error TUE Deviation from ideal transfer function. – ±10 – LSBs
(Uncalibrated) External 1.25V reference
Deviation from ideal transfer function. – ±20 – LSBs
Internal reference
Total Unadjusted Error TUE Deviation from ideal transfer function. – ±1 ±2 LSBs
(Calibrated) External 1.25V reference
Calibrated Gain Temperature Variation of FS code with temperature – ±0.01 – LSB/°C
Coefficient
DC Common-Mode Reject CMRRDC VN = VCM = 0.5V ± 0.5V, – 70 – dB
VP – VN = 100mV
Conversion Rate(2)
Conversion Time - Continuous tCONV Number of CLK cycles 26 – 32
Conversion Time - Event tCONV Number of CLK cycles – – 21
T/H Acquisition Time tACQ Number of CLK cycles 4 – –
DRP Clock Frequency DCLK DRP clock frequency 8 – 80 MHz
ADC Clock Frequency ADCCLK Derived from DCLK 1 – 5.2 MHz
CLK Duty cycle 40 – 60 %

Table 40: Analog-to-Digital Specifications (Cont’d)

Parameter Symbol Comments/Conditions Min Typ Max Units
Analog Inputs(3)
Dedicated Analog Inputs Unipolar Operation 0 – 1 Volts
Input Voltage Range
Bipolar Operation –0.5 – +0.5
VP - VN
Unipolar Common Mode Range (FS input) 0 – +0.5
Bipolar Common Mode Range (FS input) +0.5 – +0.6
Bandwidth – 20 – MHz
Auxiliary Analog Inputs Unipolar Operation 0 – 1 Volts
Input Voltage Range
Bipolar Operation –0.5 – +0.5
VAUXP[0] /VAUXN[0] to VAUXP[15]
/VAUXN[15] Unipolar Common Mode Range (FS input) 0 – +0.5
Tj = –55°C to 125°C Bipolar Common Mode Range (FS input) +0.5 – +0.6
Bandwidth – 10 – kHz
Input Leakage Current A/D not converting, ADCCLK stopped – ±1.0 – µA
Input Capacitance – 10 – pF
On-chip Supply Monitor Error VCCINT and VCCAUX with calibration enabled. – – ±1.0 % Reading
External 1.25V reference Tj = –55°C to 125°C.
VCCINT and VCCAUX with calibration enabled. – ±2 – % Reading
Internal reference Tj = –40°C to 100°C.(4)
On-chip Temperature Monitor Tj = –55°C to +125°C with calibration enabled. – – ±4 °C
Error External 1.25V reference.
Tj = –40°C to +100°C with calibration enabled. – ±5 – °C
Internal reference.(4)
External Reference Inputs(5)
Positive Reference Input VREFP Measured Relative to VREFN 1.20 1.25 1.30 Volts
Voltage Range
Negative Reference Input VREFN Measured Relative to AGND –50 0 100 mV
Voltage Range
Input current IREF ADCCLK = 5.2 MHz – – 100 µA
Power Requirements
Analog Power Supply AVDD Measured Relative to AVSS 2.375 2.5 2.625 Volts
Analog Supply Current AIDD ADCCLK = 5.2 MHz – – 12 mA
Notes:
1. Offset errors are removed by enabling the System Monitor automatic gain calibration feature.
2. See "System Monitor Timing" in UG370:Virtex-6 FPGA System Monitor User Guide
3. See "Analog Inputs" in UG370:Virtex-6 FPGA System Monitor User Guide for a detailed description.
4. These internal references are not specified over the junction temperature operating range for military (M) temperature devices.
5. Any variation in the reference voltage from the nominal VREFP = 1.25V and VREFN = 0V will result in a deviation from the ideal transfer
function.This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external
ratiometric type applications allowing reference to vary by ±4% is permitted.

Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in
Virtex-6 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are
subject to the same guidelines as the Switching Characteristics, page 26.
Table 41: Interface Performances

Speed Grade
Description
-3 -2 -1 -1L
Networking Applications
SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8) 710 Mb/s 710 Mb/s 650 Mb/s 585 Mb/s
DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 10) 1.4 Gb/s 1.3 Gb/s 1.25 Gb/s 1.1 Gb/s
SDR LVDS receiver (SFI-4.1)(1) 710 Mb/s 710 Mb/s 650 Mb/s 585 Mb/s
DDR LVDS receiver (SPI-4.2)(1) 1.4 Gb/s 1.3 Gb/s 1.1 Gb/s 0.9 Gb/s
Maximum Physical Interface (PHY) Rate for Memory Interfaces(2)(3)(4)
DDR2 800 Mb/s 800 Mb/s 800 Mb/s 606 Mb/s
DDR3 1066 Mb/s 1066 Mb/s 800 Mb/s 800 Mb/s
QDR II + SRAM 400 MHz 350 MHz 300 MHz –
RLDRAM II 500 MHz 400 MHz 350 MHz –
Notes:
1. LVDS receivers are typically bounded with certain applications where specific DPA algorithms dominate deterministic performance.
2. Verified on Xilinx memory characterization platforms designed according to the guidelines in UG:Virtex-6 FPGA Memory Interface Solutions
User Guide.
3. Consult DS186:Virtex-6 FPGA Memory Interface Solutions Data Sheet for performance and feature information on memory interface cores
(controller plus PHY).
4. Memory Interface data rates have not been tested over the junction temperature operating range for military (M) temperature devices.
Customers are responsible for specifying and testing their specific M temperature grade memory implementation.

Switching Characteristics
All values represented in this data sheet are based on these Since individual family members are produced at different
speed specifications: v1.17 for -3, -2, and -1; and v1.10 for times, the migration from one category to another depends
-1L. Switching characteristics are specified on a per-speed- completely on the status of the fabrication process for each
grade basis and can be designated as Advance, device.
Preliminary, or Production. Each designation is defined as
Table 42 correlates the current status of each Virtex-6
follows:
device on a per speed grade basis.
Advance
Table 42: Virtex-6 Device Speed Grade Designations
These specifications are based on simulations only and are
Speed Grade Designations
typically available soon after device design specifications Device
are frozen. Although speed grades with this designation are Advance Preliminary Production
considered relatively stable and conservative, some under- XC6VLX75T -3, -2, -1, -1L
reporting might still occur.
XC6VLX130T -3, -2, -1, -1L
Preliminary
XC6VLX195T -3, -2, -1, -1L
These specifications are based on complete ES XC6VLX240T -3, -2, -1, -1L
(engineering sample) silicon characterization. Devices and
XC6VLX365T -3, -2, -1, -1L
speed grades with this designation are intended to give a
better indication of the expected performance of production XC6VLX550T -2, -1, -1L
silicon. The probability of under-reporting delays is greatly XC6VLX760 -2, -1, -1L
reduced as compared to Advance data.
XC6VSX315T -3, -2, -1, -1L
Production
XC6VSX475T -2, -1, -1L
These specifications are released once enough production XC6VHX250T -3, -2, -1
silicon of a particular device family member has been
XC6VHX255T -3, -2, -1
characterized to provide full correlation between
specifications and devices over numerous production lots. XC6VHX380T -3, -2, -1
There is no under-reporting of delays, and customers XC6VHX565T -2, -1
receive formal notification of any subsequent changes.
XQ6VLX130T -2, -1, -1L
Typically, the slowest speed grades transition to Production
before faster speed grades. XQ6VLX240T -2, -1, -1L
All specifications are always representative of worst-case XQ6VLX550T -1, -1L

supply voltage and junction temperature conditions. XQ6VSX315T -2, -1, -1L
XQ6VSX475T -1, -1L
Testing of Switching Characteristics

All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed
below are representative values.
For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and
back-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex-6 devices.

Production Silicon and ISE Software Status

In some cases, a particular family member (and speed grade) is released to production before a speed specification is
released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent
speed specification releases.
Table 43 lists the production released Virtex-6 family member, speed grade, and the minimum corresponding supported
speed specification version and ISE software revisions. The ISE® software and speed specifications listed are the minimum
releases required for production. All subsequent releases of software and speed specifications are valid.
Table 43: Virtex-6 Device Production Software and Speed Specification Release
Speed Grade Designations
Device
-3 -2 -1 -1L
XC6VLX75T ISE 12.2 v1.08 ISE 12.3 v1.07 Patch
XC6VLX130T ISE 12.1 v1.06 ISE 11.5 v1.05(2) ISE 11.5 v1.05(2) ISE 12.2 v1.05
XC6VLX195T ISE 12.1 v1.06 ISE 12.1 v1.06 ISE 12.1 v1.06 ISE 12.2 v1.04
XC6VLX240T ISE 12.1 v1.06 ISE 11.4.1 v1.04(2) ISE 11.4.1 v1.04(2) ISE 12.2 v1.04
XC6VLX365T ISE 12.2 v1.08 ISE 12.2 v1.04
XC6VLX550T N/A ISE 12.2 v1.07 ISE 12.2 v1.04
XC6VLX760 N/A ISE 12.2 v1.08 ISE 12.3 v1.07 Patch
XC6VSX315T ISE 12.2 v1.08 ISE 12.1 v1.06 ISE 12.3 v1.07 Patch
XC6VSX475T N/A ISE 12.2 v1.08 ISE 12.3 v1.07 Patch
XC6VHX250T ISE 12.4 v1.10 N/A
XC6VHX255T ISE 13.1 v1.14 using the ISE 13.1 software update N/A
XC6VHX380T ISE 12.4 v1.10 N/A
XC6VHX565T N/A ISE 13.1 v1.14 using the ISE 13.1 software update N/A
XQ6VLX130T N/A ISE 13.3 v1.17 Patch ISE 13.3 v1.10
XQ6VLX240T N/A ISE 13.3 v1.17 Patch ISE 13.3 v1.10
XQ6VLX550T N/A N/A ISE 13.3 v1.17 Patch ISE 13.3 v1.10
XQ6VSX315T N/A ISE 13.3 v1.17 Patch ISE 13.3 v1.10
XQ6VSX475T N/A N/A ISE 13.3 v1.17 Patch ISE 13.3 v1.10
Notes:
1. Blank entries indicate a device and/or speed grade in advance or preliminary status.
2. Designs utilizing the GTX transceivers must use the software version ISE 12.1 v1.06 or later.

IOB Pad Input/Output/3-State Switching Characteristics

Table 44 (for commercial (XC) Virtex-6 devices) and Table 45 (for the Defense-grade (XQ) Virtex-6 devices) summarizes the
values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state
delays.
TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending
on the capability of the SelectIO input buffer.
TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies
depending on the capability of the SelectIO output buffer.
TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO capability of the output buffer.
Table 46 summarizes the value of TIOTPHZ. TIOTPHZ is described as the delay from the T pin to the IOB pad through the
output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state).
Table 44: IOB Switching Characteristics for the Commercial (XC) Virtex-6 Devices
TIOPI TIOOP TIOTP
I/O Standard Speed Grade Speed Grade Speed Grade Units
-3 -2 -1 -1L -3 -2 -1 -1L -3 -2 -1 -1L
LVDS_25 0.85 0.94 1.09 1.08 1.45 1.54 1.68 1.62 1.45 1.54 1.68 1.62 ns
LVDSEXT_25 0.85 0.94 1.09 1.08 1.53 1.65 1.84 1.73 1.53 1.65 1.84 1.73 ns
HT_25 0.85 0.94 1.09 1.08 1.51 1.62 1.78 1.69 1.51 1.62 1.78 1.69 ns
BLVDS_25 0.85 0.94 1.09 1.08 1.39 1.50 1.67 1.65 1.39 1.50 1.67 1.65 ns
RSDS_25 (point to point) 0.85 0.94 1.09 1.08 1.45 1.54 1.68 1.62 1.45 1.54 1.68 1.62 ns
HSTL_I 0.81 0.91 1.06 1.06 1.45 1.56 1.73 1.71 1.45 1.56 1.73 1.71 ns
HSTL_II 0.81 0.91 1.06 1.06 1.44 1.56 1.74 1.72 1.44 1.56 1.74 1.72 ns
HSTL_III 0.81 0.91 1.06 1.06 1.42 1.54 1.71 1.69 1.42 1.54 1.71 1.69 ns
HSTL_I_18 0.81 0.91 1.06 1.06 1.47 1.58 1.75 1.72 1.47 1.58 1.75 1.72 ns
HSTL_II_18 0.81 0.91 1.06 1.06 1.50 1.62 1.81 1.78 1.50 1.62 1.81 1.78 ns
HSTL_III_18 0.81 0.91 1.06 1.06 1.42 1.54 1.71 1.69 1.42 1.54 1.71 1.69 ns
SSTL2_I 0.81 0.91 1.06 1.06 1.49 1.60 1.77 1.74 1.49 1.60 1.77 1.74 ns
SSTL2_II 0.81 0.91 1.06 1.06 1.42 1.54 1.72 1.71 1.42 1.54 1.72 1.71 ns
SSTL15 0.81 0.91 1.06 1.06 1.42 1.54 1.71 1.69 1.42 1.54 1.71 1.69 ns
LVCMOS25, Slow, 2 mA 0.51 0.57 0.66 0.70 5.09 5.46 6.01 5.63 5.09 5.46 6.01 5.63 ns
LVCMOS25, Slow, 4 mA 0.51 0.57 0.66 0.70 3.30 3.49 3.79 3.65 3.30 3.49 3.79 3.65 ns
LVCMOS25, Slow, 6 mA 0.51 0.57 0.66 0.70 2.62 2.81 3.08 2.95 2.62 2.81 3.08 2.95 ns
LVCMOS25, Slow, 8 mA 0.51 0.57 0.66 0.70 2.21 2.41 2.72 2.59 2.21 2.41 2.72 2.59 ns
LVCMOS25, Slow, 12 mA 0.51 0.57 0.66 0.70 1.80 1.95 2.17 2.10 1.80 1.95 2.17 2.10 ns
LVCMOS25, Slow, 16 mA 0.51 0.57 0.66 0.70 1.89 2.05 2.29 2.21 1.89 2.05 2.29 2.21 ns
LVCMOS25, Slow, 24 mA 0.51 0.57 0.66 0.70 1.68 1.82 2.02 1.98 1.68 1.82 2.02 1.98 ns
LVCMOS25, Fast, 2 mA 0.51 0.57 0.66 0.70 5.12 5.49 6.04 5.62 5.12 5.49 6.04 5.62 ns
LVCMOS25, Fast, 4 mA 0.51 0.57 0.66 0.70 3.28 3.50 3.82 3.65 3.28 3.50 3.82 3.65 ns
LVCMOS25, Fast, 6 mA 0.51 0.57 0.66 0.70 2.56 2.73 2.99 2.88 2.56 2.73 2.99 2.88 ns
LVCMOS25, Fast, 8 mA 0.51 0.57 0.66 0.70 2.11 2.33 2.65 2.53 2.11 2.33 2.65 2.53 ns
LVCMOS25, Fast, 12 mA 0.51 0.57 0.66 0.70 1.74 1.88 2.08 2.03 1.74 1.88 2.08 2.03 ns
LVCMOS25, Fast, 16 mA 0.51 0.57 0.66 0.70 1.77 1.92 2.13 2.08 1.77 1.92 2.13 2.08 ns

Table 44: IOB Switching Characteristics for the Commercial (XC) Virtex-6 Devices (Cont’d)
TIOPI TIOOP TIOTP
-3 -2 -1 -1L -3 -2 -1 -1L -3 -2 -1 -1L
LVCMOS25, Fast, 24 mA 0.51 0.57 0.66 0.70 1.66 1.79 1.99 1.96 1.66 1.79 1.99 1.96 ns
LVCMOS18, Slow, 2 mA 0.55 0.61 0.71 0.73 4.21 4.47 4.87 4.30 4.21 4.47 4.87 4.30 ns
LVCMOS18, Slow, 4 mA 0.55 0.61 0.71 0.73 2.79 2.96 3.21 2.94 2.79 2.96 3.21 2.94 ns
LVCMOS18, Slow, 6 mA 0.55 0.61 0.71 0.73 2.30 2.43 2.64 2.47 2.30 2.43 2.64 2.47 ns
LVCMOS18, Slow, 8 mA 0.55 0.61 0.71 0.73 2.01 2.11 2.27 2.24 2.01 2.11 2.27 2.24 ns
LVCMOS18, Slow, 12 mA 0.55 0.61 0.71 0.73 1.88 1.99 2.15 2.10 1.88 1.99 2.15 2.10 ns
LVCMOS18, Slow, 16 mA 0.55 0.61 0.71 0.73 1.84 1.95 2.11 2.04 1.84 1.95 2.11 2.04 ns
LVCMOS18, Fast, 2 mA 0.55 0.61 0.71 0.73 4.00 4.23 4.57 4.08 4.00 4.23 4.57 4.08 ns
LVCMOS18, Fast, 4 mA 0.55 0.61 0.71 0.73 2.62 2.76 2.97 2.74 2.62 2.76 2.97 2.74 ns
LVCMOS18, Fast, 6 mA 0.55 0.61 0.71 0.73 2.15 2.28 2.46 2.32 2.15 2.28 2.46 2.32 ns
LVCMOS18, Fast, 8 mA 0.55 0.61 0.71 0.73 1.90 1.99 2.13 2.14 1.90 1.99 2.13 2.14 ns
LVCMOS18, Fast, 12 mA 0.55 0.61 0.71 0.73 1.69 1.80 1.97 1.88 1.69 1.80 1.97 1.88 ns
LVCMOS18, Fast, 16 mA 0.55 0.61 0.71 0.73 1.63 1.74 1.91 1.88 1.63 1.74 1.91 1.88 ns
LVCMOS15, Slow, 2 mA 0.64 0.73 0.85 0.85 3.43 3.77 4.29 3.91 3.43 3.77 4.29 3.91 ns
LVCMOS15, Slow, 4 mA 0.64 0.73 0.85 0.85 2.58 2.79 3.10 2.93 2.58 2.79 3.10 2.93 ns
LVCMOS15, Slow, 6 mA 0.64 0.73 0.85 0.85 2.08 2.32 2.68 2.50 2.08 2.32 2.68 2.50 ns
LVCMOS15, Slow, 8 mA 0.64 0.73 0.85 0.85 1.81 1.98 2.23 2.24 1.81 1.98 2.23 2.24 ns
LVCMOS15, Slow, 12 mA 0.64 0.73 0.85 0.85 1.76 1.91 2.13 2.07 1.76 1.91 2.13 2.07 ns
LVCMOS15, Slow, 16 mA 0.64 0.73 0.85 0.85 1.69 1.83 2.04 1.98 1.69 1.83 2.04 1.98 ns
LVCMOS15, Fast, 2 mA 0.64 0.73 0.85 0.85 3.44 3.77 4.28 3.91 3.44 3.77 4.28 3.91 ns
LVCMOS15, Fast, 4 mA 0.64 0.73 0.85 0.85 2.37 2.53 2.78 2.66 2.37 2.53 2.78 2.66 ns
LVCMOS15, Fast, 6 mA 0.64 0.73 0.85 0.85 1.80 2.05 2.42 2.16 1.80 2.05 2.42 2.16 ns
LVCMOS15, Fast, 8 mA 0.64 0.73 0.85 0.85 1.76 1.90 2.11 2.04 1.76 1.90 2.11 2.04 ns
LVCMOS15, Fast, 12 mA 0.64 0.73 0.85 0.85 1.64 1.77 1.97 1.90 1.64 1.77 1.97 1.90 ns
LVCMOS15, Fast, 16 mA 0.64 0.73 0.85 0.85 1.62 1.76 1.96 1.92 1.62 1.76 1.96 1.92 ns
LVCMOS12, Slow, 2 mA 0.72 0.81 0.93 0.95 3.14 3.39 3.75 3.54 3.14 3.39 3.75 3.54 ns
LVCMOS12, Slow, 4 mA 0.72 0.81 0.93 0.95 2.43 2.63 2.93 2.79 2.43 2.63 2.93 2.79 ns
LVCMOS12, Slow, 6 mA 0.72 0.81 0.93 0.95 1.92 2.11 2.41 2.26 1.92 2.11 2.41 2.26 ns
LVCMOS12, Slow, 8 mA 0.72 0.81 0.93 0.95 1.87 2.02 2.25 2.17 1.87 2.02 2.25 2.17 ns
LVCMOS12, Fast, 2 mA 0.72 0.81 0.93 0.95 2.71 2.98 3.39 3.11 2.71 2.98 3.39 3.11 ns
LVCMOS12, Fast, 4 mA 0.72 0.81 0.93 0.95 1.93 2.16 2.51 2.31 1.93 2.16 2.51 2.31 ns
LVCMOS12, Fast, 6 mA 0.72 0.81 0.93 0.95 1.75 1.89 2.11 2.05 1.75 1.89 2.11 2.05 ns
LVCMOS12, Fast, 8 mA 0.72 0.81 0.93 0.95 1.69 1.82 2.02 1.98 1.69 1.82 2.02 1.98 ns
LVDCI_25 0.51 0.57 0.66 0.70 2.05 2.14 2.26 2.26 2.05 2.14 2.26 2.26 ns
LVDCI_18 0.55 0.61 0.71 0.73 2.07 2.23 2.47 2.38 2.07 2.23 2.47 2.38 ns
LVDCI_15 0.64 0.73 0.85 0.85 1.85 2.01 2.24 2.18 1.85 2.01 2.24 2.18 ns

TIOPI TIOOP TIOTP
-3 -2 -1 -1L -3 -2 -1 -1L -3 -2 -1 -1L
LVDCI_DV2_25 0.51 0.57 0.66 0.70 1.71 1.83 2.01 2.00 1.71 1.83 2.01 2.00 ns
LVDCI_DV2_18 0.55 0.61 0.71 0.73 1.69 1.81 2.00 1.98 1.69 1.81 2.00 1.98 ns
LVDCI_DV2_15 0.64 0.73 0.85 0.85 1.68 1.77 1.91 1.98 1.68 1.77 1.91 1.98 ns
LVPECL_25 0.85 0.94 1.09 1.08 1.38 1.49 1.65 1.64 1.38 1.49 1.65 1.64 ns
HSTL_I_12 0.81 0.91 1.06 1.06 1.48 1.60 1.78 1.74 1.48 1.60 1.78 1.74 ns
HSTL_I_DCI 0.81 0.91 1.06 1.06 1.40 1.50 1.66 1.64 1.40 1.50 1.66 1.64 ns
HSTL_II_DCI 0.81 0.91 1.06 1.06 1.37 1.49 1.68 1.66 1.37 1.49 1.68 1.66 ns
HSTL_II_T_DCI 0.81 0.91 1.06 1.06 1.40 1.50 1.66 1.64 1.40 1.50 1.66 1.64 ns
HSTL_III_DCI 0.81 0.91 1.06 1.06 1.34 1.45 1.62 1.61 1.34 1.45 1.62 1.61 ns
HSTL_I_DCI_18 0.81 0.91 1.06 1.06 1.42 1.53 1.68 1.66 1.42 1.53 1.68 1.66 ns
HSTL_II_DCI_18 0.81 0.91 1.06 1.06 1.36 1.46 1.62 1.59 1.36 1.46 1.62 1.59 ns
HSTL_II _T_DCI_18 0.81 0.91 1.06 1.06 1.42 1.53 1.68 1.66 1.42 1.53 1.68 1.66 ns
HSTL_III_DCI_18 0.81 0.91 1.06 1.06 1.43 1.54 1.69 1.67 1.43 1.54 1.69 1.67 ns
DIFF_HSTL_I_18 0.85 0.94 1.09 1.08 1.47 1.58 1.75 1.72 1.47 1.58 1.75 1.72 ns
DIFF_HSTL_I_DCI_18 0.85 0.94 1.09 1.08 1.42 1.53 1.68 1.66 1.42 1.53 1.68 1.66 ns
DIFF_HSTL_I 0.85 0.94 1.09 1.08 1.45 1.56 1.73 1.71 1.45 1.56 1.73 1.71 ns
DIFF_HSTL_I_DCI 0.85 0.94 1.09 1.08 1.40 1.50 1.66 1.64 1.40 1.50 1.66 1.64 ns
DIFF_HSTL_II_18 0.85 0.94 1.09 1.08 1.50 1.62 1.81 1.78 1.50 1.62 1.81 1.78 ns
DIFF_HSTL_II_DCI_18 0.85 0.94 1.09 1.08 1.36 1.46 1.62 1.59 1.36 1.46 1.62 1.59 ns
DIFF_HSTL_II _T_DCI_18 0.85 0.94 1.09 1.08 1.42 1.53 1.68 1.66 1.42 1.53 1.68 1.66 ns
DIFF_HSTL_II 0.85 0.94 1.09 1.08 1.44 1.56 1.74 1.72 1.44 1.56 1.74 1.72 ns
DIFF_HSTL_II_DCI 0.85 0.94 1.09 1.08 1.37 1.49 1.68 1.66 1.37 1.49 1.68 1.66 ns
SSTL2_I_DCI 0.81 0.91 1.06 1.06 1.42 1.53 1.70 1.68 1.42 1.53 1.70 1.68 ns
SSTL2_II_DCI 0.81 0.91 1.06 1.06 1.39 1.50 1.67 1.69 1.39 1.50 1.67 1.69 ns
SSTL2_II_T_DCI 0.81 0.91 1.06 1.06 1.42 1.53 1.70 1.68 1.42 1.53 1.70 1.68 ns
SSTL18_I 0.81 0.91 1.06 1.06 1.47 1.58 1.75 1.73 1.47 1.58 1.75 1.73 ns
SSTL18_II 0.81 0.91 1.06 1.06 1.39 1.50 1.67 1.66 1.39 1.50 1.67 1.66 ns
SSTL18_I_DCI 0.81 0.91 1.06 1.06 1.40 1.51 1.67 1.65 1.40 1.51 1.67 1.65 ns
SSTL18_II_DCI 0.81 0.91 1.06 1.06 1.36 1.47 1.63 1.62 1.36 1.47 1.63 1.62 ns
SSTL18_II_T_DCI 0.81 0.91 1.06 1.06 1.40 1.51 1.67 1.65 1.40 1.51 1.67 1.65 ns
SSTL15_T_DCI 0.81 0.91 1.06 1.06 1.41 1.52 1.68 1.66 1.41 1.52 1.68 1.66 ns
SSTL15_DCI 0.81 0.91 1.06 1.06 1.41 1.52 1.68 1.66 1.41 1.52 1.68 1.66 ns
DIFF_SSTL2_I 0.85 0.94 1.09 1.08 1.49 1.60 1.77 1.74 1.49 1.60 1.77 1.74 ns
DIFF_SSTL2_I_DCI 0.85 0.94 1.09 1.08 1.42 1.53 1.70 1.68 1.42 1.53 1.70 1.68 ns
DIFF_SSTL2_II 0.85 0.94 1.09 1.08 1.42 1.54 1.72 1.71 1.42 1.54 1.72 1.71 ns
DIFF_SSTL2_II_DCI 0.85 0.94 1.09 1.08 1.39 1.50 1.67 1.69 1.39 1.50 1.67 1.69 ns
DIFF_SSTL2_II_T_DCI 0.85 0.94 1.09 1.08 1.42 1.53 1.70 1.68 1.42 1.53 1.70 1.68 ns

TIOPI TIOOP TIOTP
-3 -2 -1 -1L -3 -2 -1 -1L -3 -2 -1 -1L
DIFF_SSTL18_I 0.85 0.94 1.09 1.08 1.47 1.58 1.75 1.73 1.47 1.58 1.75 1.73 ns
DIFF_SSTL18_I_DCI 0.85 0.94 1.09 1.08 1.40 1.51 1.67 1.65 1.40 1.51 1.67 1.65 ns
DIFF_SSTL18_II 0.85 0.94 1.09 1.08 1.39 1.50 1.67 1.66 1.39 1.50 1.67 1.66 ns
DIFF_SSTL18_II_DCI 0.85 0.94 1.09 1.08 1.36 1.47 1.63 1.62 1.36 1.47 1.63 1.62 ns
DIFF_SSTL18_II_T_DCI 0.85 0.94 1.09 1.08 1.40 1.51 1.67 1.65 1.40 1.51 1.67 1.65 ns
DIFF_SSTL15 0.81 0.91 1.06 1.06 1.42 1.54 1.71 1.69 1.42 1.54 1.71 1.69 ns
DIFF_SSTL15_DCI 0.81 0.91 1.06 1.06 1.41 1.52 1.68 1.66 1.41 1.52 1.68 1.66 ns
DIFF_SSTL15_T_DCI 0.81 0.91 1.06 1.06 1.41 1.52 1.68 1.66 1.41 1.52 1.68 1.66 ns
Table 45: IOB Switching Characteristics for the Defense-grade (XQ) Virtex-6 Devices
TIOPI TIOOP TIOTP
-2 -1 -1L -2 -1 -1L -2 -1 -1L
LVDS_25 0.94 1.09 1.08 1.54 2.16 1.62 1.54 2.16 1.62 ns
LVDSEXT_25 0.94 1.09 1.08 1.65 2.20 1.73 1.65 2.20 1.73 ns
HT_25 0.94 1.09 1.08 1.62 2.20 1.69 1.62 2.20 1.69 ns
BLVDS_25 0.94 1.09 1.08 1.50 3.18 1.65 1.50 3.18 1.65 ns
RSDS_25 (point to point) 0.94 1.09 1.08 1.54 2.22 1.62 1.54 2.22 1.62 ns
HSTL_I 0.91 1.06 1.06 1.56 2.44 1.71 1.56 2.44 1.71 ns
HSTL_II 0.91 1.06 1.06 1.56 2.21 1.72 1.56 2.21 1.72 ns
HSTL_III 0.91 1.06 1.06 1.54 2.50 1.69 1.54 2.50 1.69 ns
HSTL_I_18 0.91 1.06 1.06 1.58 2.43 1.72 1.58 2.43 1.72 ns
HSTL_II_18 0.91 1.06 1.06 1.62 2.30 1.78 1.62 2.30 1.78 ns
HSTL_III_18 0.91 1.06 1.06 1.54 2.49 1.69 1.54 2.49 1.69 ns
SSTL2_I 0.91 1.06 1.06 1.60 2.50 1.74 1.60 2.50 1.74 ns
SSTL2_II 0.91 1.06 1.06 1.54 2.49 1.71 1.54 2.49 1.71 ns
SSTL15 0.91 1.06 1.06 1.54 2.07 1.69 1.54 2.07 1.69 ns
LVCMOS25, Slow, 2 mA 0.57 0.66 0.70 5.46 6.01 5.63 5.46 6.01 5.63 ns
LVCMOS25, Slow, 4 mA 0.57 0.66 0.70 3.49 3.79 3.65 3.49 3.79 3.65 ns
LVCMOS25, Slow, 6 mA 0.57 0.66 0.70 2.81 3.08 2.95 2.81 3.08 2.95 ns
LVCMOS25, Slow, 8 mA 0.57 0.66 0.70 2.41 2.72 2.59 2.41 2.72 2.59 ns
LVCMOS25, Slow, 12 mA 0.57 0.66 0.70 1.95 2.23 2.10 1.95 2.23 2.10 ns
LVCMOS25, Slow, 16 mA 0.57 0.66 0.70 2.05 2.29 2.21 2.05 2.29 2.21 ns
LVCMOS25, Slow, 24 mA 0.57 0.66 0.70 1.82 2.24 1.98 1.82 2.24 1.98 ns
LVCMOS25, Fast, 2 mA 0.57 0.66 0.70 5.49 6.04 5.62 5.49 6.04 5.62 ns
LVCMOS25, Fast, 4 mA 0.57 0.66 0.70 3.50 3.82 3.65 3.50 3.82 3.65 ns
LVCMOS25, Fast, 6 mA 0.57 0.66 0.70 2.73 2.99 2.88 2.73 2.99 2.88 ns
LVCMOS25, Fast, 8 mA 0.57 0.66 0.70 2.33 2.65 2.53 2.33 2.65 2.53 ns
LVCMOS25, Fast, 12 mA 0.57 0.66 0.70 1.88 2.08 2.03 1.88 2.08 2.03 ns

Table 45: IOB Switching Characteristics for the Defense-grade (XQ) Virtex-6 Devices (Cont’d)
TIOPI TIOOP TIOTP
-2 -1 -1L -2 -1 -1L -2 -1 -1L
LVCMOS25, Fast, 16 mA 0.57 0.66 0.70 1.92 2.15 2.08 1.92 2.15 2.08 ns
LVCMOS25, Fast, 24 mA 0.57 0.66 0.70 1.79 2.15 1.96 1.79 2.15 1.96 ns
LVCMOS18, Slow, 2 mA 0.61 0.71 0.73 4.47 4.87 4.30 4.47 4.87 4.30 ns
LVCMOS18, Slow, 4 mA 0.61 0.71 0.73 2.96 3.21 2.94 2.96 3.21 2.94 ns
LVCMOS18, Slow, 6 mA 0.61 0.71 0.73 2.43 2.64 2.47 2.43 2.64 2.47 ns
LVCMOS18, Slow, 8 mA 0.61 0.71 0.73 2.11 2.41 2.24 2.11 2.41 2.24 ns
LVCMOS18, Slow, 12 mA 0.61 0.71 0.73 1.99 2.30 2.10 1.99 2.30 2.10 ns
LVCMOS18, Slow, 16 mA 0.61 0.71 0.73 1.95 2.30 2.04 1.95 2.30 2.04 ns
LVCMOS18, Fast, 2 mA 0.61 0.71 0.73 4.23 4.57 4.08 4.23 4.57 4.08 ns
LVCMOS18, Fast, 4 mA 0.61 0.71 0.73 2.76 2.97 2.74 2.76 2.97 2.74 ns
LVCMOS18, Fast, 6 mA 0.61 0.71 0.73 2.28 2.46 2.32 2.28 2.46 2.32 ns
LVCMOS18, Fast, 8 mA 0.61 0.71 0.73 1.99 2.34 2.14 1.99 2.34 2.14 ns
LVCMOS18, Fast, 12 mA 0.61 0.71 0.73 1.80 2.19 1.88 1.80 2.19 1.88 ns
LVCMOS18, Fast, 16 mA 0.61 0.71 0.73 1.74 2.18 1.88 1.74 2.18 1.88 ns
LVCMOS15, Slow, 2 mA 0.73 0.85 0.85 3.77 4.29 3.91 3.77 4.29 3.91 ns
LVCMOS15, Slow, 4 mA 0.73 0.85 0.85 2.79 3.10 2.93 2.79 3.10 2.93 ns
LVCMOS15, Slow, 6 mA 0.73 0.85 0.85 2.32 2.68 2.50 2.32 2.68 2.50 ns
LVCMOS15, Slow, 8 mA 0.73 0.85 0.85 1.98 2.29 2.24 1.98 2.29 2.24 ns
LVCMOS15, Slow, 12 mA 0.73 0.85 0.85 1.91 2.23 2.07 1.91 2.23 2.07 ns
LVCMOS15, Slow, 16 mA 0.73 0.85 0.85 1.83 2.23 1.98 1.83 2.23 1.98 ns
LVCMOS15, Fast, 2 mA 0.73 0.85 0.85 3.77 4.28 3.91 3.77 4.28 3.91 ns
LVCMOS15, Fast, 4 mA 0.73 0.85 0.85 2.53 2.78 2.66 2.53 2.78 2.66 ns
LVCMOS15, Fast, 6 mA 0.73 0.85 0.85 2.05 2.42 2.16 2.05 2.42 2.16 ns
LVCMOS15, Fast, 8 mA 0.73 0.85 0.85 1.90 2.20 2.04 1.90 2.20 2.04 ns
LVCMOS15, Fast, 12 mA 0.73 0.85 0.85 1.77 2.11 1.90 1.77 2.11 1.90 ns
LVCMOS15, Fast, 16 mA 0.73 0.85 0.85 1.76 2.11 1.92 1.76 2.11 1.92 ns
LVCMOS12, Slow, 2 mA 0.81 0.93 0.95 3.39 3.75 3.54 3.39 3.75 3.54 ns
LVCMOS12, Slow, 4 mA 0.81 0.93 0.95 2.63 2.93 2.79 2.63 2.93 2.79 ns
LVCMOS12, Slow, 6 mA 0.81 0.93 0.95 2.11 2.67 2.26 2.11 2.67 2.26 ns
LVCMOS12, Slow, 8 mA 0.81 0.93 0.95 2.02 2.25 2.17 2.02 2.25 2.17 ns
LVCMOS12, Fast, 2 mA 0.81 0.93 0.95 2.98 3.39 3.11 2.98 3.39 3.11 ns
LVCMOS12, Fast, 4 mA 0.81 0.93 0.95 2.16 2.70 2.31 2.16 2.70 2.31 ns
LVCMOS12, Fast, 6 mA 0.81 0.93 0.95 1.89 2.34 2.05 1.89 2.34 2.05 ns
LVCMOS12, Fast, 8 mA 0.81 0.93 0.95 1.82 2.10 1.98 1.82 2.10 1.98 ns
LVDCI_25 0.57 0.70 0.70 2.14 2.82 2.26 2.14 2.82 2.26 ns
LVDCI_18 0.61 0.71 0.73 2.23 2.78 2.38 2.23 2.78 2.38 ns
LVDCI_15 0.73 0.85 0.85 2.01 2.75 2.18 2.01 2.75 2.18 ns
LVDCI_DV2_25 0.57 0.70 0.70 1.83 2.37 2.00 1.83 2.37 2.00 ns

TIOPI TIOOP TIOTP
-2 -1 -1L -2 -1 -1L -2 -1 -1L
LVDCI_DV2_18 0.61 0.72 0.73 1.81 2.36 1.98 1.81 2.36 1.98 ns
LVDCI_DV2_15 0.73 0.85 0.85 1.77 2.30 1.98 1.77 2.30 1.98 ns
LVPECL_25 0.94 1.09 1.08 1.49 2.68 1.64 1.49 2.68 1.64 ns
HSTL_I_12 0.91 1.06 1.06 1.60 2.48 1.74 1.60 2.48 1.74 ns
HSTL_I_DCI 0.91 1.06 1.06 1.50 2.43 1.64 1.50 2.43 1.64 ns
HSTL_II_DCI 0.91 1.06 1.06 1.49 2.39 1.66 1.49 2.39 1.66 ns
HSTL_II_T_DCI 0.91 1.06 1.06 1.50 2.43 1.64 1.50 2.43 1.64 ns
HSTL_III_DCI 0.91 1.06 1.06 1.45 2.48 1.61 1.45 2.48 1.61 ns
HSTL_I_DCI_18 0.91 1.06 1.06 1.53 2.44 1.66 1.53 2.44 1.66 ns
HSTL_II_DCI_18 0.91 1.06 1.06 1.46 2.41 1.59 1.46 2.41 1.59 ns
HSTL_II _T_DCI_18 0.91 1.06 1.06 1.53 2.43 1.66 1.53 2.43 1.66 ns
HSTL_III_DCI_18 0.91 1.06 1.06 1.54 2.50 1.67 1.54 2.50 1.67 ns
DIFF_HSTL_I_18 0.94 1.09 1.08 1.58 2.30 1.72 1.58 2.30 1.72 ns
DIFF_HSTL_I_DCI_18 0.94 1.09 1.08 1.53 2.21 1.66 1.53 2.21 1.66 ns
DIFF_HSTL_I 0.94 1.09 1.08 1.56 2.28 1.71 1.56 2.28 1.71 ns
DIFF_HSTL_I_DCI 0.94 1.09 1.08 1.50 2.28 1.64 1.50 2.28 1.64 ns
DIFF_HSTL_II_18 0.94 1.09 1.08 1.62 2.33 1.78 1.62 2.33 1.78 ns
DIFF_HSTL_II_DCI_18 0.94 1.09 1.08 1.46 2.18 1.59 1.46 2.18 1.59 ns
DIFF_HSTL_II _T_DCI_18 0.94 1.09 1.08 1.53 2.22 1.66 1.53 2.22 1.66 ns
DIFF_HSTL_II 0.94 1.09 1.08 1.56 2.29 1.72 1.56 2.29 1.72 ns
DIFF_HSTL_II_DCI 0.94 1.09 1.08 1.49 2.26 1.66 1.49 2.26 1.66 ns
SSTL2_I_DCI 0.91 1.06 1.06 1.53 2.51 1.68 1.53 2.51 1.68 ns
SSTL2_II_DCI 0.91 1.06 1.06 1.50 2.50 1.69 1.50 2.50 1.69 ns
SSTL2_II_T_DCI 0.91 1.06 1.06 1.53 2.52 1.68 1.53 2.52 1.68 ns
SSTL18_I 0.91 1.06 1.06 1.58 2.48 1.73 1.58 2.48 1.73 ns
SSTL18_II 0.91 1.06 1.06 1.50 2.46 1.66 1.50 2.46 1.66 ns
SSTL18_I_DCI 0.91 1.06 1.06 1.51 2.49 1.65 1.51 2.49 1.65 ns
SSTL18_II_DCI 0.91 1.06 1.06 1.47 2.41 1.62 1.47 2.41 1.62 ns
SSTL18_II_T_DCI 0.91 1.06 1.06 1.51 2.49 1.65 1.51 2.49 1.65 ns
SSTL15_T_DCI 0.91 1.06 1.06 1.52 2.48 1.66 1.52 2.48 1.66 ns
SSTL15_DCI 0.91 1.06 1.06 1.52 2.48 1.66 1.52 2.48 1.66 ns
DIFF_SSTL2_I 0.94 1.09 1.08 1.60 2.34 1.74 1.60 2.34 1.74 ns
DIFF_SSTL2_I_DCI 0.94 1.09 1.08 1.53 2.25 1.68 1.53 2.25 1.68 ns
DIFF_SSTL2_II 0.94 1.09 1.08 1.54 2.29 1.71 1.54 2.29 1.71 ns
DIFF_SSTL2_II_DCI 0.94 1.09 1.08 1.50 2.23 1.69 1.50 2.23 1.69 ns
DIFF_SSTL2_II_T_DCI 0.94 1.09 1.08 1.53 2.26 1.68 1.53 2.26 1.68 ns
DIFF_SSTL18_I 0.94 1.09 1.08 1.58 2.22 1.73 1.58 2.22 1.73 ns
DIFF_SSTL18_I_DCI 0.94 1.09 1.08 1.51 2.30 1.65 1.51 2.30 1.65 ns

TIOPI TIOOP TIOTP
-2 -1 -1L -2 -1 -1L -2 -1 -1L
DIFF_SSTL18_II 0.94 1.09 1.08 1.50 2.27 1.66 1.50 2.27 1.66 ns
DIFF_SSTL18_II_DCI 0.94 1.09 1.08 1.47 2.20 1.62 1.47 2.20 1.62 ns
DIFF_SSTL18_II_T_DCI 0.94 1.09 1.08 1.51 2.30 1.65 1.51 2.30 1.65 ns
DIFF_SSTL15 0.91 1.06 1.06 1.54 2.25 1.69 1.54 2.25 1.69 ns
DIFF_SSTL15_DCI 0.91 1.06 1.06 1.52 2.25 1.66 1.52 2.25 1.66 ns
DIFF_SSTL15_T_DCI 0.91 1.06 1.06 1.52 2.25 1.66 1.52 2.25 1.66 ns
Table 46: IOB 3-state ON Output Switching Characteristics (TIOTPHZ)

Speed Grade
-3 -2 -1 -1L
TIOTPHZ T input to Pad high-impedance 0.86 0.92 0.99 0.99 ns

I/O Standard Adjustment Measurement Methodology

Input Delay Measurements
Table 47 shows the test setup parameters used for measuring input delay.
Table 47: Input Delay Measurement Methodology

VMEAS VREF
Description I/O Standard Attribute VL (1)(2) VH(1)(2)
(1)(4)(5) (1)(3)(5)
LVCMOS, 2.5V LVCMOS25 0 2.5 1.25 –

LVCMOS, 1.8V LVCMOS18 0 1.8 0.9 –
LVCMOS, 1.5V LVCMOS15 0 1.5 0.75 –
HSTL (High-Speed Transceiver Logic), HSTL_I, HSTL_II VREF – 0.5 VREF + 0.5 VREF 0.75
Class I & II
HSTL, Class III HSTL_III VREF – 0.5 VREF + 0.5 VREF 0.90
HSTL, Class I & II, 1.8V HSTL_I_18, HSTL_II_18 VREF – 0.5 VREF + 0.5 VREF 0.90
HSTL, Class III 1.8V HSTL_III_18 VREF – 0.5 VREF + 0.5 VREF 1.08
SSTL (Stub Terminated Transceiver Logic), SSTL3_I, SSTL3_II VREF – 1.00 VREF + 1.00 VREF 1.5
Class I & II, 3.3V
SSTL, Class I & II, 2.5V SSTL2_I, SSTL2_II VREF – 0.75 VREF + 0.75 VREF 1.25
SSTL, Class I & II, 1.8V SSTL18_I, SSTL18_II VREF – 0.5 VREF + 0.5 VREF 0.90
LVDS (Low-Voltage Differential Signaling), 2.5V LVDS_25 1.2 – 0.125 1.2 + 0.125 0(6) –
LVDSEXT (LVDS Extended Mode), 2.5V LVDSEXT_25 1.2 – 0.125 1.2 + 0.125 0(6) –
HT (HyperTransport), 2.5V LDT_25 0.6 – 0.125 0.6 + 0.125 0(6) –
Notes:
1. The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay
measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other
DCI standards are the same for the corresponding non-DCI standards.
2. Input waveform switches between VLand VH.
3. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF
values listed are typical.
4. Input voltage level from which measurement starts.
5. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 6.
6. The value given is the differential input voltage.

Output Delay Measurements X-Ref Target - Figure 7
Output delays are measured using a Tektronix P6245 FPGA Output

+
TDS500/600 probe (< 1 pF) across approximately 4" of FR4
microstrip trace. Standard termination was used for all
testing. The propagation delay of the 4" trace is CREF RREF VMEAS
characterized separately and subtracted from the final
measurement, and is therefore not included in the
generalized test setups shown in Figure 6 and Figure 7. –
ds152_07_042109
Figure 7: Differential Test Setup

VREF
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it.
RREF Parameters VREF, RREF, CREF, and VMEAS fully describe
FPGA Output
the test conditions for each I/O standard. The most accurate
prediction of propagation delay in any given application can
be obtained through IBIS simulation, using the following
VMEAS method:
(voltage level when taking
delay measurement)
1. Simulate the output driver of choice into the generalized
CREF test setup, using values from Table 48.
(probe capacitance)
2. Record the time to VMEAS .
ds152_06_042109 3. Simulate the output driver of choice into the actual PCB
Figure 6: Single Ended Test Setup trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
4. Record the time to VMEAS .
5. Compare the results of steps 2 and 4. The increase or
decrease in delay yields the actual propagation delay of
the PCB trace.
Table 48: Output Delay Measurement Methodology
I/O Standard RREF CREF(1) VMEAS VREF
Description
Attribute (Ω) (pF) (V) (V)
LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0
HSTL (High-Speed Transceiver Logic), Class I HSTL_I 50 0 VREF 0.75
HSTL, Class II HSTL_II 25 0 VREF 0.75
HSTL, Class III HSTL_III 50 0 0.9 1.5
HSTL, Class I, 1.8V HSTL_I_18 50 0 VREF 0.9
HSTL, Class II, 1.8V HSTL_II_18 25 0 VREF 0.9
HSTL, Class III, 1.8V HSTL_III_18 50 0 1.1 1.8
SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL18_I 50 0 VREF 0.9
SSTL, Class II, 1.8V SSTL18_II 25 0 VREF 0.9
SSTL, Class I, 2.5V SSTL2_I 50 0 VREF 1.25
SSTL, Class II, 2.5V SSTL2_II 25 0 VREF 1.25
LVDS (Low-Voltage Differential Signaling), 2.5V LVDS_25 100 0 0(2) 1.2
LVDSEXT (LVDS Extended Mode), 2.5V LVDS_25 100 0 0(2) 1.2
BLVDS (Bus LVDS), 2.5V BLVDS_25 100 0 0(2) 0

Table 48: Output Delay Measurement Methodology (Cont’d)

I/O Standard RREF CREF(1) VMEAS VREF
Description
Attribute (Ω) (pF) (V) (V)
HT (HyperTransport), 2.5V LDT_25 100 0 0(2) 0.6
LVPECL (Low-Voltage Positive Emitter-Coupled Logic), LVPECL_25 100 0 0(2) 0
2.5V
LVDCI/HSLVDCI, 2.5V LVDCI_25, HSLVDCI_25 1M 0 1.25 0
HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI 50 0 VREF 0.75
HSTL, Class III, with DCI HSTL_III_DCI 50 0 0.9 1.5
HSTL, Class I & II, 1.8V, with DCI HSTL_I_DCI_18, HSTL_II_DCI_18 50 0 VREF 0.9
HSTL, Class III, 1.8V, with DCI HSTL_III_DCI_18 50 0 1.1 1.8
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI 50 0 VREF 0.9
SSTL, Class I & II, 2.5V, with DCI SSTL2_I_DCI, SSTL2_II_DCI 50 0 VREF 1.25
Notes:
1. CREF is the capacitance of the probe, nominally 0 pF.
2. The value given is the differential output voltage.
Input/Output Logic Switching Characteristics

Table 49: ILOGIC Switching Characteristics
Speed Grade
-3 -2 -1 -1L
Setup/Hold
TICE1CK/TICKCE1 CE1 pin Setup/Hold with respect to CLK 0.21/ 0.25/ 0.27/ 0.31/ ns
0.03 0.04 0.04 0.05
TISRCK/TICKSR SR pin Setup/Hold with respect to CLK 0.66/ 0.78/ 0.96/ 1.09/ ns
–0.08 –0.08 –0.08 –0.11
TIDOCK/TIOCKD D pin Setup/Hold with respect to CLK without Delay 0.07/ 0.08/ 0.10/ 0.11/ ns
0.41 0.46 0.54 0.64
TIDOCKD/TIOCKDD DDLY pin Setup/Hold with respect to CLK (using IODELAY) 0.10/ 0.12/ 0.14/ 0.16/ ns
0.32 0.36 0.42 0.50
Combinatorial
TIDI D pin to O pin propagation delay, no Delay 0.15 0.17 0.20 0.23 ns
TIDID DDLY pin to O pin propagation delay (using IODELAY) 0.19 0.22 0.25 0.28 ns
Sequential Delays
TIDLO D pin to Q1 pin using flip-flop as a latch without Delay 0.48 0.54 0.64 0.73 ns
TIDLOD DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY) 0.52 0.58 0.68 0.78 ns
TICKQ CLK to Q outputs 0.54 0.61 0.70 0.93 ns
TRQ_ILOGIC SR pin to OQ/TQ out 0.85 0.97 1.15 1.32 ns
TGSRQ_ILOGIC Global Set/Reset to Q outputs 7.60 7.60 10.51 10.51 ns
Set/Reset
TRPW_ILOGIC Minimum Pulse Width, SR inputs 0.78 0.95 1.20 1.30 ns, Min

Table 50: OLOGIC Switching Characteristics

Speed Grade
-3 -2 -1 (XC) -1 (XQ) -1L
Setup/Hold
TODCK/TOCKD D1/D2 pins Setup/Hold with respect to CLK 0.45/ 0.50/ 0.54/ 0.54/ 0.69/ ns
–0.08 –0.08 –0.08 –0.08 –0.11
TOOCECK/TOCKOCE OCE pin Setup/Hold with respect to CLK 0.17/ 0.20/ 0.22/ 0.27/ 0.27/ ns
–0.03 –0.03 –0.03 –0.05 –0.04
TOSRCK/TOCKSR SR pin Setup/Hold with respect to CLK 0.59/ 0.62/ 0.54/ 0.54/ 0.79/ ns
–0.24 –0.24 –0.08 –0.08 –0.35
TOTCK/TOCKT T1/T2 pins Setup/Hold with respect to CLK 0.44/ 0.51/ 0.56/ 0.60/ 0.68/ ns
–0.07 –0.07 –0.07 –0.10 –0.13
TOTCECK/TOCKTCE TCE pin Setup/Hold with respect to CLK 0.15/ 0.19/ 0.21/ 0.27/ 0.29/ ns
–0.04 –0.04 –0.04 –0.05 –0.05
Combinatorial
TDOQ D1 to OQ out or T1 to TQ out 0.78 0.87 1.01 1.01 1.15 ns
Sequential Delays
TOCKQ CLK to OQ/TQ out 0.54 0.61 0.71 0.71 0.80 ns
TRQ SR pin to OQ/TQ out 0.80 0.90 1.05 1.05 1.19 ns
TGSRQ Global Set/Reset to Q outputs 7.60 7.60 10.51 10.51 10.51 ns
Set/Reset
TRPW Minimum Pulse Width, SR inputs 0.78 0.95 1.20 1.20 1.30 ns, Min

Input Serializer/Deserializer Switching Characteristics

Table 51: ISERDES Switching Characteristics
Speed Grade
-3 -2 -1 (XC) -1 (XQ) -1L
Setup/Hold for Control Lines
TISCCK_BITSLIP/ TISCKC_BITSLIP BITSLIP pin Setup/Hold with respect to 0.07/ 0.08/ 0.09/ 0.09/ 0.14/ ns
CLKDIV 0.15 0.16 0.17 0.17 0.17
TISCCK_CE / TISCKC_CE(2) CE pin Setup/Hold with respect to CLK 0.20/ 0.25/ 0.27/ 0.27/ 0.31/ ns
(for CE1) 0.03 0.04 0.04 0.04 0.05
TISCCK_CE2 / TISCKC_CE2(2) CE pin Setup/Hold with respect to CLKDIV 0.01/ 0.01 0.01/ 0.01/ –0.05/ ns
(for CE2) 0.27 0.29 0.31 0.31 0.35
Setup/Hold for Data Lines
TISDCK_D /TISCKD_D D pin Setup/Hold with respect to CLK 0.07/ 0.08/ 0.09/ 0.09/ 0.11/ ns
0.08 0.09 0.11 0.11 0.19
TISDCK_DDLY /TISCKD_DDLY DDLY pin Setup/Hold with respect to CLK 0.10/ 0.12/ 0.14/ 0.14/ 0.16/ ns
(using IODELAY)(1) 0.05 0.06 0.07 0.07 0.15
TISDCK_D_DDR /TISCKD_D_DDR D pin Setup/Hold with respect to CLK at 0.07/ 0.08/ 0.09/ 0.09/ 0.11/ ns
DDR mode 0.08 0.09 0.11 0.11 0.19
TISDCK_DDLY_DDR D pin Setup/Hold with respect to CLK at 0.10/ 0.12/ 0.14/ 0.14/ 0.16/ ns
TISCKD_DDLY_DDR DDR mode (using IODELAY)(1) 0.05 0.06 0.07 0.07 0.15
Sequential Delays
TISCKO_Q CLKDIV to out at Q pin 0.57 0.66 0.75 0.80 0.88 ns
Propagation Delays
TISDO_DO D input to DO output pin 0.19 0.22 0.25 0.25 0.28 ns
Notes:
1. Recorded at 0 tap value.
2. TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in TRACE report.

Output Serializer/Deserializer Switching Characteristics

Table 52: OSERDES Switching Characteristics
Speed Grade
-3 -2 -1 (XC) -1 (XQ) -1L
Setup/Hold
TOSDCK_D/TOSCKD_D D input Setup/Hold with respect to CLKDIV 0.23/ 0.28/ 0.31/ 0.35/ 0.36/ ns
–0.10 –0.10 –0.10 –0.10 –0.15
TOSDCK_T/TOSCKD_T(1) T input Setup/Hold with respect to CLK 0.44/ 0.51/ 0.56/ 0.60/ 0.68/ ns
–0.10 –0.09 –0.08 –0.08 –0.15
TOSDCK_T2/TOSCKD_T2(1) T input Setup/Hold with respect to CLKDIV 0.25/ 0.27/ 0.31/ 0.31/ 0.47/ ns
–0.10 –0.09 –0.08 –0.08 –0.15
TOSCCK_OCE/TOSCKC_OCE OCE input Setup/Hold with respect to CLK 0.17/ 0.20/ 0.22/ 0.27/ 0.27/ ns
–0.03 –0.03 –0.03 –0.03 –0.04
TOSCCK_S SR (Reset) input Setup with respect to 0.07 0.07 0.07 0.07 0.08 ns
CLKDIV
TOSCCK_TCE/TOSCKC_TCE TCE input Setup/Hold with respect to CLK 0.15/ 0.19/ 0.21/ 0.27/ 0.29/ ns
–0.04 –0.04 –0.04 –0.04 –0.05
Sequential Delays
TOSCKO_OQ Clock to out from CLK to OQ 0.63 0.71 0.82 0.82 0.93 ns
TOSCKO_TQ Clock to out from CLK to TQ 0.63 0.71 0.82 0.82 0.93 ns
Combinatorial
TOSDO_TTQ T input to TQ Out 0.76 0.84 0.97 0.97 1.11 ns
Notes:
1. TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in TRACE report.

Input/Output Delay Switching Characteristics

Table 53: Input/Output Delay Switching Characteristics
Speed Grade
-3 -2 -1 -1L
IDELAYCTRL
TDLYCCO_RDY Reset to Ready for IDELAYCTRL 3.00 3.00 3.00 3.25 µs
FIDELAYCTRL_REF REFCLK frequency = 200.0(1) 200 200 200 200 MHz
REFCLK frequency = 300.0(1) 300 300 – – MHz
IDELAYCTRL_REF_PRECISION REFCLK precision ±10 ±10 ±10 ±10 MHz
TIDELAYCTRL_RPW Minimum Reset pulse width 50.00 50.00 50.00 52.50 ns
IODELAY
TIDELAYRESOLUTION IODELAY Chain Delay Resolution 1/(32 x 2 x FREF) ps
Pattern dependent period jitter in delay 0 0 0 0 ps
chain for clock pattern.(2) per tap
Pattern dependent period jitter in delay ±5 ±5 ±5 ±5 ps
chain for random data pattern per tap
TIDELAYPAT_JIT
(PRBS 23).(3)
Pattern dependent period jitter in delay ±9 ±9 ±9 ±9 ps
chain for random data pattern per tap
(PRBS 23).(4)
TIODELAY_CLK_MAX Maximum frequency of CLK input to 500.00 420.00 300.00 300.00 MHz
IODELAY
TIODCCK_CE / TIODCKC_CE CE pin Setup/Hold with respect to CK 0.45/ 0.53/ 0.65/ 0.84/ ns
–0.09 –0.09 –0.09 –0.14
TIODCK_INC/ TIODCKC_INC INC pin Setup/Hold with respect to CK 0.23/ 0.27/ 0.31/ 0.27/ ns
–0.02 –0.01 0.00 –0.04
TIODCCK_RST/ TIODCKC_RST RST pin Setup/Hold with respect to CK 0.57/ 0.62/ 0.69/ 0.74/ ns
–0.08 –0.08 –0.08 –0.13
TIODDO_T TSCONTROL delay to MUXE/MUXF Note 5 Note 5 Note 5 Note 5 ps
switching and through IODELAY
TIODDO_IDATAIN Propagation delay through IODELAY Note 5 Note 5 Note 5 Note 5 ps
TIODDO_ODATAIN Propagation delay through IODELAY Note 5 Note 5 Note 5 Note 5 ps
Notes:
1. Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps.
2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE.
3. When HIGH_PERFORMANCE mode is set to TRUE
4. When HIGH_PERFORMANCE mode is set to FALSE.
5. Delay depends on IODELAY tap setting. See TRACE report for actual values.
CLB Switching Characteristics

Table 54: CLB Switching Characteristics
Speed Grade
-3 -2 -1 -1L
Combinatorial Delays
TILO An – Dn LUT address to A 0.06 0.07 0.07 0.09 ns, Max
An – Dn LUT address to AMUX/CMUX 0.18 0.20 0.22 0.25 ns, Max
An – Dn LUT address to BMUX_A 0.28 0.31 0.36 0.40 ns, Max

Table 54: CLB Switching Characteristics (Cont’d)

Speed Grade
-3 -2 -1 -1L
TITO An – Dn inputs to A – D Q outputs 0.59 0.67 0.79 0.85 ns, Max
TAXA AX inputs to AMUX output 0.31 0.35 0.42 0.44 ns, Max
TAXB AX inputs to BMUX output 0.35 0.39 0.47 0.50 ns, Max
TAXC AX inputs to CMUX output 0.39 0.44 0.52 0.56 ns, Max
TAXD AX inputs to DMUX output 0.42 0.47 0.55 0.60 ns, Max
TBXB BX inputs to BMUX output 0.30 0.34 0.39 0.44 ns, Max
TBXD BX inputs to DMUX output 0.38 0.43 0.50 0.55 ns, Max
TCXC CX inputs to CMUX output 0.26 0.29 0.34 0.37 ns, Max
TCXD CX inputs to DMUX output 0.30 0.34 0.40 0.44 ns, Max
TDXD DX inputs to DMUX output 0.30 0.33 0.38 0.43 ns, Max
TOPCYA An input to COUT output 0.32 0.36 0.41 0.47 ns, Max
TOPCYB Bn input to COUT output 0.32 0.36 0.41 0.47 ns, Max
TOPCYC Cn input to COUT output 0.27 0.30 0.34 0.40 ns, Max
TOPCYD Dn input to COUT output 0.25 0.28 0.32 0.37 ns, Max
TAXCY AX input to COUT output 0.25 0.28 0.33 0.36 ns, Max
TBXCY BX input to COUT output 0.22 0.24 0.28 0.31 ns, Max
TCXCY CX input to COUT output 0.15 0.17 0.20 0.22 ns, Max
TDXCY DX input to COUT output 0.14 0.16 0.19 0.21 ns, Max
TBYP CIN input to COUT output 0.06 0.07 0.08 0.09 ns, Max
TCINA CIN input to AMUX output 0.21 0.24 0.28 0.30 ns, Max
TCINB CIN input to BMUX output 0.23 0.25 0.29 0.31 ns, Max
TCINC CIN input to CMUX output 0.23 0.26 0.30 0.33 ns, Max
TCIND CIN input to DMUX output 0.25 0.29 0.33 0.36 ns, Max
Sequential Delays
TCKO Clock to AQ – DQ outputs 0.29 0.33 0.39 0.44 ns, Max
TSHCKO Clock to AMUX – DMUX outputs 0.36 0.40 0.47 0.53 ns, Max
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
TDICK/TCKDI A – D input to CLK on A – D Flip Flops 0.30/0.17 0.36/0.18 0.43/0.20 0.44/0.25 ns, Min
TCECK_CLB/ CE input to CLK on A – D Flip Flops 0.20/0.00 0.25/0.00 0.32/0.00 0.32/0.01 ns, Min
TCKCE_CLB
TSRCK/TCKSR SR input to CLK on A – D Flip Flops 0.39/–0.07 0.44/–0.07 0.52/–0.07 0.58/–0.08 ns, Min
TCINCK/TCKCIN CIN input to CLK on A – D Flip Flops 0.16/0.12 0.19/0.14 0.24/0.16 0.23/0.22 ns, Min
Set/Reset
TSRMIN SR input minimum pulse width 0.90 0.90 0.97 0.80 ns, Min
TRQ Delay from SR input to AQ – DQ flip-flops 0.52 0.58 0.68 0.77 ns, Max
TCEO Delay from CE input to AQ – DQ flip-flops 0.41 0.48 0.59 0.61 ns, Max
FTOG Toggle frequency (for export control) 1412.00 1286.40 1098.00 1098.00 MHz
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
2. These items are of interest for Carry Chain applications.

CLB Distributed RAM Switching Characteristics (SLICEM Only)

Table 55: CLB Distributed RAM Switching Characteristics
Speed Grade
-3 -2 -1 -1L
Sequential Delays
TSHCKO Clock to A – B outputs 0.92 1.10 1.36 1.49 ns, Max
TSHCKO_1 Clock to AMUX – BMUX outputs 1.19 1.40 1.71 1.87 ns, Max
Setup and Hold Times Before/After Clock CLK
TDS/TDH A – D inputs to CLK 0.62/0.18 0.72/0.20 0.88/0.22 0.98/0.23 ns, Min
TAS/TAH Address An inputs to clock 0.19/0.52 0.22/0.59 0.27/0.66 0.30/0.75 ns, Min
TWS/TWH WE input to clock 0.27/0.00 0.32/0.00 0.40/0.00 0.47/–0.03 ns, Min
TCECK/TCKCE CE input to CLK 0.28/–0.01 0.34/–0.01 0.41/–0.01 0.48/–0.05 ns, Min
Clock CLK
TMPW Minimum pulse width 0.70 0.82 1.00 1.04 ns, Min
TMCP Minimum clock period 1.40 1.64 2.00 2.08 ns, Min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
2. TSHCKO also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path.
CLB Shift Register Switching Characteristics (SLICEM Only)

Table 56: CLB Shift Register Switching Characteristics
Speed Grade
-3 -2 -1 -1L
Sequential Delays
TREG Clock to A – D outputs 1.11 1.30 1.58 1.74 ns, Max
TREG_MUX Clock to AMUX – DMUX output 1.37 1.60 1.93 2.12 ns, Max
TREG_M31 Clock to DMUX output via M31 output 1.08 1.27 1.55 1.74 ns, Max
TWS/TWH WE input 0.05/0.00 0.07/0.00 0.09/0.00 0.11/0.03 ns, Min
TCECK/TCKCE CE input to CLK 0.06/–0.01 0.08/–0.01 0.10/–0.01 0.12/0.02 ns, Min
TDS/TDH A – D inputs to CLK 0.64/0.18 0.76/0.21 0.94/0.24 1.07/0.23 ns, Min
Clock CLK
TMPW Minimum pulse width 0.60 0.70 0.85 0.89 ns, Min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is

Block RAM and FIFO Switching Characteristics

Table 57: Block RAM and FIFO Switching Characteristics
Speed Grade
-3 -2 -1 -1L
Block RAM and FIFO Clock-to-Out Delays
TRCKO_DO and TRCKO_DO_REG(1) Clock CLK to DOUT output 1.60 1.79 2.08 2.36 ns, Max
(without output register)(2)(3)
Clock CLK to DOUT output 0.60 0.66 0.75 0.83 ns, Max
(with output register)(4)(5)
TRCKO_DO_ECC and Clock CLK to DOUT output with ECC 2.62 2.89 3.30 3.73 ns, Max
TRCKO_DO_ECC_REG (without output register)(2)(3)
Clock CLK to DOUT output with ECC 0.71 0.77 0.86 0.94 ns, Max
(with output register)(4)(5)
TRCKO_CASC and Clock CLK to DOUT output with Cascade 2.49 2.77 3.18 3.61 ns, Max
TRCKO_CASC_REG (without output register)(2)
Clock CLK to DOUT output with Cascade 1.29 1.41 1.58 1.79 ns, Max
(with output register)(4)
TRCKO_FLAGS Clock CLK to FIFO flags outputs(6) 0.74 0.81 0.91 0.98 ns, Max
TRCKO_POINTERS Clock CLK to FIFO pointers outputs(7) 0.90 0.98 1.09 1.21 ns, Max
TRCKO_SDBIT_ECC and Clock CLK to BITERR (with output register) 0.62 0.68 0.76 0.82 ns, Max
TRCKO_SDBIT_ECC_REG
Clock CLK to BITERR (without output register) 2.21 2.46 2.84 3.23 ns, Max
TRCKO_PARITY_ECC Clock CLK to ECCPARITY in ECC encode only 0.86 0.94 1.06 1.18 ns, Max
mode
TRCKO_RDADDR_ECC and Clock CLK to RDADDR output with ECC 0.73 0.79 0.90 1.00 ns, Max
TRCKO_RDADDR_ECC_REG (without output register)
Clock CLK to RDADDR output with ECC 0.76 0.82 0.92 1.02 ns, Max
(with output register)
TRCCK_ADDR/TRCKC_ADDR ADDR inputs(8) 0.47/ 0.53/ 0.62/ 0.66/ ns, Min
0.27 0.29 0.32 0.34
TRDCK_DI/TRCKD_DI DIN inputs(9) 0.84/ 0.95/ 1.11/ 1.26/ ns, Min
0.30 0.32 0.34 0.36
TRDCK_DI_ECC/TRCKD_DI_ECC DIN inputs with block RAM ECC in standard mode(9) 0.47/ 0.52/ 0.59/ 0.68/ ns, Min
0.30 0.32 0.34 0.36
DIN inputs with block RAM ECC encode only(9) 0.68/ 0.75/ 0.85/ 0.97/ ns, Min
0.30 0.32 0.34 0.36
DIN inputs with FIFO ECC in standard mode(9) 0.77/ 0.87/ 1.02/ 1.16/ ns, Min
0.30 0.32 0.34 0.36
TRCCK_CLK/TRCKC_CLK Inject single/double bit error in ECC mode 0.90/ 1.02/ 1.20/ 1.56/ ns, Min
0.27 0.28 0.29 0.29
TRCCK_RDEN/TRCKC_RDEN Block RAM Enable (EN) input 0.31/ 0.35/ 0.41/ 0.44/ ns, Min
0.26 0.27 0.30 0.31
TRCCK_REGCE/TRCKC_REGCE CE input of output register 0.18/ 0.19/ 0.22/ 0.24/ ns, Min
0.25 0.27 0.31 0.33
TRCCK_RSTREG/TRCKC_RSTREG Synchronous RSTREG input 0.22/ 0.24/ 0.28/ 0.31/ ns, Min
0.23 0.24 0.26 0.27
TRCCK_RSTRAM/TRCKC_RSTRAM Synchronous RSTRAM input 0.32/ 0.36/ 0.41/ 0.46/ ns, Min
0.23 0.24 0.27 0.29

Table 57: Block RAM and FIFO Switching Characteristics (Cont’d)

Speed Grade
-3 -2 -1 -1L
TRCCK_WE/TRCKC_WE Write Enable (WE) input (Block RAM only) 0.44/ 0.47/ 0.52/ 0.67/ ns, Min
0.19 0.25 0.35 0.24
TRCCK_WREN/TRCKC_WREN WREN FIFO inputs 0.47/ 0.50/ 0.55/ 0.68/ ns, Min
0.26 0.27 0.30 0.31
TRCCK_RDEN/TRCKC_RDEN RDEN FIFO inputs 0.46/ 0.50/ 0.55/ 0.67/ ns, Min
0.26 0.27 0.30 0.31
Reset Delays
TRCO_FLAGS Reset RST to FIFO Flags/Pointers(10) 0.90 0.98 1.10 1.23 ns, Max
TRCCK_RSTREG/TRCKC_RSTREG FIFO reset timing(11) 0.22/ 0.24/ 0.28/ 0.31/ ns, Min
0.23 0.24 0.26 0.27
Maximum Frequency
FMAX Block RAM in TDP and SDP modes 600 540 450 340 MHz
(Write First and No Change modes)
Block RAM (Read First mode) 525 475 400 275 MHz
Block RAM (SDP mode)(12) 525 475 400 275 MHz
FMAX_CASCADE Block RAM Cascade 550 490 400 300 MHz
(Write First and No Change modes)
Block RAM Cascade (Read First mode) 475 425 350 235 MHz
FMAX_FIFO FIFO in all modes 600 540 450 340 MHz
FMAX_ECC Block RAM and FIFO in ECC configuration 450 400 325 250 MHz
Notes:
1. TRACE will report all of these parameters as TRCKO_DO.
2. TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters.
3. These parameters also apply to synchronous FIFO with DO_REG = 0.
4. TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters.
5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
6. TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR.
7. TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT.
8. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is
possible.
9. TRCKO_DI includes both A and B inputs as well as the parity inputs of A and B.
10. TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
11. The FIFO reset must be asserted for at least three positive clock edges.
12. When using ISE software v12.4 or later, if the RDADDR_COLLISION_HWCONFIG attribute is set to PERFORMANCE or the block RAM is
in single-port operation, then the faster FMAX for WRITE_FIRST/NO_CHANGE modes apply.

DSP48E1 Switching Characteristics

Table 58: DSP48E1 Switching Characteristics
Speed Grade
Symbol Description -1 -1 Units
-3 -2 -1L
(XC) (XQ)
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_{A, ACIN; B, BCIN}_{AREG; BREG}/ {A, ACIN, B, BCIN} input to 0.25/ 0.29/ 0.35/ 0.36/ 0.46/ ns
TDSPCKD_{A, ACIN; B, BCIN}_{AREG; BREG} {A, B} register CLK 0.27 0.30 0.34 0.34 0.39
TDSPDCK_C_CREG/TDSPCKD_C_CREG C input to C register CLK 0.16/ 0.19/ 0.22/ 0.25/ 0.33/ ns

0.20 0.22 0.24 0.24 0.30
TDSPDCK_D_DREG/TDSPCKD_D_DREG D input to D register CLK 0.07/ 0.10/ 0.15/ 0.16/ 0.24/ ns
0.31 0.34 0.39 0.39 0.45
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{A, ACIN, B, BCIN}_MREG_MULT/ {A, ACIN, B, BCIN} input to 2.36/ 2.70/ 3.21/ 3.21/ 3.66/ ns
TDSPCKD_{A, ACIN, B, BCIN}_MREG_MULT M register CLK 0.04 0.04 0.04 0.04 0.02
TDSPDCK_{A, D}_ADREG/ {A, D} input to AD register CLK 1.24/ 1.42/ 1.69/ 1.69/ 1.91/ ns
TDSPCKD_{A, D}_ADREG 0.10 0.12 0.13 0.13 0.16
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{A, ACIN, B, BCIN}_PREG_MULT/ {A, ACIN, B, BCIN} input to 3.83/ 4.37/ 5.20/ 5.20/ 5.94/ ns
TDSPCKD_{A, ACIN, B, BCIN}_PREG_MULT P register CLK using multiplier –0.13 –0.13 –0.13 –0.13 –0.24
TDSPDCK_D_PREG_MULT/ TDSPCKD_D_PREG_MULT D input to P register CLK 3.62/ 4.13/ 4.90/ 4.90/ 5.61/ ns
–0.47 –0.47 –0.47 –0.47 –0.77
TDSPDCK_{A, ACIN, B, BCIN}_PREG/ {A, ACIN, B, BCIN} input to 1.59/ 1.81/ 2.15/ 2.15/ 2.44/ ns
TDSPCKD_{A, ACIN, B, BCIN}_PREG P register CLK not using –0.13 –0.13 –0.13 –0.13 –0.24
multiplier
TDSPDCK_C_PREG/ TDSPCKD_C_PREG C input to P register CLK 1.42/ 1.61/ 1.91/ 1.91/ 2.16/ ns
–0.10 –0.10 –0.10 –0.10 –0.19
TDSPDCK_{PCIN, CARRYCASCIN, MULTSIGNIN}_PREG/ {PCIN, CARRYCASCIN, 1.23/ 1.41/ 1.67/ 1.67/ 1.91/ ns
TDSPCKD_{PCIN, CARRYCASCIN, MULTSIGNIN}_PREG MULTSIGNIN} input to –0.02 –0.02 –0.02 –0.02 –0.07
P register CLK
Setup and Hold Times of the CE Pins
TDSPDCK_{CEA; CEB}_{AREG; BREG}/ {CEA; CEB} input to {A; B} 0.14/ 0.17/ 0.22/ 0.22/ 0.30/ ns
TDSPCKD_{CEA; CEB}_{AREG; BREG} register CLK 0.19 0.22 0.25 0.25 0.28
TDSPDCK_CEC_CREG/ TDSPCKD_CEC_CREG CEC input to C register CLK 0.15/ 0.18/ 0.24/ 0.24/ 0.31/ ns
0.18 0.20 0.23 0.23 0.26
TDSPDCK_CED_DREG/ TDSPCKD_CED_DREG CED input to D register CLK 0.20/ 0.24/ 0.31/ 0.31/ 0.43/ ns
0.12 0.13 0.14 0.14 0.16
TDSPDCK_CEM_MREG/ TDSPCKD_CEM_MREG CEM input to M register CLK 0.16/ 0.20/ 0.26/ 0.26/ 0.32/ ns
0.19 0.21 0.25 0.25 0.28
TDSPDCK_CEP_PREG/ TDSPCKD_CEP_PREG CEP input to P register CLK 0.32/ 0.38/ 0.46/ 0.46/ 0.54/ ns
0.02 0.02 0.03 0.03 0.04
Setup and Hold Times of the RST Pins
TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/ {RSTA, RSTB} input to {A, B} 0.27/ 0.31/ 0.38/ 0.38/ 0.41/ ns
TDSPCKD_{RSTA; RSTB}_{AREG; BREG} register CLK 0.17 0.19 0.22 0.22 0.25
TDSPDCK_RSTC_CREG/ TDSPCKD_RSTC_CREG RSTC input to C register CLK 0.18/ 0.20/ 0.23/ 0.23/ 0.27/ ns
0.08 0.08 0.09 0.09 0.11
TDSPDCK_RSTD_DREG/ TDSPCKD_RSTD_DREG RSTD input to D register CLK 0.28/ 0.32/ 0.38/ 0.38/ 0.45/ ns
0.15 0.16 0.19 0.19 0.21
TDSPDCK_RSTM_MREG/ TDSPCKD_RSTM_MREG RSTM input to M register CLK 0.20/ 0.23/ 0.26/ 0.26/ 0.29/ ns
0.24 0.26 0.30 0.30 0.34

Table 58: DSP48E1 Switching Characteristics (Cont’d)

Speed Grade
-3 -2 -1L
(XC) (XQ)
TDSPDCK_RSTP_PREG/ TDSPCKD_RSTP_PREG RSTP input to P register CLK 0.26/ 0.30/ 0.35/ 0.35/ 0.43/ ns
0.04 0.04 0.05 0.05 0.06
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_{A, B}_{P, CARRYOUT}_MULT {A, B} input to {P, CARRYOUT} 3.76 4.29 5.08 5.08 5.87 ns
output using multiplier
TDSPDO_D_{P, CARRYOUT}_MULT D input to {P, CARRYOUT} 3.57 4.07 4.82 4.82 5.57 ns
output using multiplier
TDSPDO_{A, B}_{P, CARRYOUT} {A, B} input to {P, CARRYOUT} 1.55 1.76 2.07 2.07 2.41 ns
output not using multiplier
TDSPDO_{C, CARRYIN}_{P, CARRYOUT} {C, CARRYIN} input to {P, 1.38 1.56 1.83 1.83 2.13 ns
CARRYOUT} output
Combinatorial Delays from Input Pins to Cascading Output Pins
TDSPDO_{A; B}_{ACOUT; BCOUT} {A, B} input to {ACOUT, BCOUT} 0.49 0.56 0.65 0.65 0.73 ns
output
TDSPDO_{A, B}_{PCOUT, CARRYCASCOUT, {A, B} input to {PCOUT, 3.87 4.42 5.24 5.24 6.09 ns
MULTSIGNOUT}_MULT CARRYCASCOUT,
MULTSIGNOUT} output using
multiplier
TDSPDO_D_{PCOUT, CARRYCASCOUT, D input to {PCOUT, 3.66 4.17 4.94 4.94 5.76 ns
multiplier
TDSPDO_{A, B}_{PCOUT, CARRYCASCOUT, MULTSIGNOUT} {A, B} input to {PCOUT, 1.64 1.86 2.19 2.19 2.60 ns
CARRYCASCOUT,
MULTSIGNOUT} output not
using multiplier
TDSPDO__{C, CARRYIN}_{PCOUT, {C, CARRYIN} input to {PCOUT, 1.46 1.66 1.95 1.95 2.32 ns
CARRYCASCOUT,MULTSIGNOUT} CARRYCASCOUT,
MULTSIGNOUT} output
Combinatorial Delays from Cascading Input Pins to All Output Pins
TDSPDO_{ACIN, BCIN}_{P, CARRYOUT}_MULT {ACIN, BCIN} input to {P, 3.67 4.19 4.97 4.97 5.75 ns
CARRYOUT} output using
multiplier
TDSPDO_{ACIN, BCIN}_{P, CARRYOUT {ACIN, BCIN} input to {P, 1.43 1.63 1.92 1.92 2.25 ns
CARRYOUT} output not using
multiplier
TDSPDO_{ACIN; BCIN}_{ACOUT; BCOUT} {ACIN, BCIN} input to {ACOUT, 0.36 0.42 0.49 0.49 0.56 ns
BCOUT} output
TDSPDO_{ACIN, BCIN}_{PCOUT, CARRYCASCOUT, {ACIN, BCIN} input to {PCOUT, 3.76 4.29 5.10 5.10 5.94 ns
multiplier
TDSPDO_{ACIN, BCIN}_{PCOUT, CARRYCASCOUT, {ACIN, BCIN} input to {PCOUT, 1.52 1.73 2.05 2.05 2.44 ns
MULTSIGNOUT} CARRYCASCOUT,
using multiplier
TDSPDO_{PCIN, CARRYCASCIN, MULTSIGNIN}_ {PCIN, CARRYCASCIN, 1.19 1.35 1.60 1.60 1.87 ns
{P, CARRYOUT} MULTSIGNIN} input to {P,
CARRYOUT} output


Speed Grade
-3 -2 -1L
(XC) (XQ)
TDSPDO_{PCIN, CARRYCASCIN, MULTSIGNIN}_ {PCIN, CARRYCASCIN, 1.28 1.46 1.72 1.72 2.06 ns
{PCOUT, CARRYCASCOUT, MULTSIGNOUT} MULTSIGNIN} input to {PCOUT,
CARRYCASCOUT,
MULTSIGNOUT} output
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_{P, CARRYOUT}_PREG CLK (PREG) to {P, CARRYOUT} 0.38 0.43 0.50 0.50 0.57 ns
output
TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_PREG CLK (PREG) to 0.50 0.56 0.66 0.66 0.76 ns
{CARRYCASCOUT, PCOUT,
MULTSIGNOUT} output
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_{P, CARRYOUT}_MREG CLK (MREG) to {P, CARRYOUT} 1.72 1.96 2.30 2.30 2.69 ns
output
TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_MREG CLK (MREG) to {PCOUT, 1.81 2.06 2.43 2.43 2.88 ns
CARRYCASCOUT,
MULTSIGNOUT} output
TDSPCKO_{P, CARRYOUT}_ADREG_MULT CLK (ADREG) to {P, 2.79 3.16 3.72 3.72 4.32 ns
CARRYOUT} output
TDSPCKO_{PCOUT, CARRYCASCOUT, CLK (ADREG) to {PCOUT, 2.87 3.26 3.84 3.84 4.51 ns
MULTSIGNOUT}_ADREG_MULT CARRYCASCOUT,
MULTSIGNOUT} output
Clock to Outs from Input Register Clock to Output Pins
TDSPCKO_{P, CARRYOUT}_{AREG, BREG}_MULT CLK (AREG, BREG) to {P, 3.97 4.52 5.36 5.36 6.20 ns
CARRYOUT} output using
multiplier
TDSPCKO_{P, CARRYOUT}_{AREG, BREG} CLK (AREG, BREG) to {P, 1.70 1.93 2.27 2.27 2.65 ns
CARRYOUT} output not using
multiplier
TDSPCKO_{P, CARRYOUT}_CREG CLK (CREG) to {P, CARRYOUT} 1.70 1.93 2.27 2.27 2.80 ns
output
TDSPCKO_{P, CARRYOUT}_DREG_MULT CLK (DREG) to {P, CARRYOUT} 3.89 4.44 5.25 5.25 6.07 ns
output
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUT; BCOUT}_{AREG; BREG} CLK (AREG, BREG) to {P, 0.66 0.76 0.89 0.89 1.01 ns
CARRYOUT} output
TDSPCKO_{PCOUT, CARRYCASCOUT, CLK (AREG, BREG) to {PCOUT, 4.05 4.63 5.49 5.49 6.39 ns
MULTSIGNOUT}_{AREG, BREG}_MULT CARRYCASCOUT,
multiplier
TDSPCKO_{PCOUT, CARRYCASCOUT, CLK (AREG, BREG) to {PCOUT, 1.79 2.03 2.40 2.40 2.84 ns
MULTSIGNOUT}_{AREG, BREG} CARRYCASCOUT,
using multiplier
TDSPCKO_{PCOUT, CARRYCASCOUT, CLK (DREG) to {PCOUT, 3.98 4.54 5.38 5.38 6.26 ns
MULTSIGNOUT}_DREG_MULT CARRYCASCOUT,
multiplier
TDSPCKO_{PCOUT, CARRYCASCOUT, MULTSIGNOUT}_CREG CLK (CREG) to {PCOUT, 1.78 2.03 2.40 2.40 2.99 ns
CARRYCASCOUT,
MULTSIGNOUT} output


Speed Grade
-3 -2 -1L
(XC) (XQ)
Maximum Frequency
FMAX With all registers used 600 540 450 450 410 MHz
FMAX_PATDET With pattern detector 551 483 408 408 356 MHz
FMAX_MULT_NOMREG Two register multiply without 356 311 262 262 224 MHz
MREG
FMAX_MULT_NOMREG_PATDET Two register multiply without 327 286 241 241 211 MHz
MREG with pattern detect
FMAX_PREADD_MULT_NOADREG Without ADREG 398 347 292 292 254 MHz
FMAX_PREADD_MULT_NOADREG_PATDET Without ADREG with pattern 398 347 292 292 254 MHz
detect
FMAX_NOPIPELINEREG Without pipeline registers 266 233 196 196 171 MHz
(MREG, ADREG)
FMAX_NOPIPELINEREG_PATDET Without pipeline registers 250 219 184 184 160 MHz
(MREG, ADREG) with pattern
detect
Configuration Switching Characteristics

Table 59: Configuration Switching Characteristics
Speed Grade
-3 -2 -1 -1L
Power-up Timing Characteristics
TPL(1) Program Latency 5 5 5 5 ms, Max
TPOR(1) Power-on-Reset 15/55 15/55 15/55 15/60 ms, Min/Max
TICCK CCLK (output) delay 400 400 400 400 ns, Min
TPROGRAM Program Pulse Width 250 250 250 250 ns, Min
Master/Slave Serial Mode Programming Switching
TDCCK/TCCKD DIN Setup/Hold, slave mode 4.0/0.0 4.0/0.0 4.0/0.0 4.5/0.0 ns, Min
TDSCCK/TSCCKD DIN Setup/Hold, master mode 4.0/0.0 4.0/0.0 4.0/0.0 5.0/0.0 ns, Min
TCCO DOUT at 2.5V 6 6 6 7 ns, Max
DOUT at 1.8V 6 6 6 7 ns, Max
FMCCK Maximum CCLK frequency, serial modes 105 105 105 70 MHz, Max
FMCCKTOL Frequency Tolerance, master mode with respect to 55 55 55 60 %
nominal CCLK.
FMSCCK Slave mode external CCLK 100 100 100 100 MHz
SelectMAP Mode Programming Switching
TSMDCCK/TSMCCKD SelectMAP Data Setup/Hold 4.0/0.0 4.0/0.0 4.0/0.0 5.5/0.0 ns, Min
TSMCSCCK/TSMCCKCS CSI_B Setup/Hold 4.0/0.0 4.0/0.0 4.0/0.0 5.5/0.0 ns, Min
TSMCCKW/TSMWCCK RDWR_B Setup/Hold 10.0/0.0 10.0/0.0 10.0/0.0 16.0/0.0 ns, Min
TSMCKCSO CSO_B clock to out 6 6 6 7 ns, Max
(330 Ω pull-up resistor required)
TSMCO CCLK to DATA out in readback at 2.5V 6 6 6 7 ns, Max
CCLK to DATA out in readback at 1.8V 6 6 6 7 ns, Max

Table 59: Configuration Switching Characteristics (Cont’d)

Speed Grade
-3 -2 -1 -1L
TSMCKBY CCLK to BUSY out in readback at 2.5V 6 6 6 7 ns, Max
CCLK to BUSY out in readback at 1.8V 6 6 6 7 ns, Max
FSMCCK Maximum Frequency with respect to nominal CCLK 100 100 100 70 MHz, Max
FRBCCK Maximum Readback Frequency with respect to 100 100 100 60 MHz, Max
nominal CCLK
FMCCKTOL Frequency tolerance, master mode with 55 55 55 60 %
respect to nominal CCLK
Boundary-Scan Port Timing Specifications
TTAPTCK/TTCKTAP TMS and TDI Setup time before TCK/ Hold time 3.0/2.0 3.0/2.0 3.0/2.0 4.0/2.0 ns, Min
after TCK
TTCKTDO TCK falling edge to TDO output valid at 2.5V 6 6 6 7 ns, Max
TCK falling edge to TDO output valid at 1.8V 6 6 6 7 ns, Max
FTCK Maximum configuration TCK clock frequency 66 66 66 33 MHz, Max
FTCKB_MIN Minimum boundary-scan TCK clock frequency 15 15 15 15 MHz, Min
when using IEEE Std 1149.6 (AC-JTAG). Minimum
operating temperature for IEEE Std 1149.6 is 0°C.
FTCKB Maximum boundary-scan TCK clock frequency 66 66 66 33 MHz, Max
BPI Master Flash Mode Programming Switching
TBPICCO(2) ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B 6 6 6 7 ns
outputs valid after CCLK rising edge at 2.5V
ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B 6 6 6 7 ns
outputs valid after CCLK rising edge at 1.8V
TBPIDCC/TBPICCD Setup/Hold on D[15:0] data input pins 4.0/0.0 4.0/0.0 4.0/0.0 5.0/0.0 ns
TINITADDR Minimum period of initial ADDR[25:0] address 3 3 3 3 CCLK cycles
cycles
SPI Master Flash Mode Programming Switching
TSPIDCC/TSPIDCCD DIN Setup/Hold before/after the rising CCLK edge 3.0/0.0 3.0/0.0 3.0/0.0 3.5/0.0 ns
TSPICCM MOSI clock to out at 2.5V 6 6 6 7 ns
MOSI clock to out at 1.8V 6 6 6 7 ns
TSPICCFC FCS_B clock to out at 2.5V 6 6 6 7 ns
FCS_B clock to out at 1.8V 6 6 6 7 ns
TFSINIT/TFSINITH FS[2:0] to INIT_B rising edge Setup and Hold 2 2 2 2 µs
CCLK Output (Master Modes)
TMCCKL Master CCLK clock Low time duty cycle 45/55 45/55 45/55 40/60 %, Min/Max
TMCCKH Master CCLK clock High time duty cycle 45/55 45/55 45/55 40/60 %, Min/Max
CCLK Input (Slave Modes)
TSCCKL Slave CCLK clock minimum Low time 2.5 2.5 2.5 2.5 ns, Min
TSCCKH Slave CCLK clock minimum High time 2.5 2.5 2.5 2.5 ns, Min
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
FDCK Maximum frequency for DCLK 200 200 200 200 MHz
TMMCMDCK_DADDR/ DADDR Setup/Hold 1.25/ 1.40/ 1.63/ 1.64/ ns
TMMCMCKD_DADDR 0.00 0.00 0.00 0.00

Table 59: Configuration Switching Characteristics (Cont’d)

Speed Grade
-3 -2 -1 -1L
TMMCMDCK_DI/ DI Setup/Hold 1.25/ 1.40/ 1.63/ 1.64/ ns
TMMCMCKD_DI 0.00 0.00 0.00 0.00
TMMCMDCK_DEN/ DEN Setup/Hold time 1.25/ 1.40/ 1.63/ 1.64/ ns
TMMCMCKD_DEN 0.00 0.00 0.00 0.00
TMMCMDCK_DWE/ DWE Setup/Hold time 1.25/ 1.40/ 1.63/ 1.64/ ns
TMMCMCKD_DWE 0.00 0.00 0.00 0.00
TMMCMCKO_DO CLK to out of DO(3) 2.60 3.02 3.64 3.68 ns
TMMCMCKO_DRDY CLK to out of DRDY 0.32 0.34 0.38 0.38 ns
Notes:
1. To support longer delays in configuration, use the design solutions described in UG360:Virtex-6 FPGA Configuration User Guide.
2. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
3. DO will hold until next DRP operation.
Clock Buffers and Networks

Table 60: Global Clock Switching Characteristics (Including BUFGCTRL)
Speed Grade
Symbol Description Devices Units
-3 -2 -1 -1L
TBCCCK_CE/TBCCKC_CE(1) CE pins Setup/Hold All 0.11/ 0.13/ 0.16/ 0.13/ ns
0.00 0.00 0.00 0.00
TBCCCK_S/TBCCKC_S(1) S pins Setup/Hold All 0.11/ 0.13/ 0.16/ 0.13/ ns
0.00 0.00 0.00 0.00
TBCCKO_O(2) BUFGCTRL delay from I0/I1 to O All 0.07 0.08 0.10 0.10 ns
Maximum Frequency
All except LX760 800 750 700 667 MHz
FMAX Global clock tree (BUFG)
LX760 N/A 700 700 667 MHz
Notes:
1. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold
times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching
between clocks.
2. TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values.
Table 61: Input/Output Clock Switching Characteristics (BUFIO)

Speed Grade
-3 -2 -1 -1L
TBIOCKO_O Clock to out delay from I to O 0.14 0.16 0.18 0.21 ns
Maximum Frequency
FMAX I/O clock tree (BUFIO) 800 800 710 710 MHz
Table 62: Regional Clock Switching Characteristics (BUFR)

Speed Grade
-3 -2 -1 -1L
TBRCKO_O Clock to out delay from I to O 0.56 0.62 0.73 0.82 ns
Clock to out delay from I to O with Divide Bypass attribute 0.28 0.31 0.36 0.41 ns
TBRCKO_O_BYP
set

Table 62: Regional Clock Switching Characteristics (BUFR) (Cont’d)

Speed Grade
-3 -2 -1 -1L
TBRDO_O Propagation delay from CLR to O 0.69 0.74 0.80 1.12 ns
Maximum Frequency
FMAX(1) Regional clock tree (BUFR) 500 420 300 300 MHz
Notes:
1. The maximum input frequency to the BUFR is the BUFIO FMAX frequency.
Table 63: Horizontal Clock Buffer Switching Characteristics (BUFH)

Speed Grade
-3 -2 -1 -1L
TBHCKO_O BUFH delay from I to O 0.10 0.11 0.13 0.15 ns
0.04/ 0.04/ 0.05/ 0.04/ ns
TBHCCK_CE/TBHCKC_CE CE pin Setup and Hold
0.04 0.04 0.05 0.04
Maximum Frequency
FMAX Horizontal clock buffer (BUFH) 800 750 700 667 MHz
MMCM Switching Characteristics

Table 64: MMCM Specification
Speed Grade
-3 -2 -1 -1L
FINMAX Maximum Input Clock Frequency(1) 800 750 700 700 MHz
FINMIN Minimum Input Clock Frequency 10 10 10 10 MHz
FINJITTER Maximum Input Clock Period Jitter < 20% of clock input period or 1 ns Max
FINDUTY(2) Allowable Input Duty Cycle: 10—49 MHz 25/75 %
Allowable Input Duty Cycle: 50—199 MHz 30/70 %
Allowable Input Duty Cycle: >500 MHz 45/55 %
FMIN_PSCLK Minimum Dynamic Phase Shift Clock Frequency 0.01 0.01 0.01 0.01 MHz
FMAX_PSCLK Maximum Dynamic Phase Shift Clock Frequency 550 500 450 450 MHz
FVCOMIN Minimum MMCM VCO Frequency 600 600 600 600 MHz
FVCOMAX Maximum MMCM VCO Frequency 1600 1440 1200 1200 MHz
FBANDWIDTH Low MMCM Bandwidth at Typical(3) 1.00 1.00 1.00 1.00 MHz
High MMCM Bandwidth at Typical(3) 4.00 4.00 4.00 4.00 MHz
TSTATPHAOFFSET Static Phase Offset of the MMCM Outputs(4) 0.12 0.12 0.12 0.12 ns
TOUTJITTER MMCM Output Jitter(5) Note 3
TOUTDUTY MMCM Output Clock Duty Cycle Precision(6) 0.15 0.20 0.20 0.20 ns
TLOCKMAX MMCM Maximum Lock Time 100 100 100 100 µs
FOUTMAX MMCM Maximum Output Frequency 800 750 700 700 MHz
FOUTMIN MMCM Minimum Output Frequency(7)(8) 4.69 4.69 4.69 4.69 MHz
TEXTFDVAR External Clock Feedback Variation < 20% of clock input period or 1 ns Max

Table 64: MMCM Specification (Cont’d)

Speed Grade
-3 -2 -1 -1L
RSTMINPULSE Minimum Reset Pulse Width 1.5 1.5 1.5 1.5 ns
FPFDMAX Maximum Frequency at the Phase Frequency 550 500 450 450 MHz
Detector with Bandwidth Set to High or Optimized(9)
Maximum Frequency at the Phase Frequency 300 300 300 300 MHz
Detector with Bandwidth Set to Low
FPFDMIN Minimum Frequency at the Phase Frequency 135 135 135 135 MHz
Detector with Bandwidth Set to High or Optimized
Minimum Frequency at the Phase Frequency 10 10 10 10 MHz
Detector with Bandwidth Set to Low
TFBDELAY Maximum Delay in the Feedback Path 3 ns Max or one CLKIN cycle
TMMCMDCK_PSEN/ Setup and Hold of Phase Shift Enable 1.04 1.04 1.04 1.04 ns
TMMCMCKD_PSEN 0.00 0.00 0.00 0.00
TMMCMDCK_PSINCDEC/ Setup and Hold of Phase Shift Increment/Decrement 1.04 1.04 1.04 1.04 ns
TMMCMCKD_PSINCDEC 0.00 0.00 0.00 0.00
TMMCMCKO_PSDONE Phase Shift Clock-to-Out of PSDONE 0.32 0.34 0.38 0.38 ns
Notes:
1. When DIVCLK_DIVIDE = 3 or 4, FINMAX is 315 MHz.
2. This duty cycle specification does not apply to the GTH_QUAD (GTH) to MMCM connection. The GTH transceivers drive the MMCMs at the
following maximum frequencies: 323 MHz for -1 speed grade devices, 350 MHz for -2 speed grade devices, or 350 MHz for -3 speed grade
devices.
3. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
4. The static offset is measured between any MMCM outputs with identical phase.
5. Values for this parameter are available in the Clocking Wizard.
See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm.
6. Includes global clock buffer.
7. Calculated as FVCO/128 assuming output duty cycle is 50%.
8. When CLKOUT4_CASCADE = TRUE, FOUTMIN is 0.036 MHz.
9. In ISE software 12.3 (or earlier versions supporting the Virtex-6 family), the phase frequency detector Optimized bandwidth setting is
equivalent to the High bandwidth setting. Starting with ISE software 12.4, the Optimized bandwidth setting is automatically adjusted to Low
when the software can determine that the phase frequency detector input is less than 135 MHz.

Virtex-6 Device Pin-to-Pin Output Parameter Guidelines

All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 65. Values are expressed in nanoseconds unless otherwise noted.
Table 65: Global Clock Input to Output Delay Without MMCM

Speed Grade
-3 -2 -1 -1L
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without MMCM.
TICKOF Global Clock input and OUTFF without XC6VLX75T 4.91 5.32 5.88 6.02 ns
MMCM
XC6VLX130T 4.89 5.33 6.00 6.13 ns
XC6VLX195T 5.02 5.46 6.13 6.27 ns
XC6VLX240T 5.02 5.46 6.13 6.27 ns
XC6VLX365T 5.30 5.75 6.43 6.37 ns
XC6VLX550T N/A 6.02 6.72 6.60 ns
XC6VLX760 N/A 6.26 6.97 6.87 ns
XC6VSX315T 5.40 5.85 6.54 6.49 ns
XC6VSX475T N/A 6.01 6.71 6.61 ns
XC6VHX250T 5.18 5.63 6.30 N/A ns
XC6VHX255T 5.20 5.66 6.34 N/A ns
XC6VHX380T 5.38 5.84 6.53 N/A ns
XC6VHX565T N/A 6.03 6.71 N/A ns
XQ6VLX130T N/A 5.33 6.00 6.13 ns
XQ6VLX240T N/A 5.46 6.13 6.27 ns
XQ6VLX550T N/A N/A 6.72 6.60 ns
XQ6VSX315T N/A 5.85 6.54 6.49 ns
XQ6VSX475T N/A N/A 6.71 6.61 ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.

Table 66: Global Clock Input to Output Delay With MMCM

Speed Grade
-3 -2 -1 -1L
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with MMCM.
TICKOFMMCMGC Global Clock Input and OUTFF with XC6VLX75T 2.34 2.50 2.77 2.85 ns
MMCM
XC6VLX130T 2.35 2.51 2.78 2.87 ns
XC6VLX195T 2.36 2.52 2.79 2.88 ns
XC6VLX240T 2.36 2.52 2.79 2.88 ns
XC6VLX365T 2.37 2.53 2.79 2.89 ns
XC6VLX550T N/A 2.55 2.82 2.93 ns
XC6VLX760 N/A 2.54 2.82 2.92 ns
XC6VSX315T 2.35 2.51 2.79 2.87 ns
XC6VSX475T N/A 2.43 2.70 2.79 ns
XC6VHX250T 2.36 2.53 2.80 N/A ns
XC6VHX255T 2.46 2.63 2.91 N/A ns
XC6VHX380T 2.39 2.59 2.83 N/A ns
XC6VHX565T N/A 2.54 2.81 N/A ns
XQ6VLX130T N/A 2.51 2.78 2.87 ns
XQ6VLX240T N/A 2.52 2.79 2.88 ns
XQ6VLX550T N/A N/A 2.82 2.93 ns
XQ6VSX315T N/A 2.51 2.79 2.87 ns
XQ6VSX475T N/A N/A 2.70 2.79 ns
Notes:
2. MMCM output jitter is already included in the timing calculation.

Table 67: Clock-Capable Clock Input to Output Delay With MMCM

Speed Grade
-3 -2 -1 -1L
LVCMOS25 Clock-capable Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with MMCM.
TICKOFMMCMCC Clock-capable Clock Input and OUTFF XC6VLX75T 2.22 2.38 2.63 2.72 ns
with MMCM
XC6VLX130T 2.24 2.39 2.65 2.74 ns
XC6VLX195T 2.24 2.40 2.65 2.75 ns
XC6VLX240T 2.24 2.40 2.65 2.75 ns
XC6VLX365T 2.25 2.42 2.65 2.76 ns
XC6VLX550T N/A 2.43 2.68 2.80 ns
XC6VLX760 N/A 2.42 2.69 2.79 ns
XC6VSX315T 2.23 2.38 2.65 2.73 ns
XC6VSX475T N/A 2.30 2.57 2.66 ns
XC6VHX250T 2.25 2.41 2.67 N/A ns
XC6VHX255T 2.35 2.51 2.78 N/A ns
XC6VHX380T 2.27 2.43 2.69 N/A ns
XC6VHX565T N/A 2.41 2.68 N/A ns
XQ6VLX130T N/A 2.39 2.65 2.74 ns
XQ6VLX240T N/A 2.40 2.65 2.75 ns
XQ6VLX550T N/A N/A 2.68 2.80 ns
XQ6VSX315T N/A 2.38 2.65 2.73 ns
XQ6VSX475T N/A N/A 2.57 2.66 ns
Notes:
2. MMCM output jitter is already included in the timing calculation.

Virtex-6 Device Pin-to-Pin Input Parameter Guidelines

All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 68. Values are expressed in nanoseconds unless otherwise noted.
Table 68: Global Clock Input Setup and Hold Without MMCM
Speed Grade
-3 -2 -1 -1L
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSFD/ TPHFD Full Delay (Legacy Delay or Default Delay) XC6VLX75T 1.33/ 1.44/ 1.75/ 2.18/ ns
Global Clock Input and IFF(2) without MMCM 0.03 0.03 0.03 –0.22
XC6VLX130T 1.31/ 1.54/ 1.88/ 2.31/ ns
–0.08 –0.08 –0.08 –0.12
XC6VLX195T 1.36/ 1.60/ 1.97/ 2.40/ ns
–0.11 –0.11 –0.11 –0.25
XC6VLX240T 1.36/ 1.60/ 1.97/ 2.40/ ns
–0.11 –0.11 –0.11 –0.25
XC6VLX365T 1.79/ 1.87/ 2.17/ 2.48/ ns
–0.28 –0.28 –0.28 –0.24
XC6VLX550T N/A 2.22/ 2.36/ 2.77/ ns
–0.12 –0.12 –0.26
XC6VLX760 N/A 2.19/ 2.35/ 2.71/ ns
–0.24 –0.24 –0.21
XC6VSX315T 1.75/ 1.85/ 2.06/ 2.47/ ns
–0.09 –0.09 –0.09 –0.24
XC6VSX475T N/A 2.14/ 2.31/ 2.71/ ns
–0.14 –0.14 –0.30
XC6VHX250T 1.93/ 2.04/ 2.25/ N/A ns
–0.22 –0.22 –0.22
XC6VHX255T 1.81/ 2.11/ 2.56/ N/A ns
–0.33 –0.33 –0.33
XC6VHX380T 1.93/ 2.04/ 2.25/ N/A ns
–0.11 –0.11 –0.11
XC6VHX565T N/A 2.20/ 2.39/ N/A ns
–0.12 –0.12
XQ6VLX130T N/A 1.54/ 1.88/ 2.31/ ns
–0.08 –0.08 –0.12
XQ6VLX240T N/A 1.60/ 1.97/ 2.40/ ns
–0.11 –0.11 –0.25
XQ6VLX550T N/A N/A 2.36/ 2.77/ ns
–0.12 –0.26
XQ6VSX315T N/A 1.85/ 2.06/ 2.47/ ns
–0.09 –0.09 –0.24
XQ6VSX475T N/A N/A 2.31/ 2.71/ ns
–0.14 –0.30
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch
3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0"
is listed, there is no positive hold time.

Table 69: Global Clock Input Setup and Hold With MMCM
Speed Grade
-3 -2 -1 -1L
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSMMCMGC/ No Delay Global Clock Input and IFF(2) XC6VLX75T 1.45/ 1.57/ 1.72/ 1.78/ ns
TPHMMCMGC with MMCM –0.18 –0.18 –0.18 –0.08
XC6VLX130T 1.53/ 1.65/ 1.81/ 1.87/ ns
–0.18 –0.18 –0.18 –0.07
XC6VLX195T 1.54/ 1.66/ 1.82/ 1.87/ ns
–0.17 –0.17 –0.17 –0.08
XC6VLX240T 1.54/ 1.66/ 1.82/ 1.87/ ns
–0.17 –0.17 –0.17 –0.08
XC6VLX365T 1.55/ 1.67/ 1.83/ 1.87/ ns
–0.18 –0.18 –0.18 –0.07
XC6VLX550T N/A 1.84/ 2.02/ 2.06/ ns
–0.17 –0.17 –0.06
XC6VLX760 N/A 2.26/ 2.49/ 2.06/ ns
–0.13 –0.13 –0.03
XC6VSX315T 1.56/ 1.68/ 1.84/ 1.89/ ns
–0.18 –0.18 –0.18 –0.08
XC6VSX475T N/A 1.85/ 2.03/ 2.07/ ns
–0.23 –0.23 –0.13
XC6VHX250T 1.52/ 1.64/ 1.80/ N/A ns
–0.17 –0.17 –0.17
XC6VHX255T 1.52/ 1.64/ 1.85/ N/A ns
–0.12 –0.12 –0.12
XC6VHX380T 1.68/ 1.81/ 1.99/ N/A ns
–0.16 –0.16 –0.16
XC6VHX565T N/A 1.81/ 1.99/ N/A ns
–0.01 –0.01
XQ6VLX130T N/A 1.65/ 1.81/ 1.87/ ns
–0.18 –0.18 –0.07
XQ6VLX240T N/A 1.66/ 1.82/ 1.87/ ns
–0.17 –0.17 –0.08
XQ6VLX550T N/A N/A 2.02/ 2.06/ ns
–0.17 –0.06
XQ6VSX315T N/A 1.68/ 1.84/ 1.89/ ns
–0.18 –0.18 –0.08
XQ6VSX475T N/A N/A 2.03/ 2.07/ ns
–0.23 –0.13
Notes:
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.

Table 70: Clock-Capable Clock Input Setup and Hold With MMCM
Speed Grade
-3 -2 -1 -1L
Input Setup and Hold Time Relative to Clock-capable Clock Input Signal for LVCMOS25 Standard.(1)
TPSMMCMCC/ No Delay Clock-capable Clock Input and XC6VLX75T 1.56/ 1.69/ 1.86/ 1.91/ ns
TPHMMCMCC IFF(2) with MMCM –0.25 –0.25 –0.25 –0.15
XC6VLX130T 1.64/ 1.78/ 1.95/ 2.00/ ns
–0.25 –0.25 –0.25 –0.14
XC6VLX195T 1.65/ 1.79/ 1.96/ 2.01/ ns
–0.24 –0.24 –0.24 –0.15
XC6VLX240T 1.65/ 1.79/ 1.96/ 2.01/ ns
–0.24 –0.24 –0.24 –0.15
XC6VLX365T 1.66/ 1.79/ 1.97/ 2.02/ ns
–0.25 –0.25 –0.25 –0.15
XC6VLX550T N/A 1.97/ 2.16/ 2.19/ ns
–0.24 –0.24 –0.14
XC6VLX760 N/A 2.39/ 2.63/ 2.21/ ns
–0.20 –0.20 –0.10
XC6VSX315T 1.67/ 1.80/ 1.98/ 2.03/ ns
–0.25 –0.25 –0.25 –0.16
XC6VSX475T N/A 1.98/ 2.17/ 2.21/ ns
–0.29 –0.29 –0.20
XC6VHX250T 1.63/ 1.76/ 1.94/ N/A ns
–0.24 –0.24 –0.24
XC6VHX255T 1.63/ 1.76/ 1.99/ N/A ns
–0.19 –0.19 –0.19
XC6VHX380T 1.80/ 1.94/ 2.13/ N/A ns
–0.23 –0.23 –0.23
XC6VHX565T N/A 1.94/ 2.13/ N/A ns
–0.08 –0.08
XQ6VLX130T N/A 1.78/ 1.95/ 2.00/ ns
–0.25 –0.25 –0.14
XQ6VLX240T N/A 1.79/ 1.96/ 2.01/ ns
–0.24 –0.24 –0.15
XQ6VLX550T N/A N/A 2.16/ 2.19/ ns
–0.24 –0.14
XQ6VSX315T N/A 1.80/ 1.98/ 2.03/ ns
–0.25 –0.25 –0.16
XQ6VSX475T N/A N/A 2.17/ 2.21/ ns
–0.29 –0.20
Notes:
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.

Clock Switching Characteristics

The parameters in this section provide the necessary values for calculating timing budgets for Virtex-6 FPGA clock
transmitter and receiver data-valid windows.
Table 71: Duty Cycle Distortion and Clock-Tree Skew

Speed Grade
-3 -2 -1 -1L
TDCD_CLK Global Clock Tree Duty Cycle Distortion(1) All 0.12 0.12 0.12 0.12 ns
TCKSKEW Global Clock Tree Skew(2) XC6VLX75T 0.15 0.16 0.18 0.17 ns
XC6VLX130T 0.25 0.26 0.29 0.28 ns
XC6VLX195T 0.26 0.27 0.31 0.30 ns
XC6VLX240T 0.26 0.27 0.31 0.30 ns
XC6VLX365T 0.28 0.29 0.31 0.31 ns
XC6VLX550T N/A 0.50 0.54 0.54 ns
XC6VLX760 N/A 0.51 0.56 0.56 ns
XC6VSX315T 0.27 0.28 0.32 0.30 ns
XC6VSX475T N/A 0.39 0.44 0.42 ns
XC6VHX250T 0.25 0.26 0.29 N/A ns
XC6VHX255T 0.35 0.37 0.41 N/A ns
XC6VHX380T 0.45 0.47 0.52 N/A ns
XC6VHX565T N/A 0.46 0.51 N/A ns
XQ6VLX130T N/A 0.26 0.29 0.28 ns
XQ6VLX240T N/A 0.27 0.31 0.30 ns
XQ6VLX550T N/A N/A 0.54 0.54 ns
XQ6VSX315T N/A 0.28 0.32 0.30 ns
XQ6VSX475T N/A N/A 0.44 0.42 ns
TDCD_BUFIO I/O clock tree duty cycle distortion All 0.08 0.08 0.08 0.08 ns
TBUFIOSKEW I/O clock tree skew across one clock region All 0.03 0.03 0.03 0.02 ns
TBUFIOSKEW2 I/O clock tree skew across three clock regions All 0.10 0.12 0.23 0.12 ns
TDCD_BUFR Regional clock tree duty cycle distortion All 0.15 0.15 0.15 0.15 ns
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical
rise/fall times.
2. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to your application.

Table 72: Package Skew

Symbol Description Device Package Value Units
TPKGSKEW Package Skew(1) FF484 95 ps
XC6VLX75T
FF784 146 ps
FF484 95 ps
XC6VLX130T FF784 146 ps
FF1156 165 ps
FF784 145 ps
XC6VLX195T
FF1156 182 ps
FF784 146 ps
XC6VLX240T FF1156 182 ps
FF1759 187 ps
FF1156 189 ps
XC6VLX365T
FF1759 184 ps
FF1759 196 ps
XC6VLX550T
FF1760 249 ps
XC6VLX760 FF1760 236 ps
FF1156 168 ps
XC6VSX315T
FF1759 190 ps
FF1156 168 ps
XC6VSX475T
FF1759 204 ps
XC6VHX250T FF1154 166 ps
FF1155 168 ps
XC6VHX255T
FF1923 228 ps
FF1154 159 ps
FF1155 172 ps
XC6VHX380T
FF1923 227 ps
FF1924 220 ps
FF1923 232 ps
XC6VHX565T
FF1924 197 ps
XQ6VLX130T RF784 146 ps
RF1156 165 ps
FFG1156 165 ps
RF1156 182 ps
FFG1156 182 ps
RF1759 187 ps
XQ6VSX315T RF1156 168 ps
FFG1156 168 ps
RF1759 190 ps
XQ6VSX475T RF1156 168 ps
FFG1156 168 ps
RF1759 204 ps
Notes:
1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest flight time to longest flight time
from Pad to Ball (7.0 ps per mm).
2. Package trace length information is available for these device/package combinations. This information can be used to deskew the package.

Table 73: Sample Window

Speed Grade
-3 -2 -1 -1L
TSAMP Sampling Error at Receiver Pins(1) All 510 560 610 670 ps
TSAMP_BUFIO Sampling Error at Receiver Pins using BUFIO(2) All 300 350 400 440 ps
Notes:
1. This parameter indicates the total sampling error of Virtex-6 FPGA DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements
include:
- CLK0 MMCM jitter
- MMCM accuracy (phase offset)
- MMCM phase shift resolution
These measurements do not include package or clock tree skew.
2. This parameter indicates the total sampling error of Virtex-6 FPGA DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers’ edges of
operation. These measurements do not include package or clock tree skew.
Table 74: Pin-to-Pin Setup/Hold and Clock-to-Out

Speed Grade
-3 -2 -1 -1L
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
TPSCS/TPHCS Setup/Hold of I/O clock –0.28/1.09 –0.28/1.16 –0.28/1.33 –0.18/1.79 ns
Pin-to-Pin Clock-to-Out Using BUFIO
TICKOFCS Clock-to-Out of I/O clock 4.22 4.59 5.22 5.63 ns
Revision History
The following table shows the revision history for this document:
Date Version Description of Revisions

06/24/2009 1.0 Initial Xilinx release.
07/16/2009 1.1 Revised the maximum VCCAUX and VIN numbers in Table 2, page 2. Removed empty column from
Table 3, page 3. Revised specifications on Table 20, page 13. Updated Table 38, page 22 and added
notes 1 and 2. Revised TDLYCCO_RDY, TIDELAYCTRL_RPW, and TIDELAYPAT_JIT in Table 53, page 41.
Updated Table 58, page 46 to more closely match the DSP48E1 speed specifications. Updated
TTAPTCK/TTCKTAP in Table 59, page 49. Updated XC6VLX130T parameters in Table 68 through
Table 70, page 59.
08/19/2009 1.2 Added values for -1L voltages and speed grade in all pertinent tables. Added VFS and notes to Table 1
and Table 2. Removed DVPPIN from the example in Figure 2. Added networking applications to
Table 41, page 25. Changed and added to the block RAM FMAX section in Table 57, page 44 including
removing Note 12. Changed FPFDMAX values and corrected units for TSTATPHAOFFSET and TOUTDUTY
in Table 64, page 52. Updated Table 71, page 60.
09/16/2009 2.0 Added Virtex-6 HXT devices to entire document including GTH Transceiver Specifications. Updated
speed specifications as described in Switching Characteristics, includes changes in Table 51,
Table 57, Table 58, and Table 66 through Table 70. Comprehensive changes to Table 14, Table 15, and
Table 16. Added conditions to DVPPOUT and revised description of TOSKEW in Table 17. Removed VISE
specification and note from Table 18. Added note 3 to Table 23. Updated note 3 in Table 24. Updated
LVCMOS25 delays in Table 44. Updated specification for TIOTPHZ in Table 46. Removed TBUFHSKEW
from Table 71, page 60 and added values for TBUFIOSKEW. Added values in Table 74.


01/18/2010 2.1 Changed absolute maximum ratings for both VIN and VTS in Table 1. Added data to Table 3. Added
data to Table 5. Updated SSTL15 in Table 7. Updated VOCM and VOD values in Table 8. Added eFUSE
endurance Table 12. Added values to VMGTREFCLK and VIN in Table 13, page 11. Added values and
updated tables in the GTX Transceiver Specifications and GTH Transceiver Specifications sections.
Added Table 27 and Figure 4. Revised parameters and values in Table 39. Updated Table 40, page 23.
Added data to Table 41. Updated speed specification to v1.04 with appropriate changes to Table 42
and Table 43 including production release of the XC6VLX240T for -1 and -2 speed grades. Speed
specification changes and numerous updates also made to Table 44, and Table 49 through Table 71.
Added data to Table 73 and Table 74.
02/09/2010 2.2 Revised description of CIN in Table 3. Clarified values in Table 5. Fixed SDR LVDS unit error in
Table 41.
04/12/2010 2.3 Added note 3 and update value of n in Table 3. Clarified simultaneous power-down in Power-On Power
Supply Requirements. Updated external reference junction temperatures in Table 40, Analog-to-Digital
Specifications. Updated speed specification to v1.05 with appropriate changes to Table 42 and
Table 43 including production release of the XC6VLX130T for -1 and -2 speed grades. Fixed note 4 in
Table 48. Increased the -2 specification for FIDELAYCTRL_REF and clarified units for TIDELAYPAT_JIT in
Table 53. Added note 1 to Table 62.
05/11/2010 2.4 Updated FRXREC in Table 22. Revised FIDELAYCTRL_REF in Table 53. Removed TRCKO_PARITY_ECC:
Clock CLK to ECCPARITY in standard ECC mode row in Table 57. Added XC6VLX130T values to
Table 72.
05/26/2010 2.5 Added XC6VLX195T data to Table 5. Updated values in Table 22 including adding note 2 and note 3.
Updated speed specification to v1.06 with appropriate changes to Table 42 and Table 43 including
production release of the XC6VLX195T for -1 and -2 speed grades. Added XC6VLX195T values to
Table 72.
07/16/2010 2.6 Changed Table 42 and Table 43 to production status on the -3 speed grade XC6VLX130T,
XC6VLX195T, and XC6VLX240T devices. Added XC6VHX250Tdata to Table 4 and Table 72. Added
Note 6 to Table 64.
07/23/2010 2.7 Changed Table 42 and Table 43 to production status on the XC6VLX75T, XC6VLX365T, XC6VLX550T,
XC6VLX760, XC6VSX315T, and XC6VSX475T devices using ISE 12.2 software with speed
specification v1.08. Updated VCMOUTDC equation to MGTAVTT – DVPPOUT/4 in Table 17. Updated
some -3, -2, -1 specifications in Table 65 through Table 72. Added and updated -1L specifications to
Table 41 and for most switching characteristics tables.
07/30/2010 2.8 Changed Table 42 and Table 43 to production status on the -1L speed grade for the XC6VLX130T,
XC6VLX195T, XC6VLX240T, XC6VLX365T, and XC6VLX550T devices using ISE 12.2 software with
current speed specifications. Also updated the speed specifications for XC6VLX75T, XC6VLX550T,
and XC6VSX315T. Updated VCCINT specifications for -1L speed grade industrial temperature range
devices in Table 2.
09/20/2010 2.9 In Table 32, changed FGPLLMAX specification in -3 column from 5.951 to 5.591. In Table 40, changed
FMAX for the DCLK from 250 MHz to 80 MHz.
10/18/2010 2.10 The specification change in version 2.9, Table 40 is described in XCN10032, Virtex-6 FPGA: GTX
Transceiver User Guide, Family Data Sheet (SYSMON DCLK), and JTAG ID Changes
In this version (2.10), -1L(I) data is added to Table 4 and clarified in Note 2. Changed Table 42 and
Table 43 to production status on the -1L speed grade XC6VLX75T, XC6VLX760, XC6VSX315T, and
XC6VSX475T devices using ISE 12.3 software with current speed specifications. Revised the
XC6VLX760 -1L speed specification for TPHMMCMGC in Table 69 and TPHMMCMCC in Table 70.
01/17/2011 2.11 Changed in Table 42 and Table 43 to production status on the XC6VHX250T devices using ISE 12.4
software with current speed specifications.
Added industrial temperature range (Tj) recommended specifications to Table 2; including specific
ranges for the -2I XC6VSX475T, XC6VLX550T, XC6VLX760, and XC6VHX565Tdevices. Added
note 3 to Table 36 and maximum total jitter values. Added note 4 to Table 37 and maximum sinusoidal
jitter values. Added note 2 to Table 43. Revised FMAX descriptions in Table 57 and added note 12.
Added note 8 to FPFDMIN in Table 64.
The following revisions are due to specification changes as described in XCN11009, Virtex-6 FPGA:
Data Sheet, User Guides, and JTAG ID Updates.
In Table 59:Configuration Switching Characteristics, page 49, revised -1L specifications for TPOR,
FMCCK, FMCCKTOL, TSMCSCCK, TSMCCKW, FRBCCK, FTCK, FTCKB, TMCCKL, and TMCCKH. In Table 64:
MMCM Specification, added bandwidth settings to FPFDMIN and added note 1.


02/08/2011 2.12 Removed note 1 from Table 4 as the larger devices (XC6VLX550T, XC6VLX760, XC6VSX475T, and
XC6VHX565T) are now offered in -2I. Updated Table 4 and Table 5 with data for the XC6VHX380T in
the FF(G)1154 package. In Table 41, updated -1L specification for DDR3. Added Note 1 to Table 42.
Moved the XC6VHX380Tdevices in the FF(G)1154 package to production release in Table 43 using
ISE 12.4 software with current speed specifications. Updated description for FINDUTY in Table 64.
02/25/2011 3.0 Designated the data sheet as Preliminary for all devices not already labeled production in Table 42.
Changed the XC6VHX380T devices in all packages to production status in Table 42 and Table 43.
Removed note 1 from Table 42.
Added maximum specifications to Table 25. Updated THAVCC2HAVCCRX in Table 27. Updated the
typical values and notes in Table 28 and Table 29. Added values to Table 30 and Table 31. In Table 34,
added values for TLOCK and TPHASE. Updated the values in Table 36 and added note 3. Updated
Table 37 and added note 4.
03/21/2011 3.1 Updated Table 2 including Note 7. In Table 4, added Note 3 and -2E, extended temperature range to
the XC6VLX550T, XC6VLX760, XC6VSX475T, and XC6VHX380T devices, and added Note 5 for the
XC6VHX565T. Updated Table 28 typical values. Updated the description for FIDELAYCTRL_REF in
Table 53. Updated FMCCK in Table 59.
04/01/2011 3.2 Added Tj values for C, E, and I temperature ranges to Table 2. Updated the ICCQ values in Table 4.
Updated FGCLK in Table 34.
Designated the data sheet as Production for all devices not already labeled production in Table 42.
Changed the XC6VHX255T and XC6VHX565T devices in all packages to production status in Table 42
and Table 43. This included updates to the Virtex-6 Device Pin-to-Pin Output Parameter Guidelines
and Virtex-6 Device Pin-to-Pin Input Parameter Guidelines for these devices. Production speed
specifications for these devices are available using the speed specification v1.14 in the ISE 13.1
software update.
Updated and added package skew values to Table 72; these values are correct with regards to
previous production released speed specifications in software. Updated copyright page 1 and Notice
of Disclaimer.
12/08/2011 3.3 Production release of the Defense-grade XQ devices in Table 42 and Table 43 using ISE v13.3 v1.17
Patch for -2 and -1 speed specifications; and v1.10 for -1L speed specifications. Added the
XQ6VLX130T, XQ6VLX240T, XQ6VLX550T, XQ6VSX315T, and XQ6VSX475T to the data sheet
which included adding Table 45. Updated Tj in Table 2. In Table 40, updated Tj for most specifications
and added Note 4. Added Note 4 to Table 41. Added -1(XQ) speed specification columns only to
Table 50, Table 51, Table 52, and Table 58.
Updated VOD in Table 8, VOCM in Table 9, and VOCM and VDIFF in Table 10. Updated the Power-On
Power Supply Requirements section. In Table 27, updated maximum specification for
THAVCC2HAVCCRX and added Note 3. Updated Tj in Table 40. In Table 41, increased the DDR LVDS
receiver (SPI-4.2) -1 speed grade performance value from 1.0 Gb/s to 1.1 Gb/s. In Table 60, updated
the FMAX to add a separate row for the LX760 device values. The speed specifications in the software
tools have always matched these values for the LX760, the data sheet is now correct. Updated the
notes for TOUTJITTER in Table 64.
01/12/2012 3.4 Added the temperature range -2E to Note 5 in Table 4.
05/17/2013 3.5 Added the DIFF_SSTL15 I/O standard to Table 7. Added Note 1 to Table 18.
03/18/2014 3.6 Updated Note 8 in Table 64. Updated Notice of Disclaimer.

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Virtex-6 FPGA Data Sheet:

DC and Switching Characteristics

Virtex-6 FPGA Electrical Characteristics

Virtex-6 FPGA DC Characteristics

DS152 (v3.6) March 18, 2014 www.xilinx.com

Table 2: Recommended Operating Conditions

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Table 3: DC Characteristics Over Recommended Operating Conditions (1)(2)

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Table 4: Typical Quiescent Supply Current

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Table 4: Typical Quiescent Supply Current (Cont’d)

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Table 4: Typical Quiescent Supply Current (Cont’d)

Power-On Power Supply Requirements

DS152 (v3.6) March 18, 2014 www.xilinx.com

Table 5: Power-On Current for Virtex-6 Devices

Table 6: Power Supply Ramp Time

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SelectIO™ DC Input and Output Levels

Table 7: SelectIO DC Input and Output Levels

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LVDS DC Specifications (LVDS_25)

Extended LVDS DC Specifications (LVDSEXT_25)

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LVPECL DC Specifications (LVPECL_25)

Table 11: LVPECL DC Specifications

eFUSE Read Endurance

Table 12: eFUSE Read Endurance

DS152 (v3.6) March 18, 2014 www.xilinx.com

GTX Transceiver Specifications

Table 14: Recommended Operating Conditions for GTX Transceivers(1)(2)

Table 15: GTX Transceiver Supply Current (per Lane) (1)(2)

DS152 (v3.6) March 18, 2014 www.xilinx.com

GTX Transceiver DC Input and Output Levels

Table 17: GTX Transceiver DC Specifications

X-Ref Target - Figure 1

Figure 1: Single-Ended Peak-to-Peak Voltage

DS152 (v3.6) March 18, 2014 www.xilinx.com

X-Ref Target - Figure 2

Figure 2: Differential Peak-to-Peak Voltage

Table 18: GTX Transceiver Clock DC Input Level Specification

GTX Transceiver Switching Characteristics

Table 19: GTX Transceiver Performance

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Table 21: GTX Transceiver Reference Clock Switching Characteristics

X-Ref Target - Figure 3

Figure 3: Reference Clock Timing Parameters

Table 22: GTX Transceiver User Clock Switching Characteristics(1)

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Table 23: GTX Transceiver Transmitter Switching Characteristics

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Table 24: GTX Transceiver Receiver Switching Characteristics

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GTH Transceiver Specifications

Table 26: Recommended Operating Conditions for GTH Transceivers (1)(2)

Table 27: GTH Transceiver Power Supply Sequencing (1)(2)(3)

DS152 (v3.6) March 18, 2014 www.xilinx.com

Figure 4 shows the timing parameters in Table 27.