Name: IITA J.

S Student Number: 214047547

Bench Number: A4 Group: 35BELL

ELECTRONICS 2 LABORATORY ASSIGNMENT 1

MARKS OBTAINED:
Neatness (5)
Table 2 (8)
Table 3 (7)
Calculations (5) MODERATOR SIGNATURE
Penalties (-x)
Total marks [25] Total %

OBJECTIVE:
Investigate the operation of a series regulator with discrete input voltages.

EQUIPMENT AND COMPONENTS NEEDED:

1 x Variable DC power supply 3 x BNC to crocodile cables 1 x BZX83C6V8 Zener diode 2 x 10 kΩ Resistors
1 x Signal generator 3 x Banana to banana cables 1 x LM741 Op-amp
2 x Multimeters 3 x Banana to crocodile cables 1 x 5 kΩ Variable resistor
1 x Breadboard 1 x BC109 Transistors 1 x 1 kΩ Resistor

PROCEDURE:
1. Construct the circuit:

Vce(Q1)

+ _ +
+ _
Q1

BC109

_ +
R1

1k

1 5
10k
R2

Vref +
3
LM741
6
+ -
E 2 IC1
VL
RL

13 V to 18 V
5k
BZX83C6V8
D1

10k
R3

Vs Vb

L1-1-11
_

Connect the LM741's power terminals, -Vs and +Vs, to

ground and the positive voltage of VIN respectively.

741 0PERATIONAL AMPLIFIER: PIN CONNECTIONS

OFFSET NULL 1 8 NO CONNECTION

INVERTING INPUT 2 7 +Vs

741
NON-INVERTING INPUT 3 6 OUTPUT

-Vs 4 5 OFFSET NULL

497596959.doc Page 1 of 37 03 November 2020

2. Complete the table with RL = 4 k:
CALCULATED MEASURED
E/V
VL/V Vb/V VCE(Q1)/V Vs/V VL/V Vb/V VCE(Q1)/V Vs/V

13 11,7 12,4 1,3 5,85 11,60 12,26 1,30 5,79

14 12,7 13,4 1,3 6,35 12,65 13,32 1,30 6,31

15 13,6 14,3 1,4 6,8 13,62 14,29 1,31 6,80

16 13,6 14,3 2,4 6,8 13,71 14,38 2,12 6,85

17 13,6 14,3 3,4 6,8 13,73 14,39 3 6,86

18 13,6 14,3 4,4 6,8 13,74 14,40 3,97 6,86

Note 
VCE _ L1-2-13
If the original calculated Vb is higher than E, which is not possible, Vb must be +
+ _

VBC VBE
calculated using a different formula. To calculate Vb you need to calculate VL (reverse) _ + (foward)

where VL = E - VCEQ1 and VCEQ1 = VBEQ1  VBCQ1 with VBCQ1  - 0,6 V.

VCE = VBE - VBC
(where VBC is negative)

Note ‚ If the original calculated Vb is lower than E, Vb must be calculated normaly.

CALCULATED MEASURED

VZ/V 6,8 6,86

3. Complete the table with VIN= 16 V:

Calculated Measured
RL/kΩ
VL/V Vb/V VCE(Q1)/V Vs/V VL/V Vb/V VCE(Q1)/V Vs/V

4 13,6 14,3 2,4 6,8 13,72 14,39 2,09 6,85

3 13,6 14,3 2,4 6,8 13,72 14.39 2,09 6,85

2 13,6 14,3 2,4 6,8 13,72 14,40 2,10 6,85

1 13,6 14,3 2,4 6,8 13,72 14,40 2,10 6,86

497596959.doc Page 2 of 37 03 November 2020

CALCULATIONS

Calculate Vb then compare it with E.

 R 
VL   1  2   VZ
 R3 
 10  103 
 1   6,8
 10  103 
 
 13,6 V

Vb  VBE  VL
 0,7  13,6
 14,3 V

When Vb  E i.e. where E = 13 V and 14 V

Calculate all the unknowns with E = 13 V:

 VL  E  VCEQ1
 13  1,3
 11,7 V

Vb  VBEQ1  VL
 0,7  11,7
 12, 4 V

VCE  VBE  VBC

Q1 Q1 Q1
 0,7   0,6 
 1,3 V

 R3 
Vs     VL
 R 2  R3 
 10  103 
   11,7
 10  103  10  103 
 
 5,85 V

But when Vb  E i.e. where E = 15 V to 18 V

 R 
VL   1  2   VZ
 R3 
 10  103 
 1   6,8
 10  103 
 
 13,6 V

Vb  VBEQ1  VL
 0,7  13,6
 14,3 V

497596959.doc Page 3 of 37 03 November 2020

Name: IITA J.S Student Number: 214047547

Bench Number: A4 Group: 35BELL

ELECTRONICS 2 LABORATORY ASSIGNMENT 2

MARKS OBTAINED:
Neatness (4)
Graph 3 (5)
Graph 4 (2)
Calculations (4) MODERATOR SIGNATURE
Penalties (-x)
Total marks [15] Total %

OBJECTIVE:
Investigate the operation of a series regulator with a filtered halve wave rectifier as an input.

EQUIPMENT AND COMPONENTS NEEDED:

1 x Variable AC power supply 3 x BNC to crocodile cables 1 x BZX83C6V8 Zener diode 1 x 18 Ω Resistor
1 x Signal generator 3 x Banana to banana cables 1 x LM741 Op-amp 1 x 1 kΩ Resistor
2 x Multimeters 3 x Banana to crocodile cables 1 x 1 kΩ Variable resistor 2 x 10 kΩ Resistors
1 x Breadboard 1 x BC109 Transistors 1 x 5 kΩ Variable resistor

PROCEDURE:
1. Construct the circuit:

Vce(Q1)
D2

1N4007 BC109
Q1
R1

1k

1 5
+ 10k
3
R2

*
LM741
6
100u

E Vin **
C1

-
19 V Ch 1 2 IC1
VL
RL
Ch 2
1k
BZX83C6V8
D1

10k
R3

L2-1-11

* Connect the LM741’s power terminals, -Vs and +Vs to ground and the positive terminal of C1 respectively.
** Vin is the regulator’s input voltage.

741 0PERATIONAL AMPLIFIER: PIN CONNECTIONS

OFFSET NULL 1 8 NO CONNECTION

INVERTING INPUT 2 7 +Vs

741
NON-INVERTING INPUT 3 6 OUTPUT

-Vs 4 5 OFFSET NULL

2. Complete the table:

REGULATOR CIRCUIT
E(p)/V Vin(min)/V
Vin(p)/V Vin(r)(pp)/V
(Minimum voltage that may be supplied to the regulator.)

26,87 26,17 5,19 20,98

Note 1
The load of the rectifier, RL(rectifier), must be approximated as the series resistances of R1 and ZZT of D1. This resistance
must be used as the load resistance in the Vr(pp) calculation.

497596959.doc Page 4 of 37 03 November 2020

3. Draw Vin, VL and Vce(Q1) versus time to the same scale:

30
50

4. Draw only the AC component of VL versus time on the same time scale as the graph above.

30
20

30
20

497596959.doc Page 5 of 37 03 November 2020

CALCULATIONS

Ep  ERMS 2
 19 2
 26,87 V

Vinp  Ep  VF D2 
 26,87  0,7
 26,17 V

RL  R1  Z ZT  D1 (Z ZT  D1 from datasheet) See note 1

rectifier

 1 103  8
 1,008  103 
 1,008 k

Vin
p
Vin 
r(pp) fRL C
rectifier 
26,17


50  1008  100  10 6 
 5,19 V

Vin  Vin  Vin

min p r(pp)

 26,17  5,19
 20,98 V

497596959.doc Page 6 of 37 03 November 2020

Name: IITA J.S Student Number: 214047547

Bench Number: A4 Group: 35BELL

ELECTRONICS 2 LABORATORY ASSIGNMENT 3

MARKS OBTAINED:
Neatness (3)
Table 2 (3)
Answer 3 (3)
Calculation (1) MODERATOR SIGNATURE
Penalties (-x)
Total marks [10] Total %

OBJECTIVE:
Investigate the operation of a summing amplifier.

EQUIPMENT AND COMPONENTS NEEDED:

2 x Variable DC power supplies 1 x Breadboard 1 x 1 kΩ Resistors
1 x Signal generator 3 x Banana to crocodile cables 1 x 2 kΩ Resistors
1 x Oscilloscope 3 x Banana to Banana cables 1 x 3 kΩ Resistor
2 x Multimeters 3 x BNC to crocodile cables 1 x LM741 Op-amp

PROCEDURE:
1. Construct the circuit:

R3
741 0PERATIONAL AMPLIFIER: PIN CONNECTIONS

R1 1k
V1 OFFSET NULL 1 8 NO CONNECTION
2k 2 IC1
-
6 INVERTING INPUT 2 7 +Vs
R2 LM741 VO 741
3
V2 + NON-INVERTING INPUT 3 6 OUTPUT
3k 1 5
-Vs 4 5 OFFSET NULL
L3-1-11
NC NC

The supply voltage to the op-amp is ±15 V

2. Apply the input voltages as shown and complete the table:

VO/V
V1/V V2/V
CALCULATED MEASURED
+2 -3 0 -0,01

+2 -2 -0,33 -0,32

+2 -1 -0,67 -0,65

+2 +1 -1,33 -1,29

+2 +2 -1,67 -1,61

+2 +3 -2 -1,95

3. Write in words exactly what this circuit is doing.

The circuit is adding the half of V1 with the third of V2.

497596959.doc Page 7 of 37 03 November 2020

CALCULATIONS

R R 
Vo    f  V1  f  V2 
R
 1 R 2 
 1 103 1 103 
  2   3  
 2  103 3  10 3 
 
1 1 
    2    3  
2 3 
0 V

497596959.doc Page 8 of 37 03 November 2020

Name: IITA J.S Student Number: 214047547

Bench Number: A4 Group: 35BELL

ELECTRONICS 2 LABORATORY ASSIGNMENT 4

MARKS OBTAINED:
Neatness (3)
Table 2 (3)
Answer 3 (3)
Calculation (1) MODERATOR SIGNATURE
Penalties (-x)
Total marks [10] Total %

OBJECTIVE:
Investigate the operation of an averaging amplifier.

EQUIPMENT AND COMPONENTS NEEDED:

2 x Variable DC power supplies 1 x Breadboard 1 x 1 kΩ Resistors
1 x Signal generator 3 x Banana to crocodile cables 2 x 2 kΩ Resistors
1 x Oscilloscope 3 x Banana to Banana cables 1 x LM741 Op-amp
2 x Multimeters 3 x BNC to crocodile cables 1 x Light dependent resistor (LDR)

PROCEDURE:
1. Construct the circuit:

R3
741 0PERATIONAL AMPLIFIER: PIN CONNECTIONS

R1 1k
V1 OFFSET NULL 1 8 NO CONNECTION
2k 2 IC1
-
6 INVERTING INPUT 2 7 +Vs
R2 LM741 VO 741
3
V2 + NON-INVERTING INPUT 3 6 OUTPUT
2k 1 5
-Vs 4 5 OFFSET NULL
NC NC L4-1-11

The supply voltage to the op-amp is ±15 V

2. Apply the input voltages as shown and complete the table:

VO/V
V1/V V2/V
CALCULATED MEASURED

+5 -5 0 0,08

+5 -3 -1 -0,93

+5 -1 -2 -1,96

+5 +4 -4,5 -4,40

+5 +5 -5 -4,90

+5 +6 -5,5 -5,41

3. Show, using a formula, that the output is the average of the two inputs.

 V  V2 
Vo    1 
 2 

497596959.doc Page 9 of 37 03 November 2020

CALCULATIONS

R R 
Vo    f  V1  F  V2 
 R1 R2 
R1  R2
R
  f   V1  V2 
R1

 RF ishalf of R1
 V  V2 
 Vo    1 
 2 
 5  ( 5) 
  
 2 
 0 V

497596959.doc Page 10 of 37 03 November 2020

Name: IITA J.S Student Number: 214047547

Bench Number: A4 Group: 35BELL

ELECTRONICS 2 LABORATORY ASSIGNMENT 5

MARKS OBTAINED:
Neatness (5)
Table 2 (4)
Table 3 (2)
Calculations (4) MODERATOR SIGNATURE
Penalties (-x)
Total marks [25] Total %

OBJECTIVE:
Investigate the operation of a comparator.

EQUIPMENT AND COMPONENTS NEEDED:

2 x Variable DC power supplies 1 x Breadboard 2 x 1 kΩ Resistors 1 x Light dependent resistor (LDR)
1 x Signal generator 3 x Banana to crocodile cables 1 x 10 kΩ Resistor
1 x Oscilloscope 3 x Banana to Banana cables 1 x 22 kΩ Trimmer
2 x Multimeters 3 x BNC to crocodile cables 1 x LM741 Op-amp

PROCEDURE:
1. Construct the circuit:
+15 V
R1

22k

R3

1k

2 IC1 741 0PERATIONAL AMPLIFIER: PIN CONNECTIONS

-
6
LM741 VO
3 OFFSET NULL 1 8 NO CONNECTION
+
1 5
INVERTING INPUT 2 7 +Vs
VA VB 741
10k
R2

R4

1k

NC NC NON-INVERTING INPUT 3 6 OUTPUT

-Vs 4 5 OFFSET NULL

L5-1-11

The supply voltage to the op-amp is ±15 V

2. Adjust R1 as shown and complete the table:

CALCULATED Vo/V
R1/kΩ
VA/V VB/V CALCULATED MEASURED

2 12,5 -15 -12,89

5 10 -15 -12,88

10 7,5 -15 -12,83

7,5
15 6 15 14,41

20 5 15 14,41

22 4,69 15 14,41

3. Replace R1 with the light dependent resistor (LDR) and complete the table.
LDR STATUS Vo/V (MEASURED)

Expose to light -12,88

Dark (cover the LDR) 14,41

497596959.doc Page 11 of 37 03 November 2020

CALCULATIONS

 R2 
VA     VCC
 R1  R2 
 10  103 
  3   15
3 
 2  10  10  10 
 12,5 V

 R4 
VB     VCC
 R3  R 4 
 1 103 
  3   15
3
 1 10  1  10 
 7,5 V

If VA  VB then Vo = -15 V

If VA  VB then Vo = +15 V

497596959.doc Page 12 of 37 03 November 2020

Name: IITA J.S Student Number: 214047547

Bench Number: A4 Group: 35BELL

ELECTRONICS 2 LABORATORY ASSIGNMENT 6

MARKS OBTAINED:
Neatness (3)
Table 3 (3)
Graph 4 (6)
Graph 5 (6)
Answer 6 (4)
Answer 6.1 (2)
Answer 6.2 (2)
Calculations (4) MODERATOR SIGNATURE
Penalties (-x)
Total marks [30] Total %

OBJECTIVE:
Investigate the operation of an operational amplifier used as a differentiator.

EQUIPMENT AND COMPONENTS NEEDED:

1 x Variable DC power supply 1 x Breadboard 1 x 2,2 k Resistors
1 x Signal generator 3 x Banana to crocodile cables 1 x 22 k Resistor
1 x Oscilloscope 3 x Banana to Banana cables 1 x 4,7 nF capacitor
2 x Multimeters 3 x BNC to crocodile cables 1 x LM741 op-amp

PROCEDURE:
1. Construct the circuit:

RF
741 0PERATIONAL AMPLIFIER: PIN CONNECTIONS
22k

R1 C1
2 IC1 OFFSET NULL 1 8 NO CONNECTION
-
2k2 4n7 6
LM741 Vo INVERTING INPUT 2 7 +Vs
3 741
V1(pp) +
1V 1 5 NON-INVERTING INPUT 3 6 OUTPUT
400 Hz to 30 kHz
-Vs 4 5 OFFSET NULL
L6-1-11

The supply voltage to the op-amp is ±15 V

2. Adjust the input voltage to a triangular wave.

3. Change the input frequency as shown on the table and record the readings.
Vo(p)/V
% ERROR/%
fV(1)/Hz
(From measured to calculated)
CALCULATED MEASURED

400 -0,083 -0,08 3,75 %

3
1 X 10 -0,207 -0,20 3,5 %

30 X 103 -6,082 -4 52,05 %

497596959.doc Page 13 of 37 03 November 2020

4. Draw both V1 and Vo at 400 Hz.

Expected Observed
30 30
30 30

5. Draw both V1 and Vo at 30 kHz.

Expected Observed
30 30
30 30

6. Why did the output signal’s shape change with an increasing frequency?

1
 An increase in frequency will cause the reactance of the capacitor denoted by XC  to decrease.
2 fC
 R1 is there for the compensation of output’s offset voltage.
 In the case where the reactance of the capacitor is equal to the feedback resistance, differentiation will stop.

1
 When differentiation has stopped the circuit will operate in the cut-off frequency denoted by fC 
2 RC

6.1 Why is the output similar to an inverting amplifier’s output when the input frequency is 30 kHz?

1 1
XC    1,13 k 

2 f C 2  30  103 4,7  10  9 
R1  2,2 k 

R1 is the effective input part in the circuit therefore it will cause the output to be similar to an inverting amplifier’s output.

6.2 Why did the output signal’s amplitude increase as the frequency increases?

An increase in frequency has decreased the impedance of the two component therefore increasing the output signal.
i.e;

R 
Vo    f   V1
 R1 

497596959.doc Page 14 of 37 03 November 2020

CALCULATIONS

For f = 400 Hz

VC  V1 p   V1 p 

 0,5   0,5 
1 V

 1
t     V1 p 
f
 1 
   0,5
 400 
 1,25  103 s
 1,25 ms

 V 
Vo  RC  1  Where V1  VC
 t 

 
  22  103  4,7  10 9  
1 
3 
 1,25  10 
 82,7  10 3
 82,7 mV

VO Calculated  VO Measured

% error   100%
VO Measured
0,083   0,08 
  100%
0,08
 3,75 %

497596959.doc Page 15 of 37 03 November 2020

Name: IITA J.S Student Number: 2145047547

Bench Number: A4 Group: 35BELL

ELECTRONICS 2 LABORATORY ASSIGNMENT 7

MARKS OBTAINED:
Neatness (3)
Table 3 (3)
Graph 4 (6)
Graph 5 (6)
Answer 6 (4)
Answer 6.1 (2)
Answer 6.2 (2)
Calculations (4) MODERATOR SIGNATURE
Penalties (-x)
Total marks [30] Total %

OBJECTIVE:
Investigate the operation of an operational amplifier used as an integrator.

EQUIPMENT AND COMPONENTS NEEDED:

1 x Variable DC power supply 1 x Breadboard 2 x 10 k Resistors
1 x Signal generator 3 x Banana to crocodile cables 1 x 100 k Resistor
1 x Oscilloscope 3 x Banana to Banana cables 1 x 2.2 nF capacitor
2 x Multimeters 3 x BNC to crocodile cables 1 x LM741 op-amp

PROCEDURE:
1. Construct the circuit:

RF

100k
CF
741 0PERATIONAL AMPLIFIER: PIN CONNECTIONS
2n2
R1
2 IC1 OFFSET NULL 1 8 NO CONNECTION
-
10k 6
LM741 Vo INVERTING INPUT 2 7 +Vs
3 741
+
1 5 NON-INVERTING INPUT 3 6 OUTPUT
V1(pp)
10k
R2

1V
100 Hz to 10 kHz -Vs 4 5 OFFSET NULL
L7-1-11

The supply voltage to the op-amp is ±15 V

2. Adjust the input voltage to a square wave.

3. Change the input frequency as shown on the table and record the readings.
Vo(pp)/V
% ERROR/%
fV(1)/Hz
(From measured to calculated)
CALCULATED MEASURED

10 X 103 -1,136 -1 13,6 %

4 X 103 -2,841 -2,8 1,46 %

100 -113,64 -10,5 1031 %

497596959.doc Page 16 of 37 03 November 2020

4. Draw both V1 and Vo at 10 kHz.

Expected Observed
30 30
30 30

5. Draw both V1 and Vo at 100 Hz.

Expected Observed
30 30
30 30

6. Why did the output signal’s shape change with a decreasing frequency?

1
 As the frequency decreases, the reactance of the feedback capacitor defined XCf  will increase.
2 fCf
 R2 is there for the compensation of the offset output voltage (Vo)

 When the reactance of the feedback capacitor is equal to the feedback resistance when the frequency is decreasing,
integration action will stop.

1
 If the integration action has stopped the circuit will operate in the cut-off frequency denoted by fC 
2 R f Cf

6.1 Why is the output similar to an inverting amplifier’s output when the input frequency is 100 Hz?
1 1
XC    72 3 k 

2 f C 2  10 0  2,2  10  9 
R f  100 k 

Rf is the effective feedback part therefore it will cause the output to be similar to an inverting amplifier.

6.2 Why did the output signal’s amplitude increase as the frequency decreases?

A decrease in frequency will cause an increase in reactance of capacitor therefore the output signal
i.e ;

R 
Vo    f   V1
 R1 

497596959.doc Page 17 of 37 03 November 2020

CALCULATIONS

For 10 kHz:

V1 p p 
V1 
2
1

2
 0,5 V

 1
t     V1
f
 1 
   0,5
 10  103 
 50  10 6 s
 50  s

  V  t 
Vo   1 
 RC 
 0,5  50  106 
 
 10  103  2,2  10 9 
 
 1,136 V

Vo calculated  Vo measured

% error   100%
Vo measured
1,136  ( 1)
  100%
1
 13,6 %

497596959.doc Page 18 of 37 03 November 2020

Name: IITA J.S Student Number: 214047547

Bench Number: A4 Group: 35BELL

ELECTRONICS 2 LABORATORY ASSIGNMENT 8

MARKS OBTAINED:
Neatness (5)
Table 2 (6)
Table 3 (3)
Table 4 (3)
Graph 5 (12)
Calculations (21) MODERATOR SIGNATURE
Penalties (-x)
Total marks [50] Total %

OBJECTIVE:
To obtain the DC and AC parameters of a two-stage amplifier.

EQUIPMENT AND COMPONENTS NEEDED:

1 x Variable DC power supply 1 x Breadboard 2 x 2N2222A Transistors 1 x 10 kΩ Resistors
1 x Signal generator 3 x BNC to crocodile cables 2 x 220 Ω Resistors 2 x 18 kΩ Resistors
1 x Oscilloscope 3 x Banana-to-Banana cables 2 x 1,8 kΩ Resistors 2 x 56 kΩ Resistors
2 x Multimeters 3 x Banana to crocodile cables 2 x 5,6 kΩ Resistors 2 x 1F Capacitors
3 x 10 F Capacitors

PROCEDURE.
1. Construct the circuit:

+
+15 V L8-1-12
56k

5k6

56k

5k6
R3

R6

R8
R1

C2 C3

Q1 Q2
C1 10u 10u

10u
2N2222 2N2222
RS

220R

220R
18k

18k

10k
R4

R7

R9
R2

RL

Es(pp)
15 mV
R10
1k8

1k8
R5

1 kHz
10u

10u
C5
C4

Note: The value of the internal resistance of the source (RS) must be read from the function generator, just above the output
terminal.

MEASURED Q1 Q2

VBE 0,61 0,61

βDC 227 205

497596959.doc Page 19 of 37 03 November 2020

2. With the function generator off, calculate/measure the DC voltages and currents and complete the table:
CALCULATED MEASURED
DC PARAMETER
STAGE 1 STAGE 2 STAGE 1 STAGE 2

VB/V 3,65 3,65 3,49 3,52

VR1, 6/V 11,35 11,35 11,48 11,45

VE/V 3,04 3,04 2,89 2,92

VC/V 6,94 6,94 7,01 6,88

VCE/V 4,03 4,03 4,13 3,96

IE/mA 1,50 1,50 1,44 1,45

IC/mA 1,50 1,50 1,44 1,45

3. Calculate the ac parameters and complete the table using the measured values of VBE and βDC:
AC PARAMETER CALCULATED FOR STAGE 1 CALCULATED FOR STAGE 2

re/Ω 17,33 17,33

Zi/Ω 11,07×103 10,65×103

Zo/Ω 5,6×103 5,6×103

A VNL -25,45 -25,45

Total A VLS = A VT
263,74
(for both amps)

4. With the function generator on, measure the input/output voltages and complete the table:
PARAMETER MEASURED FOR STAGE 1 MEASURED FOR STAGE 2

Es(pp)/V 15×10-3 -0,36 See note 2

Vi(pp)/V 15×10-3 -0,36

See note 4
Vo(pp)/V - 0,36 5,4

VL(pp)/V -0,24 3,5

A VNL 0 0

A VS -24 -15

A VL 0 0

A VLS -16 -9,7

Total A VLS = A VT
155,2
(for both amps)
Note 1: To measure ES(pp) of stage 1 make sure that stage 1’s amplifier is disconnected form the function generator.
Note 2: To measure ES(pp) of stage 2 make sure that stage 2’s amplifier is disconnected form stage 1’s amplifier.
Note 3: To measure Vo(pp) of stage 1 make sure that stage 1’s amplifier is disconnected form stage 2’s amplifier.
Note 4: To measure Vo(pp) of stage 2 make sure that stage 2’s amplifier is disconnected form the load resistor.

5. Plot the input and output signals:

497596959.doc Page 20 of 37 03 November 2020

 EXPECTED OBSERVED
ES1 Vi1 ES1 Vi1
30 30 30 30
40 40 40 40

VL1 Vo1 VL1 Vo1

30 30 30 30
40 40 40 40

ES2 Vi2 ES2 Vi2

30 30 30 30
40 40 40 40

VL2 Vo2 VL2 Vo2

30 30 30 30
40 40 40 40

497596959.doc Page 21 of 37 03 November 2020

CALCULATIONS (Use the two-port model to calculate the effect of the load and source.)

For Stage 1
Œ
 ŒREŒ   Œ  R 4  R5   227(220  1,8  103 )  458,54  103  458,58 k Use measured DC ( hfe ) of Q1  227
Although ŒREŒ  10R2;Exact method is used
3 3
10R2  10(18  10 )  180  10   180 k
3 3
R1  R2 56  10  18  10
RThŒ  R1 R2    13,62 k
R1  R2 56  103  18  103
 R2   18  103 
EThŒ     15    15  3,65 V
 R1  R2   56  10  18  10 
3 3
 
EThŒ  VBEQ 3,65  0,61
IBŒ  1
  6,6  10 6  6,6  A Use measured VBE of Q1  0,61
RThŒ     1 REŒ 
13,62   227  1 220  1,8  10 3

ICŒ   IBŒ  227  6,6  10 6  1,50  10 3  1,50 mA IC  IE
Œ Œ
3 3
26  10 26  10
reŒ    17,33 
IEŒ 1,50  103
ZitŒ  re     1 R 4   227  17,33    228   220  59,09  103  59,09 k
Œ
1 1
ZiŒ  ZitŒ R1 R2    11,07  103  11,07 k
1 1 1 1 1 1
   
ZitŒ R1 R2 59  103 56  103 18  103
ZoŒ  R3  5,6 k

R3 5,6  103
A vNLŒ     25,45
R4 220
 Zi   11,07  103 
A v sŒ     A vNLŒ     25, 45   25,34
 RS  Zi   50  11,07  103 
 
For Stage 2
‚
 ‚ RE‚   ‚  R9  R10   207(220  1,8  103 )  414,1 103  414,1 k Use measured DC (  hfe ) of Q2  205

10R7  10(18  103 )  180  103   180 k Although  ‚ RE‚  10R 2;Exact method is used

R 6  R7 56  103  18  103
RTh‚  R6 / / R7    13,62 k
R 6  R7 56  103  18  103
 R7   18  103 
ETh‚     15    15  3,65 V
 R6  R7   56  103  18  103 
 
ETh  VBEQ 3,65  0,61
IB‚  ‚ 1
  7,31 A Use measured VBE of Q2  0,61 V
RTh     1 RE
‚ ‚ 
13,62   205  1 220  1,8  103 
IC‚   IB  205  7,31 106  1,50 mA IC‚  IE‚
‚

26  103 26  10 3
re‚    17,33 
IE 1,50  103
‚
Zit‚  re     1 R9   205  17,33    206   220  48,87 k
‚
1 1
Zi‚  Zi  Zit / / R1 / / R2    10,65  103  10,65 k
‚ ‚ 1 1 1 1 1 1
   
Z it ‚ R1 R2 48,87  103 56  103 18  103
Zo‚  R8  5,6 k

R 5,6  103
A vNL‚   8   25,45
R9 220
 Zi   10,65  103 
A Vs‚   ‚   Av     25,45   25,33
 R S  Zi  NL‚  50  10,65  103 
 ‚   

497596959.doc Page 22 of 37 03 November 2020

Name: IITA J.S Student Number: 214047547

Bench Number: A4 Group: 35BELL

ELECTRONICS 2 LABORATORY ASSIGNMENT 9

MARKS OBTAINED:
Neatness (5)
Graph 3 (5) MODERATOR SIGNATURE
Penalties (-x)
Total marks [10] Total %

OBJECTIVE:
Investigate the operation of class B push-pull amplifier.

EQUIPMENT AND COMPONENTS NEEDED:

1 x Variable DC power supply 2 x Multimeters 3 x Banana to Banana cables 2 x 10 kΩ Resistor
1 x Signal generator 1 x Breadboard 3 x BNC to crocodile cables 2 x 1N4007 Diodes
1 x Oscilloscope 3 x Banana to crocodile cables 1 x 1 kΩ Resistor 1 x BC327Transistor
1 x BC337Transistor

PROCEDURE:
1. Construct the circuit:

+9 V L9-1-11

Q1

BC337

Q3
Vin(pp)
9V
RL

1k
2 kHz
BC327

-9 V

2. Set the Vin(pp) to 9 V at 2 kHz.

3. Plot one and a half cycles of the input and output waveforms. Note the amplitude difference between the input voltage and the
output voltage as well as the crossover distortion.

Expected Observed
50 50
40 40

4. How much is the voltage gain of the amplifier?

Vo( pp )
AV 
Vin( pp )
7,8

9
 0,867
1

497596959.doc Page 23 of 37 03 November 2020

Name: IITA J.S Student Number: 214047547

Bench Number: A4 Group: 35BELL

ELECTRONICS 2 LABORATORY ASSIGNMENT 10

MARKS OBTAINED:
Neatness (5)
Table 2 (3)
Table 3 (3)
Table 4 (6)
Graph 5 (3)
Calculations (5) MODERATOR SIGNATURE
Penalties (-x)
Total marks [25] Total %

OBJECTIVE:
Investigate the operation of class AB push-pull amplifier.

EQUIPMENT AND COMPONENTS NEEDED:

1 x Variable DC power supply 2 x Multimeters 3 x Banana to Banana cables 2 x 10 kΩ Resistor
1 x Signal generator 1 x Breadboard 3 x BNC to crocodile cables 2 x 1N4007 Diodes
1 x Oscilloscope 3 x Banana to crocodile cables 1 x 1 kΩ Resistor 1 x BC327Transistor
1 x BC337Transistor
PROCEDURE:
1. Construct the circuit:

+9 V
10k
R1

Q1
1N4007

BC337
D1
1N4007

Vin(pp)
D2

9V
RL

BC327
1k

2 kHz
10k
R2

Q2

L10-1-11
-9 V

2. Complete the table for the DC parameters. The function generator must be switched off:
DC PARAMETER CALCULATED MEASURED

VE/V 0 9,7×10-3

VB1/V 0,7 0,59

VB2/V -0,7 -0,57

VCEQ1/V 9 8,93

VCEQ2/V -9 -8.95

497596959.doc Page 24 of 37 03 November 2020

3. With the function generator switched on, determine the maximum efficiency of the cct. (Vin(p) equal to the maximum.)
AC PARAMETER CALCULATED MEASURED

Vout(p)/V 9 8,5

Iout(p)/mA 9 8,5

Pout(max)/mW 40,5 36,13

PDC(max)/mW 51,57 48,7

Av 1 0,94

ηmax/% 78,53 % 74,19 %

4. With the function generator switched on, determine the efficiency with Vin(p) = 4,5 V.
AC PARAMETER CALCULATED MEASURED

Vout(p)/V 4,5 4,4

Iout(p)/mA 4,5 4,4

Pout/mW 10,13 9,68

PDC/mW 25,78 25,21

Av 1 0,98

η/% 39,29 % 38,4 %

NB: When the peak input voltage is only half of the maximum peak input voltage, the
efficiency is only half of the maximum efficiency. The maximum peak input voltage for
this a class AB push-pull amplifier is equal to VCC - (-VCC).

5. Plot the input and output waveforms observed on the oscilloscope for the table in point 4 above.

Expected Observed
50 50
40 40

497596959.doc Page 25 of 37 03 November 2020

CALCULATIONS

For Vinp  9 V

VL  Vin @ max.
p p

9 V

VLp
ILp 
RL
9

1 103
 9  103
 9 mA

VL 2 rms 
PL 
max RL
2
 9 
 

2
1 103
 40,5  10 3
 40,5 mW

2IL  p 
PDCmax  VCEQ 

 VCE
Q
 VCC 
 9

2 9  103 

 51,57  103
 51,57 mW

VLp
AV 
Vin
p

9

9
1

PLmax
% max   100%
PDCmax

40,5  10 3
  100%
51,57  103
 78,53 %

497596959.doc Page 26 of 37 03 November 2020

Name: IITA J.S Student Number: 214047547

Bench Number: A4 Group: 35BELL

ELECTRONICS 2 LABORATORY ASSIGNMENT 11

MARKS OBTAINED:
Neatness (3)
Table 2 (8)
Graph 3 (5)
Table 4 (3)
Calculations (1) MODERATOR SIGNATURE
Penalties (-x)
Total marks [20] Total %

OBJECTIVE:
To obtain the transfer and output characteristics of a JFET.

EQUIPMENT AND COMPONENTS NEEDED:

1 x Variable DC power supply 1 x Breadboard 1 x 220 Ω Resistor
1 x Signal generator 3 x Banana to crocodile cables 1 x 22 kΩ Resistor
1 x Oscilloscope 3 x Banana to Banana cables 1 x BF245 JFET
2 x Multimeters 3 x BNC to crocodile cables

PROCEDURE:
1. Construct the circuit:

220R
RD

Q1
RG VDD

22k BF245

VGG

L11-1-12

2. Adjust VDD to obtain values of VDS from 0 V to +20 V as indicated in the table and measure VRD. Then calculate ID. Record
these values in the table. (VGG = VGS)
NOTE 2
VGG = VGS/V YOUR
0 -1 -2 -3 -4 VGS  4, 4V
VGS(off )

VRD/V ID/mA VRD/V ID/mA VRD/ V ID/ µA VRD/ mV ID/ µA VRD/ mV ID/ µA VRD/ mV ID/ nA
VDS/V

1 0,96 4,36 0,56 2,55 0,15 681,8 0 0 0 0 0 0

2 1,41 6,41 0,74 3,36 0,17 772,7 0 0 0 0 0 0

3 1,56 7,09 0,78 3,55 0,17 772,7 0 0 0 0 0 0

4 1,62 7,36 0,80 3,64 0,18 818,2 0,1 0,45 0,1 0,45 0 0

7 1,66 7,55 0,82 3,73 0,19 863,6 0,1 0,45 0,1 0,45 0,1 454,5

10 1,66 7,55 0,83 3,77 0,19 863,6 0,2 0,91 0,2 0,91 0,1 454,1

15 1,63 7,41 0,84 3,82 0,20 909,1 0,3 1,36 0,3 1,36 0,2 909,1

20 1,61 7,32 0,84 3,82 0,20 909,1 0,4 1,82 0,4 1,82 0,2 909,1
NOTE 1
YOUR
VDS  4, 4 V 1,62 7,36 0,80 3,64 0,18 818,2 0,1 0,45 0,1 0,45 0 0
VP

Note 1: Set VGG (VGS) = 0 V and start increasing VDD from 0 V while measuring VRD and VDS. At the precise voltage that VRD
becomes a constant ID will also becomes a constant. ID = IDSS, VDS = VP where 0,5 V ≤ VP ≤ 8 V.
Note 2: Keep VDS =15 V (As measured in note 1.) and start decreasing VGG (VGS) from 0. At the voltage where VRD becomes 0
(zero) ID will be 0 (zero) and VGG (VGS) = VGS(off). This VGS(off) is suppose to be equal to –VP as determined in note 1.

497596959.doc Page 27 of 37 03 November 2020

3. Use the values obtained in the table to plot the transfer and output characteristic curves of the transistor. Indicate on the
curves the values of IDSS, Vgs(off) and Vp.

100
100

4. Compare the values you obtained with the values in the data tables.

PARAMETER YOUR VALUE DATA SHEET VALUE RANGE

IDSS/mA 7,36 6 to 15

VGS(off)/V -4,4 -0,5 to -8

Vp/V 4,4

YOU MUST USE THE SAME TRANSISTOR IN THE NEXT TWO LABS AS IN THIS LAB.
THEREFORE YOU MUST MAKE A NOTE OF YOUR TRANSISTOR’S IDSS AND VGS(off).

497596959.doc Page 28 of 37 03 November 2020

CALCULATIONS

VRD
ID 
RD
0,96

220
 4,36  103
 4,36 mA

497596959.doc Page 29 of 37 03 November 2020

Name: IITA J.S Student Number: 214047547

Bench Number: A4 Group: 35BELL

ELECTRONICS 2 LABORATORY ASSIGNMENT 12

MARKS OBTAINED:
Neatness (3)
Table 2 (4)
Table 3 (3)
Graph 4 (4)
Calculations (11) MODERATOR SIGNATURE
Penalties (-x)
Total marks [25] Total %

OBJECTIVE:
To investigate the parameters of a JFET amplifier connected in the common-gate configuration.

EQUIPMENT AND COMPONENTS NEEDED:

1 x Variable DC power supply 2 x Multimeters 3 x Banana to Banana cables 2 x 10 kΩ Resistors
1 x Signal generator 1 x Breadboard 3 x BNC to crocodile cables 2 x 1 μF Capacitor
1 x Oscilloscope 3 x Banana to crocodile cables 1 x 4.7 kΩ Resistor 1 x BF245 JFET

PROCEDURE:
1. Construct the circuit (Using the same transistor as in LAB. 11.).

+15 V L12-1-16
10k
RD

C2

10u
Q1

C1 BF245
10k
RL

1u

Esig(pp)
4k7
RS

0,5 V
2 kHz

Use values of IDSS and VGS(off) obtained in your Lab 11.

IDSS/mA VGS(off)/V

7,36 -4,4

2. With Esig disconnected, complete the table

PARAMETER CALCULATED MEASURED

ID/A 657×10-6 472×10-6

VD/V 8,43 10,34

VS/V 3,09 2,22

VGS/V -3,09 -2,22

497596959.doc Page 30 of 37 03 November 2020

3. With Esig connected, complete the table. (Use values of IDSS and VGS(off) obtained in Lab. 11).
Hint: To make sure that Esig(pp) is 0,5 V, disconnect the signal generator from the rest of the circuit
and adjust Esig(pp) to 0,5 V and then reconnect it to the rest of the circuit for the measurements.
PARAMETER CALCULATED MEASURED

Esig(pp)/V 0,5 0,5

A vLS 3,73 to 6,55 6,8

VL(p-p)/V 1,87 to 3,28 3,4

Zi/Ω 1137,23 to 614,61

Zo/Ω 7,14×103

4. Draw one cycle of the input and the output voltages on the graph.

30
40

497596959.doc Page 31 of 37 03 November 2020

CALCULATIONS

IDSS  RS 
2
2IDSSRS
a  b  1
V 
2
V
GSoff GSoff

 7,36  10    4,7  10   
2
3 3
2  7,36  10 3  4,7  103
  1
( 4, 4) 2
4,4
 1
 8, 40  103 A   16,72
 

c  IDSS
 7,36 mA

b  b2  4ac
ID 
2a


  16,72    16,72 
2
  
 4  8, 40  103  7,36  10 3 

2  8, 40  10 3

657,14106 A or 1,33103
 657,14 A  1,33 mA
 ID  657,14 A

VD  VDD  IDRD VS  IDRS


 15  657,14  10 6
   10  10 
3
  
 657,14  106  4,7  103 
 8, 43 V  3,09 V

VGS  VG  VS
 0  3,09
 3,09 V

497596959.doc Page 32 of 37 03 November 2020

  VGS 
gm  gm0  1  
 VGS off  
 
 3,09   3,09 
 3  103  1  to  6,5  10 3  1 
 4, 4   4, 4 
 893,18  106  1,94  10 3
 893,18  S  1,94 mS

1
rd 
yos
1

 40  10 
6

 25  103
 25 k

 r  RD 
RS   d 
Zi   1  gmrd 
 r  RD 
RS   d 
 1  gmrd 

 25  10    10  10  
 3 3 
 25  10    10  10  
3 3

 4,7  10    1 
3
 4,7  10    1
3

 
893,18  10    25  10   
 
6 3
1,94  10    25  10   
3 3

  to  

 25  10    10  10  
3 3 
 25  10    10  10  
3 3

 4,7  10   1  893,18  10  25  10 
  3
 4,7  103   1 1,94  10  25  10 
 

          
6 3 3 3

 1137,23   614,61 

RD  rd
Zo 
RD  rd


 10  10    25  10 
3 3

 10  10    25  10 
3 3

 7,14  103
 7,14 k

 RD 
 gmRD  
rd 
A vNL  
 RD 
1  
 rd 
  10  103    3 
 6
 
 893,18  10  10 x 10  
3
 3   1,94 x 10  x  10 x 10    10
-3  10
3

 25  10  
3
25  10
  to   
 10  103   10  103 
 1    1  
 25  103   25  103 
 6,67  14,14

 Zi   RL 
A VLS     A vNL
 Rsig  Zi   Zo  RL 
 
 1137,23   10  103   614,61   10  10 3 
    3
 6,67 to     3 
 12,14
 50  1137,23   7,14  10  10  10   50  614,61   7,14  10  10  10 
3 3

 3,73  6,55

VL(pp)  A v Vi(pp)
 3,73  0,5 to  6,55  0,5
 1,87 V  3,28 V

497596959.doc Page 33 of 37 03 November 2020

Name: IITA J.S Student Number: 214047547

Bench Number: A4 Group: 35BELL

ELECTRONICS 2 LABORATORY ASSIGNMENT 13

MARKS OBTAINED:
Neatness (3)
Table 2 (4)
Table 3 (3)
Graph 4 (4)
Calculations (11) MODERATOR SIGNATURE
Penalties (-x)
Total marks [25] Total %

OBJECTIVE:
To investigate the parameters of a JFET amplifier connected in the common-drain configuration.

EQUIPMENT AND COMPONENTS NEEDED:

1 x Variable DC power supply 1 x Breadboard 1 x 1 kΩ Resistor 1 x BF245 JFET
1 x Signal generator 3 x Banana to crocodile cables 2 x 10 kΩ Resistors
1 x Oscilloscope 3 x Banana to Banana cables 1 x 10 MΩ Resistor
2 x Multimeters 3 x BNC to crocodile cables 2 x 1 μF Capacitor

PROCEDURE:
1. Construct the circuit (Using the same transistor as in Lab. 11.).

+12 V L13-1-16

Q1
C1
C2
1u BF245
1u
Esig(pp)
2V
10M

10k
RG

RS

RL
1k

2 kHz

Use values of IDSS and VGS(off) obtained in your Lab 11.

IDSS/mA VGS(off)/V

7,36 -4,4

2. With Esig disconnected, complete the table.

PARAMETER CALCULATED MEASURED
-3
ID/A 2,06×10 1,71×10-3

VD/V 12 12,01

VS/V 2,06 1,67

VGS /V -2,06 -1,37

497596959.doc Page 34 of 37 03 November 2020

3. With Esig connected, complete the table. (Use values of IDSS and VGS(off) obtained in Lab. 11).
Hint: To make sure that Esig(pp) is 2 V, disconnect the signal generator from the rest of the circuit
and adjust Esig(pp) to 0,5 V and then reconnect it to the rest of the circuit for the measurements.
PARAMETER CALCULATED MEASURED

Esig(pp)/V 2 2

A vLS 0,59 to 0,75 0,7

VL(p-p)/mV 1,18 to 1,50 1,4

Zi/Ω 10×106

Zo/Ω 378,79 to 222,22

4. Draw one cycle of the input and the output voltages on the graph.

30
40

497596959.doc Page 35 of 37 03 November 2020

CALCULATIONS

IDSS  RS 
2
2IDSSRS
a  b  1
V 
2
V  
GS off
GS off 

 7,36  10    1 10      1
2
3 3
2  8, 46  10 3  1 103
 
 4, 4  4, 4
2

1
 380,17     4,35
A

c  IDSS
 7,36 mA

b  b2  4ac
ID 
2a
  4,35    4,35   4  380,17   7,36  103 
2

 VD  VDD
2  380,17 
 2,06 103 or  9,38103 12 V
ID  2,06 mA

VS  IDRS VGS   VS


 2,06  10 3
   1 10 
3
 2,06 V
 2,06 V

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  V 
gm  gm0  1  GS 
 VGSoff 
 2,06   2,06 
 3  10 3  1  to  6,5  10 3  1 
 4, 4   4,4 
 1,60 mS  3,46 mS

1
Zi  RG rds 
y os
1
 10  106    25  103   25 k
40  106

1 1 1
   gm
Zo RS rds


 1  
 1 10

3 
  25
1
 10

3 


 1,60  103  to 
 1  
 1 10

3 
  25
1
 10

3 


 3, 46  103 
 Zo  378,79   222,22 

 R r 
gm  S d 
A vNL =  RS  rd 
 R r 
1+gm  S d 
 RS  rd 
 1  103  25  103   1 103  25  103 
1,60  10-3   3 
3 
3,46  10 -3   3 3
=  1  10  25  10  to =  1 10  25  10 
 1  103  25  103   1 103  25  103 

1+ 1,60  10-3    3 
3   
1+ 3,46  10-3   3 3 
 1  10  25  10   1 10  25  10 
= 0,61 = 0,77

 Zi   RL 
A vLS    A vNL
 Rsig  Zi   Zo  RL 
 
 10  106   10  103   10  106   10  103 
    378,79  10  103   0,61
6 
  to     222,22  10  103   0,77
6 
 
 50  10  10     50  10  10   
 0,59  0,75

VL(pp)  A v Vi(p p)

 0,59  2  1,18 V to  0,75  2  1,50 V

497596959.doc Page 37 of 37 03 November 2020