6502 Instruction Set

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  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

0 BRK ORA ??? ??? ??? --- ORA ASL ??? PHP ORA ASL ??? ??? --- ORA ASL ???
0 impl X,ind --- --- zpg zpg --- impl # A --- abs abs ---

1 BPL ORA ??? ??? ??? --- ORA ASL ??? CLC ORA ??? ??? ??? --- ORA ASL ???
0 rel ind,Y --- --- zpg,X zpg,X --- impl abs,Y --- --- abs,X abs,X ---

2 JSR AND ??? ??? BIT AND ROL ??? PLP AND ROL ??? BIT AND ROL ???
0 abs X,ind --- --- zpg zpg zpg --- impl # A --- abs abs abs ---

3 BMI AND ??? ??? ??? --- AND ROL ??? SEC AND ??? ??? ??? --- AND ROL ???
0 rel ind,Y --- --- zpg,X zpg,X --- impl abs,Y --- --- abs,X abs,X ---

4 RTI EOR ??? ??? ??? --- EOR LSR ??? PHA EOR LSR ??? JMP EOR LSR ???
0 impl X,ind --- --- zpg zpg --- impl # A --- abs abs abs ---

5 BVC EOR ??? ??? ??? --- EOR LSR ??? CLI EOR ??? ??? ??? --- EOR LSR ???
0 rel ind,Y --- --- zpg,X zpg,X --- impl abs,Y --- --- abs,X abs,X ---

6 RTS ADC ??? ??? ??? --- ADC ROR ??? PLA ADC ROR ??? JMP ADC ROR ???
0 impl X,ind --- --- zpg zpg --- impl # A --- ind abs abs ---

7 BVS ADC ??? ??? ??? --- ADC ROR ??? SEI ADC ??? ??? ??? --- ADC ROR ???
0 rel ind,Y --- --- zpg,X zpg,X --- impl abs,Y --- --- abs,X abs,X ---

8 ??? STA ??? ??? STY STA STX ??? DEY ??? --- TXA ??? STY STA STX ???
0 --- X,ind --- --- zpg zpg zpg --- impl impl --- abs abs abs ---

9 BCC STA ??? ??? STY STA STX ??? TYA STA TXS ??? ??? --- STA ??? --- ???
0 rel ind,Y --- --- zpg,X zpg,X zpg,Y --- impl abs,Y impl --- abs,X ---

A LDY LDA LDX ??? LDY LDA LDX ??? TAY LDA TAX ??? LDY LDA LDX ???
0 # X,ind # --- zpg zpg zpg --- impl # impl --- abs abs abs ---

B BCS LDA ??? ??? LDY LDA LDX ??? CLV LDA TSX ??? LDY LDA LDX ???
0 rel ind,Y --- --- zpg,X zpg,X zpg,Y --- impl abs,Y impl --- abs,X abs,X abs,Y ---
C CPY CMP ??? ??? CPY CMP DEC ??? INY CMP DEX ??? CPY CMP DEC ???
0 # X,ind --- --- zpg zpg zpg --- impl # impl --- abs abs abs ---

D BNE CMP ??? ??? ??? --- CMP DEC ??? CLD CMP ??? ??? ??? --- CMP DEC ???
0 rel ind,Y --- --- zpg,X zpg,X --- impl abs,Y --- --- abs,X abs,X ---

E CPX SBC ??? ??? CPX SBC INC ??? INX SBC # NOP ??? CPX SBC INC ???
0 # X,ind --- --- zpg zpg zpg --- impl impl --- abs abs abs ---

F BEQ SBC ??? ??? ??? --- SBC INC ??? SED SBC ??? ??? ??? --- SBC INC ???
0 rel ind,Y --- --- zpg,X zpg,X --- impl abs,Y --- --- abs,X abs,X ---

Address Modes:

A .... Accumulator   OPC A   operand is AC

OPC
abs .... absolute     operand is address $HHLL
$HHLL
OPC
abs, absolute, X-
....   $HHLL,   operand is address incremented by X with carry
X indexed
X
OPC
abs, absolute, Y-
....   $HHLL,   operand is address incremented by Y with carry
Y indexed
Y
OPC
# .... immediate     operand is byte (BB)
#$BB
imp
.... implied   OPC   operand implied
l
OPC
ind .... indirect     operand is effective address; effective address is value of address
($HHLL)
X,in X-indexed, OPC operand is effective zeropage address; effective address is byte (BB) incremented by X
....    
d indirect ($BB,X) without carry
ind, indirect, Y- OPC operand is effective address incremented by Y with carry; effective address is word at
....    
Y indexed ($LL),Y zeropage address
OPC
rel .... relative     branch target is PC + offset (BB), bit 7 signifies negative offset
$BB
zpg .... zeropage   OPC $LL   operand is of address; address hibyte = zero ($00xx)
zpg, zeropage, X- OPC
....     operand is address incremented by X; address hibyte = zero ($00xx); no page transition
X indexed $LL,X
zpg, zeropage, Y- OPC
....     operand is address incremented by Y; address hibyte = zero ($00xx); no page transition
Y indexed $LL,Y

Instructions by Name:

AD
.... add with carry
C
AN
.... and (with accumulator)
D
AS
.... arithmetic shift left
L
BC
.... branch on carry clear
C
BC
.... branch on carry set
S
BE
.... branch on equal (zero set)
Q
BIT .... bit test
BM
.... branch on minus (negative set)
I
BN
.... branch on not equal (zero clear)
E
BP
.... branch on plus (negative clear)
L
BR
.... interrupt
K
BV
.... branch on overflow clear
C
BV
.... branch on overflow set
S
CL
.... clear carry
C
CL
.... clear decimal
D
CLI .... clear interrupt disable
CL
.... clear overflow
V
CM
.... compare (with accumulator)
P
CP
.... compare with X
X
CP
.... compare with Y
Y
DE
.... decrement
C
DE
.... decrement X
X
DE
.... decrement Y
Y
EO
.... exclusive or (with accumulator)
R
INC .... increment
INX .... increment X
INY .... increment Y
JM
.... jump
P
JSR .... jump subroutine
LD
.... load accumulator
A
LD
.... load X
Y
LD
.... load Y
Y
LS
.... logical shift right
R
NO
.... no operation
P
OR
.... or with accumulator
A
PH
.... push accumulator
A
PH
.... push processor status (SR)
P
PL
.... pull accumulator
A
PLP .... pull processor status (SR)
RO
.... rotate left
L
RO
.... rotate right
R
RTI .... return from interrupt
RT
.... return from subroutine
S
SB
.... subtract with carry
C
SE
.... set carry
C
SE
.... set decimal
D
SEI .... set interrupt disable
ST
.... store accumulator
A
ST
.... store X
X
ST
.... store Y
Y
TA
.... transfer accumulator to X
X
TA
.... transfer accumulator to Y
Y
TS
.... transfer stack pointer to X
X
TX
.... transfer X to accumulator
A
TX
.... transfer X to stack pointer
S
TY
.... transfer Y to accumulator
A

Registers:

P
.... program counter (16 bit)
C
A
.... accumulator (8 bit)
C
X .... X register (8 bit)
Y .... Y register (8 bit)
S
.... status register [NV-BDIZC] (8 bit)
R
SP .... stack pointer (8 bit)

 
SR Flags (bit 7 to bit 0):

N .... Negative
V .... Overflow
- .... ignored
B .... Break
D .... Decimal (use BCD for arithmetics)
I .... Interrupt (IRQ disable)
Z .... Zero
C .... Carry
 

Processor Stack:
LIFO, top down, 8 bit range, 0x0100 - 0x01FF
 

Bytes, Words, Addressing:

8 bit bytes, 16 bit words in lobyte-hibyte representation (Little-Endian).
16 bit address range, operands follow instruction codes.
 

Vendor:
MOS Technology, 1975

APPENDIX A: 6502 Instructions in Detail

ADC Add Memory to Accumulator with Carry

A + M + C -> A, C NZCIDV
+++--+

addressing assembler opc bytes cyles

--------------------------------------------
immidiate ADC #oper 69 2 2
zeropage ADC oper 65 2 3
zeropage,X ADC oper,X 75 2 4
absolute ADC oper 6D 3 4
absolute,X ADC oper,X 7D 3 4*
absolute,Y ADC oper,Y 79 3 4*
(indirect,X) ADC (oper,X) 61 2 6
(indirect),Y ADC (oper),Y 71 2 5*

AND AND Memory with Accumulator

A AND M -> A NZCIDV

++----

addressing assembler opc bytes cyles

--------------------------------------------
immidiate AND #oper 29 2 2
zeropage AND oper 25 2 3
zeropage,X AND oper,X 35 2 4
absolute AND oper 2D 3 4
absolute,X AND oper,X 3D 3 4*
absolute,Y AND oper,Y 39 3 4*
(indirect,X) AND (oper,X) 21 2 6
(indirect),Y AND (oper),Y 31 2 5*

ASL Shift Left One Bit (Memory or Accumulator)

C <- [76543210] <- 0 NZCIDV

+++---

addressing assembler opc bytes cyles

--------------------------------------------
accumulator ASL A 0A 1 2
zeropage ASL oper 06 2 5
zeropage,X ASL oper,X 16 2 6
absolute ASL oper 0E 3 6
absolute,X ASL oper,X 1E 3 7

BCC Branch on Carry Clear

branch on C = 0 NZCIDV
 ------

addressing assembler opc bytes cyles

--------------------------------------------
relative BCC oper 90 2 2**

BCS Branch on Carry Set

branch on C = 1 NZCIDV
------

addressing assembler opc bytes cyles

--------------------------------------------
relative BCS oper B0 2 2**

BEQ Branch on Result Zero

branch on Z = 1 NZCIDV
------

addressing assembler opc bytes cyles

--------------------------------------------
relative BEQ oper F0 2 2**

BIT Test Bits in Memory with Accumulator

bits 7 and 6 of operand are transfered to bit 7 and 6 of SR (N,V);

the zeroflag is set to the result of operand AND accumulator.

A AND M, M7 -> N, M6 -> V NZCIDV

M7 + - - - M6

addressing assembler opc bytes cyles

--------------------------------------------
zeropage BIT oper 24 2 3
absolute BIT oper 2C 3 4

BMI Branch on Result Minus

branch on N = 1 NZCIDV
------

addressing assembler opc bytes cyles

--------------------------------------------
relative BMI oper 30 2 2**

BNE Branch on Result not Zero

branch on Z = 0 NZCIDV
------

addressing assembler opc bytes cyles

--------------------------------------------
relative BNE oper D0 2 2**

BPL Branch on Result Plus

branch on N = 0 NZCIDV
------

addressing assembler opc bytes cyles

--------------------------------------------
relative BPL oper 10 2 2**

BRK Force Break

interrupt, NZCIDV
push PC+2, push SR ---1--

addressing assembler opc bytes cyles

--------------------------------------------
implied BRK 00 1 7
BVC Branch on Overflow Clear

branch on V = 0 NZCIDV
------

addressing assembler opc bytes cyles

--------------------------------------------
relative BVC oper 50 2 2**

BVS Branch on Overflow Set

branch on V = 1 NZCIDV
------

addressing assembler opc bytes cyles

--------------------------------------------
relative BVC oper 70 2 2**

CLC Clear Carry Flag

0 -> C NZCIDV
--0---

addressing assembler opc bytes cyles

--------------------------------------------
implied CLC 18 1 2

CLD Clear Decimal Mode

0 -> D NZCIDV
----0-

addressing assembler opc bytes cyles

--------------------------------------------
implied CLD D8 1 2

CLI Clear Interrupt Disable Bit

0 -> I NZCIDV
---0--

addressing assembler opc bytes cyles

--------------------------------------------
implied CLI 58 1 2

CLV Clear Overflow Flag

0 -> V NZCIDV
-----0

addressing assembler opc bytes cyles

--------------------------------------------
implied CLV B8 1 2

CMP Compare Memory with Accumulator

A-M NZCIDV
+++---

addressing assembler opc bytes cyles

--------------------------------------------
immidiate CMP #oper C9 2 2
zeropage CMP oper C5 2 3
zeropage,X CMP oper,X D5 2 4
absolute CMP oper CD 3 4
absolute,X CMP oper,X DD 3 4*
absolute,Y CMP oper,Y D9 3 4*
(indirect,X) CMP (oper,X) C1 2 6
(indirect),Y CMP (oper),Y D1 2 5*

CPX Compare Memory and Index X

X-M NZCIDV
+++---
 addressing assembler opc bytes cyles
--------------------------------------------
immidiate CPX #oper E0 2 2
zeropage CPX oper E4 2 3
absolute CPX oper EC 3 4

CPY Compare Memory and Index Y

Y-M NZCIDV
+++---

addressing assembler opc bytes cyles

--------------------------------------------
immidiate CPY #oper C0 2 2
zeropage CPY oper C4 2 3
absolute CPY oper CC 3 4

DEC Decrement Memory by One

M - 1 -> M NZCIDV
++----

addressing assembler opc bytes cyles

--------------------------------------------
zeropage DEC oper C6 2 5
zeropage,X DEC oper,X D6 2 6
absolute DEC oper CE 3 3
absolute,X DEC oper,X DE 3 7

DEX Decrement Index X by One

X - 1 -> X NZCIDV
++----

addressing assembler opc bytes cyles

--------------------------------------------
implied DEC CA 1 2

DEY Decrement Index Y by One

Y - 1 -> Y NZCIDV
++----

addressing assembler opc bytes cyles

--------------------------------------------
implied DEC 88 1 2

EOR Exclusive-OR Memory with Accumulator

A EOR M -> A NZCIDV

++----

addressing assembler opc bytes cyles

--------------------------------------------
immidiate EOR #oper 49 2 2
zeropage EOR oper 45 2 3
zeropage,X EOR oper,X 55 2 4
absolute EOR oper 4D 3 4
absolute,X EOR oper,X 5D 3 4*
absolute,Y EOR oper,Y 59 3 4*
(indirect,X) EOR (oper,X) 41 2 6
(indirect),Y EOR (oper),Y 51 2 5*

INC Increment Memory by One

M + 1 -> M NZCIDV
++----

addressing assembler opc bytes cyles

--------------------------------------------
zeropage INC oper E6 2 5
zeropage,X INC oper,X F6 2 6
absolute INC oper EE 3 6
absolute,X INC oper,X FE 3 7
INX Increment Index X by One

X + 1 -> X NZCIDV
++----

addressing assembler opc bytes cyles

--------------------------------------------
implied INX E8 1 2

INY Increment Index Y by One

Y + 1 -> Y NZCIDV
++----

addressing assembler opc bytes cyles

--------------------------------------------
implied INY C8 1 2

JMP Jump to New Location

(PC+1) -> PCL NZCIDV

(PC+2) -> PCH ------

addressing assembler opc bytes cyles

--------------------------------------------
absolute JMP oper 4C 3 3
indirect JMP (oper) 6C 3 5

JSR Jump to New Location Saving Return Address

push (PC+2), NZCIDV

(PC+1) -> PCL ------
(PC+2) -> PCH

addressing assembler opc bytes cyles

--------------------------------------------
absolute JSR oper 20 3 6

LDA Load Accumulator with Memory

M -> A NZCIDV
++----

addressing assembler opc bytes cyles

--------------------------------------------
immidiate LDA #oper A9 2 2
zeropage LDA oper A5 2 3
zeropage,X LDA oper,X B5 2 4
absolute LDA oper AD 3 4
absolute,X LDA oper,X BD 3 4*
absolute,Y LDA oper,Y B9 3 4*
(indirect,X) LDA (oper,X) A1 2 6
(indirect),Y LDA (oper),Y B1 2 5*

LDX Load Index X with Memory

M -> X NZCIDV
++----

addressing assembler opc bytes cyles

--------------------------------------------
immidiate LDX #oper A2 2 2
zeropage LDX oper A6 2 3
zeropage,Y LDX oper,Y B6 2 4
absolute LDX oper AE 3 4
absolute,Y LDX oper,Y BE 3 4*

LDY Load Index Y with Memory

M -> Y NZCIDV
++----

addressing assembler opc bytes cyles

 --------------------------------------------
immidiate LDY #oper A0 2 2
zeropage LDY oper A4 2 3
zeropage,X LDY oper,X B4 2 4
absolute LDY oper AC 3 4
absolute,X LDY oper,X BC 3 4*

LSR Shift One Bit Right (Memory or Accumulator)

0 -> [76543210] -> C NZCIDV

-++---

addressing assembler opc bytes cyles

--------------------------------------------
accumulator LSR A 4A 1 2
zeropage LSR oper 46 2 5
zeropage,X LSR oper,X 56 2 6
absolute LSR oper 4E 3 6
absolute,X LSR oper,X 5E 3 7

NOP No Operation

--- NZCIDV
------

addressing assembler opc bytes cyles

--------------------------------------------
implied NOP EA 1 2

ORA OR Memory with Accumulator

A OR M -> A NZCIDV
++----

addressing assembler opc bytes cyles

--------------------------------------------
immidiate ORA #oper 09 2 2
zeropage ORA oper 05 2 3
zeropage,X ORA oper,X 15 2 4
absolute ORA oper 0D 3 4
absolute,X ORA oper,X 1D 3 4*
absolute,Y ORA oper,Y 19 3 4*
(indirect,X) ORA (oper,X) 01 2 6
(indirect),Y ORA (oper),Y 11 2 5*

PHA Push Accumulator on Stack

push A NZCIDV
------

addressing assembler opc bytes cyles

--------------------------------------------
implied PHA 48 1 3

PHP Push Processor Status on Stack

push SR NZCIDV
------

addressing assembler opc bytes cyles

--------------------------------------------
implied PHP 08 1 3

PLA Pull Accumulator from Stack

pull A NZCIDV
++----

addressing assembler opc bytes cyles

--------------------------------------------
implied PLA 68 1 4

PLP Pull Processor Status from Stack

 pull SR NZCIDV
from stack

addressing assembler opc bytes cyles

--------------------------------------------
implied PHP 28 1 4

ROL Rotate One Bit Left (Memory or Accumulator)

C <- [76543210] <- C NZCIDV

+++---

addressing assembler opc bytes cyles

--------------------------------------------
accumulator ROL A 2A 1 2
zeropage ROL oper 26 2 5
zeropage,X ROL oper,X 36 2 6
absolute ROL oper 2E 3 6
absolute,X ROL oper,X 3E 3 7

ROR Rotate One Bit Right (Memory or Accumulator)

C -> [76543210] -> C NZCIDV

+++---

addressing assembler opc bytes cyles

--------------------------------------------
accumulator ROR A 6A 1 2
zeropage ROR oper 66 2 5
zeropage,X ROR oper,X 76 2 6
absolute ROR oper 6E 3 6
absolute,X ROR oper,X 7E 3 7

RTI Return from Interrupt

pull SR, pull PC NZCIDV

from stack

addressing assembler opc bytes cyles

--------------------------------------------
implied RTI 40 1 6

RTS Return from Subroutine

pull PC, PC+1 -> PC NZCIDV

------

addressing assembler opc bytes cyles

--------------------------------------------
implied RTS 60 1 6

SBC Subtract Memory from Accumulator with Borrow

A - M - C -> A NZCIDV
+++--+

addressing assembler opc bytes cyles

--------------------------------------------
immidiate SBC #oper E9 2 2
zeropage SBC oper E5 2 3
zeropage,X SBC oper,X F5 2 4
absolute SBC oper ED 3 4
absolute,X SBC oper,X FD 3 4*
absolute,Y SBC oper,Y F9 3 4*
(indirect,X) SBC (oper,X) E1 2 6
(indirect),Y SBC (oper),Y F1 2 5*

SEC Set Carry Flag

1 -> C NZCIDV
--1---

addressing assembler opc bytes cyles

--------------------------------------------
implied SEC 38 1 2
SED Set Decimal Flag

1 -> D NZCIDV
----1-

addressing assembler opc bytes cyles

--------------------------------------------
implied SED F8 1 2

SEI Set Interrupt Disable Status

1 -> I NZCIDV
---1--

addressing assembler opc bytes cyles

--------------------------------------------
implied SEI 78 1 2

STA Store Accumulator in Memory

A -> M NZCIDV
------

addressing assembler opc bytes cyles

--------------------------------------------
zeropage STA oper 85 2 3
zeropage,X STA oper,X 95 2 4
absolute STA oper 8D 3 4
absolute,X STA oper,X 9D 3 5
absolute,Y STA oper,Y 99 3 5
(indirect,X) STA (oper,X) 81 2 6
(indirect),Y STA (oper),Y 91 2 6

STX Store Index X in Memory

X -> M NZCIDV
------

addressing assembler opc bytes cyles

--------------------------------------------
zeropage STX oper 86 2 3
zeropage,Y STX oper,Y 96 2 4
absolute STX oper 8E 3 4

STY Sore Index Y in Memory

Y -> M NZCIDV
------

addressing assembler opc bytes cyles

--------------------------------------------
zeropage STY oper 84 2 3
zeropage,X STY oper,X 94 2 4
absolute STY oper 8C 3 4

TAX Transfer Accumulator to Index X

A -> X NZCIDV
++----

addressing assembler opc bytes cyles

--------------------------------------------
implied TAX AA 1 2

TAY Transfer Accumulator to Index Y

A -> Y NZCIDV
++----

addressing assembler opc bytes cyles

--------------------------------------------
implied TAY A8 1 2
TSX Transfer Stack Pointer to Index X

SP -> X NZCIDV
++----

addressing assembler opc bytes cyles

--------------------------------------------
implied TSX BA 1 2

TXA Transfer Index X to Accumulator

X -> A NZCIDV
++----

addressing assembler opc bytes cyles

--------------------------------------------
implied TXA 8A 1 2

TXS Transfer Index X to Stack Register

X -> SP NZCIDV
++----

addressing assembler opc bytes cyles

--------------------------------------------
implied TXS 9A 1 2

TYA Transfer Index Y to Accumulator

Y -> A NZCIDV
++----

addressing assembler opc bytes cyles

--------------------------------------------
implied TYA 98 1 2

* add 1 to cycles if page boundery is crossed

** add 1 to cycles if branch occurs on same page

add 2 to cycles if branch occurs to different page

Legend to Flags: + .... modified

- .... not modified
1 .... set
0 .... cleared
M6 .... memory bit 6
M7 .... memory bit 7

Note on assembler syntax:

Most assemblers employ "OPC *oper" for forced zeropage addressing.

APENDIX B: The 65xx-Family:

Type Features, Comments

-------------------------------------
6502 NMOS, 16 bit address bus, 8 bit data bus
6502A accelerated version of 6502
6502C accelerated version of 6502, CMOS
65C02 16 bit version, additional instructions and address modes
6503, 6505, 6506 12 bit address bus [4 KiB]
6504 13 bit address bus [8 KiB]
6507 13 bit address bus [8 KiB], no interrupts
6509 20 bit address bus [1 MiB] by bankswitching
6510 as 6502 with additional 6 bit I/O-port
6511 integrated micro controler with I/O-port, serial interface, and RAM (Rockwell)
65F11 as 6511, integrated FORTH interpreter
7501 as 6502, HMOS
8500 as 6510, CMOS
8502 as 6510 with switchable 2 MHz option, 7 bit I/O-port
65816 (65C816) 16 bit registers and ALU, 24 bit address bus [16 MiB], up to 24 MHz (Western Design Center)
65802 (65C802) as 65816, pin compatible to 6502, 64 KiB address bus, up to 16 MHz
 

Disclaimer:
Errors excepted. The information is provided for free and AS IS, therefore without any warranty;
without even the implied warranty of merchantability or fitness for a particular purpose.