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EE577a Syllabus Jaiswal Fall20

This document provides information for the EE577A Fall 20 - VLSI System Design course taught by Akhilesh Jaiswal at USC. The course covers advanced VLSI design topics such as digital system design, custom layout techniques, timing and power analysis, and memory design. It lists course materials, prerequisites, instructor contact information, teaching assistants, grading policy, exam details, assignment expectations, and a tentative schedule of topics.

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Amandeep Vaish
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0% found this document useful (0 votes)
670 views4 pages

EE577a Syllabus Jaiswal Fall20

This document provides information for the EE577A Fall 20 - VLSI System Design course taught by Akhilesh Jaiswal at USC. The course covers advanced VLSI design topics such as digital system design, custom layout techniques, timing and power analysis, and memory design. It lists course materials, prerequisites, instructor contact information, teaching assistants, grading policy, exam details, assignment expectations, and a tentative schedule of topics.

Uploaded by

Amandeep Vaish
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EE577A Fall 20 – VLSI System Design

Akhilesh Jaiswal
University of Southern California
Viterbi School of Engineering

Course Description
This is the second course on VLSI design covering, among others, the following topics:
digital system design; advanced custom layout design techniques; timing, power, and
noise analysis of VLSI circuits; data path, flip-flop and latch design, and memory design.

Websites
http://courses.uscden.net
https://courses.uscden.net/d2l/home/19117

Course Materials
• Lecture slides (will be posted on the course page)
• Supplemental material (research papers, technical articles, etc. provided by the
instructor)
• Textbook: CMOS VLSI Design: A Circuits and Systems Perspective, N. Weste
and D. Harris, Addison-Wesley, 4th edition, 2011.

Additional Readings
• CMOS Digital Integrated Circuits, S.M. Kang and Y. Leblebici, Mc Graw Hill, 3rd
edition, 2003; or the 4th edition: CMOS Digital Integrated Circuits: Analysis and
Design, S. M. Kang, Y. Leblebici, and C. Kim, McGraw-Hill, 4th edition, 2014.
• Digital Integrated Circuits: A Design Perspective, J. Rabaey, A.
Chandrakasan, and B. Nikolic, Prentice Hall, 2nd edition, 2003.
• Modern VLSI Design: System-On-Chip Design, W. Wolf, Prentice Hall, 3rd
edition, 2002.
• Logical Effort: Designing Fast CMOS Circuits, I. Sutherland, R. F. Sproull,
D. Harris, Morgan Kaufmann, 1999.

Prerequisite
EE477L

Instructor
Akhilesh Jaiswal
Office Hours: Mon/Wed 1-2pm (Pacific Time) or by appointment
Contact: [email protected]
Zoom :https://usc.zoom.us/j/95881072168?pwd=ejhNWTNWeG1MdTlqL2d1TE90eVNnQT09
Passcode: 229321
Teaching Assistants
Marzieh Vaeztourshizi [email protected]
Office: TBD
Office hours:

Graders
Shwetha Vijayakumar [email protected]

Tools Teaching Assistant


Soowang Park [email protected]

Grading Policy
Homework and Lab Assignments: 15%
Midterms 1-2: 30%, 40%
Final Project: 15%

Exams
There are two exams (midterms), all of which are tentatively closed-book, with no
calculators allowed. You will receive updated guidelines for each exam about 5 to 7 days
before the exam date.

Assignments
Assignments are key to the learning process. They are designed to familiarize you with
the design problems and skills you will need for your future careers. Some lab assignments
will also be included to guide you through learning the tools, languages, and standards.
Only by doing real problems or lab tasks on your own will you develop the skills and
understanding to succeed. Please also note the following guidelines:
• Each lab may consist of a few phases to help with time management. It is expected
that you present your own original work and solution.
• Homework assignments may be used to support the lecture contents.
• The final project will also be developed in multiple phases.
• We take academic honesty very seriously. Any type of unauthorized collaboration or
plagiarism on any assignment will be subject to penalties, from grade reductions to
failing the course and expulsion from USC in case of severe violations of academic
integrity rules.
• We highly recommend posting your questions on the Piazza discussion board for each
assignment, so others would be able to review your questions and our answers.
• Make sure that your first and last names and your student ID are clearly readable on
your submissions. You may be penalized if any of the above items is missing.

All assignments will be graded


Discussion Sections
The main purpose of discussion classes is to help you learn the tools and languages as well as discuss the lab
and project details.

Expectations
Students are expected to follow the academic honesty policies of USC, attend classes, take notes, and participate
in discussions by asking questions and providing answers/arguments.

Statement on Academic Conduct and Support Systems

Academic Integrity
Plagiarism – presenting someone else’s ideas as your own, either verbatim or recast in your own words – is a
serious academic offense with serious consequences. Please familiarize yourself with the discussion of
plagiarism in SCampus in Section 11, Behavior Violating University Standards (https://scampus.usc.edu/1100-
behavior-violating- university-standards-and-appropriate-sanctions/). Other forms of academic dishonesty are
equally unacceptable. See additional information in SCampus and university policies on scientific misconduct
(http://policy.usc.edu/scientific-misconduct/). Discrimination, sexual assault, and harassment are not tolerated
by the university. You are encouraged to report any incidents to the Office of Equity and Diversity
(http://equity.usc.edu/) or to the Department of Public Safety (http://capsnet.usc.edu/department/department-
public- safety/online-forms/contactus). This is important for the safety of the whole USC community. Another
member of the university community - such as a friend, classmate, advisor, or faculty member - can help initiate
the report, or can initiate the report on behalf of another person. The Center for Women and Men
(http://www.usc.edu/student- affairs/cwm/) provides 24/7 confidential support, and the sexual assault resource
center webpage [email protected] describes reporting options and other resources.

Support Systems
A number of USC's schools provide support for students who need help with scholarly writing. Check with your
advisor or program staff to find out more. Students whose primary language is not
English should check with the American Language Institute http://dornsife.usc.edu/ali,
which sponsors courses and workshops specifically for international graduate students. The Office of Disability
Services and Programs http://sait.usc.edu/academicsupport/centerprograms/dsp/home_index.html provides
certification for students with disabilities and helps arrange the relevant accommodations. If
an officially declared emergency makes travel to campus infeasible, USC Emergency Information
http://emergency.usc.edu/ will provide safety and other updates, including ways in which instruction will be
continued by means of blackboard, teleconferencing, and other technology.
Tentative Schedule and Topics
Week Lecture-1 (Tuesday) Lecture-2 (Thursday) Friday Discussion
Pre-Requisites Review
MOSFET HW1/Lab1/Perl/Pytho
Introduction
HW1 Assigned. Lab1P1 n
24-Aug 1 Assigned
Lab1P2/Tool Demo
Pre-Requisites Review Short Channel Effects Lab1P1 Due, Lab1P2
MOSFET Assigned
31-Aug 2
Short Channel Effects and
Logical Effort,
Advanced MOSFETS HW2/Tool Demo
HW1 Due, HW2 Assigned,
7-Sep 3
Lab1P3
Logical Effort
Logical Effort Lab1P2 Due,Lab1P3
14-Sep 4 Assigned
Logical Effort
Memory Basic - ROM HW3/Lab1P3
21-Sep 5 HW2 Due, HW3 Assigned,
Project Phase I/Mid-
Term-1
ROM Design Midterm-1
Project Phase I
28-Sep 6 Assigned
SRAM Design SRAM Design
HW4/Lab2
5-Oct 7 HW3 Due, HW4 Assigned, Lab1P3 Due, Lab2 Assigned
HW5/Project Phase II
DRAM Design,
SRAM Optimization Project Phase II-III
HW4 Due, HW 5 Assigned
12-Oct 8 Assigned
Power Components &
Power Components & HW6
Optimization,
Optimization Project Phase I Due
19-Oct 9 HW 5 Due, HW 6 Assigned
Power Components & Power Components & Lab3/HW7
Optimization Optimization HW 6 Due, HW 7
26-Oct 10 Lab 2 Due, Lab3 Assigned Assigned
HW8
Datapath Design,
Datapath Design, HW 7 Due, HW 8
2-Nov 11 Assigned
Flip Flop Design
Time Borrowing, HW 8 Due
9-Nov 12 Lab 3 Due
Project Phase III/Mid-
Time Borrowing Course Wrap Up Term-2
16-Nov 13 Phase II Due
23-Nov 14 Midterm-2

Finals Week Project Phase III Due


1-2 Additional Online Pre-Recorded Lectures on Introduction to Emerging Memory Technologies
La1P1: Scripting, Lab1P2: Adder/Mul, Lab1P3: Adder/Mul Layout, Lab2: SRAM, Lab3: Pipelined Mul

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