UNIT 4

Single-phase half-bridge inverter

• Consists of 2 choppers, 3-wire DC source

• Transistors switched on and off alternately

• Need to isolate the gate signal for Q1 (upper device)

• Each provides opposite polarity of Vs/2 across the load

Mode1: Q1 on, Q2 off, Vo = Vs/2

Mode2: Q1 off, Q2 on, Vo = -Vs/2

When the load is highly inductive

Turn off Q1 at t = To/2 Turn off Q1 at t = To/2

Current falls to 0 via D2, L, (Vs/2) lower Current falls to 0 via D2, L, (Vs/2) lower

Single-phase full-bridge inverter

Mode1: Q1-Q2 on, Q3-Q4 off, Vo = Vs

Mode2: Q3-Q4 on, Q1-Q2 off, Vo = -Vs

When the load is highly inductive in a single phase full bridge inverter

Turn Q1-Q2 off – Q3-Q4 off Turn Q3-Q4 off – Q1-Q2 off

Fig (b) shows the waveform output and Fig(c) shows the io when the load is highly inductive
Three-Phase Inverters:

 Three-phase inverters are used for high power applications.

 This arrangement will require 6 thyristor switches, 6 diodes in a three phase inverter.

 Two types of control signals can be applied to the transistors: 180o conduction or 120o
conduction.

 The gating signals of the single phase inverters should be 180 or 120 degrees with
respect to each other and a phase shift of 60 degrees from each other.

180o conduction mode:

The gating signals of the single phase inverters should be 180 degrees with respect to each
other and a phase shift of 60 degrees from each other

Mode Interval Thyristors Operating

I 00-600 T5, T6, T1

II 600-1200 T6, T1, T2

III 1200-1800 T1, T2, T3

IV 1800-2400 T3, T4, T5

V 2400-3000 T4, T5, T6

VI 3000-3600 T5, T6, T1

Mode1:
R 3R
Req  R  
2 2
V 2V
i1  s  s
Req 3R
i1 R Vs
van  vcn  
2 3
2Vs
vbn  i1 R 
3
Mode2:
120 degree Conduction:
 Mode Interval Thyristors Operating

I 00-600 T6, T1

II 600-1200 T1, T2

III 1200-1800 T2, T3

IV 1800-2400 T3, T4

V 2400-3000 T4, T5

VI 3000-3600 T5, T6

PWM techniques:

In this method, a fixed dc input voltage is given to the inverter and a controlled ac output
voltage is obtained by adjusting the on and off periods of the inverter components. This is the
most popular method of controlling the output voltage and this method is termed as PWM
control.
Single-Pulse-Width-Modulation

Multi-Pulse width modulation

The harmonic content can be reduced by using several pulses in each half-cycle of output voltage. The
generation of gating signals for turning on and off transistors is shown in Figure (3). The gating signals
are produced by comparing reference signal with triangular carrier wave. The variation of modulation
index (M) from 0 to 1 varies the pulse from 0 to π/p and the output voltage from 0 to Vm.
Sinusoidal Pulse Width modulation

Instead of maintaining the width of all pulses the same as in the case of uniform pulse width
modulation, the width of each pulse is vary in proportion to the amplitude of a sine wave evaluated at
the center of the same pulse.
The distortion factor and lower-order harmonics are reduced scientifically. The gating signals as shown
in Fig.(2) are generated by comparing a sinusoidal reference signal with a triangular carrier signal of
frequency fc. This type of modulation is commonly used in industrial applications and abbreviated as
SPWM. The frequency of reference signal (fr), determine the converter output frequency (fo) and its
peak amplitude (Ar) controls the modulation index, M. The number of pulses per half cycle depends on
the carrier frequency.

Triangle waveform switching freq. = fc (also called carrier freq.)

Control signal freq. = f (also called modulation freq.)

Amplitude modulation ratio, m = Peak amplitude of control signal /Peak amplitude of triangular signal
Frequency modulation ratio,
mf (P)= fc / f

In multiple-pulse modulation, all pulses are the same width

Vary the pulse width according to the amplitude of a sine wave evaluated at the center of the same
pulse

Modified sinusoidal PWM

Space Vector Modulation:

In a three phase inverter the switches must be controlled so that at no time are both switches in the
same leg turned on or else the DC supply would be shorted. This requirement may be met by the
complementary operation of the switches within a leg i.e. if A+ is on then A− is off and vice versa. This
leads to eight possible switching vectors for the inverter, V0 through V7 with six active switching vectors
and two zero vectors.

Vector A+ B+ C+ A− B− C− VAB VBC VCA

V0 = {000} OFF OFF OFF ON ON ON 0 0 0 zero vector

V1 = {100} ON OFF OFF OFF ON ON +Vdc 0 −Vdc active vector

V2 = {110} ON ON OFF OFF OFF ON 0 +Vdc −Vdc active vector

V3 = {010} OFF ON OFF ON OFF ON −Vdc +Vdc 0 active vector

V4 = {011} OFF ON ON ON OFF OFF −Vdc 0 +Vdc active vector

V5 = {001} OFF OFF ON ON ON OFF 0 −Vdc +Vdc active vector

V6 = {101} ON OFF ON OFF ON OFF +Vdc −Vdc 0 active vector

V7 = {111} ON ON ON OFF OFF OFF 0 0 0 zero vector

Note that looking down the columns for the active switching vectors V1-6, the output voltages vary as a
pulsed sinusoid, with each leg offset by 120 degrees of phase angle.
To implement space vector modulation, a reference signal Vref is sampled with a frequency fs (Ts = 1/fs).
The reference signal may be generated from three separate phase references using the Clarke
Transformation. The reference vector is then synthesized using a combination of the two adjacent active
switching vectors and one or both of the zero vectors. Various strategies of selecting the order of the
vectors and which zero vector(s) to use exist. Strategy selection will affect the harmonic content and the
switching losses.
 Fig. Output voltage vector in the α β, plane or d-q axis
Series-Resonant Inverter:

 T1 is fired and resonant pulse of current flows through the load.

 The current falls to zero at t = t1m and T1 is “self – commutated”.
 T2 is then fired, and reverse resonant current flows through the load
 T2 is also “self-commutated”. The series resonant circuit must be under-damped,

R2 < (4L/C)
Mode1: Fire T1

Mode2: T1, T2 Both OFF

Mode3: Fire T2
To avoid a short-circuit across the main dc supply, T1 must be turned OFF before T2 is turned ON,
resulting in a “dead zone”. This “off-time” must be longer than the turn-off time of the thyristors, tq.
The maximum possible output frequency is:

Auto-Sequential Commutated Inverter (ASCI):

Mode I: The circuit for this mode is shown in Fig. 39.3. The following are the assumptions. Starting from
the instant,t=0 , the thyristor pair, Th−=0t & Th , is conducting (ON), and the current (I) flows through
2 4
the path, Th , D , load (L), D , Th , and source, I. The commutating capacitors are initially charged equally
2 2 4 4
with the polarity as given, i.e., vc1 = vc2 = VCo. This means that both capacitors have right hand plate
positive and left hand plate negative. If two capacitors are not charged initially, they have to pre-
charged.

Mode II: The circuit for this mode is shown in Fig. 39.4a. Diodes, D & D , are already conducting,
2 4
but at t=t1, diodes, D1 & D , get forward biased, and start conducting. Thus, at the end of time t , all
3 1
four diodes, D –D conduct. As a result, the commutating capacitors now get connected in parallel
1 4
with the load (L).
Mode1 Mode2