MCS9835CV-BA

PCI to Dual UART & Parallel Port

Datasheet

MosChip Semiconductor Technology

3335, Kifer Road, Santa Clara,
California - 95051
Ph. (408) 737- 7141
www.moschip.com
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effect at the time of sale per MosChip Semiconductor Technology, LTD standard limited warranty. MosChip
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information contained herein is subject to change without notice and no responsibility is assumed by MosChip
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Copyright © 2010 MosChip Semiconductor All Rights Reserved.

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Index

1. General Description ................................................................................................................. 3

2. Features..................................................................................................................................... 3
3. Applications ............................................................................................................................... 4
4. Ordering Information............................................................................................................... 4
5. Application Schematic .............................................................................................................. 4
6. Evaluation Board ...................................................................................................................... 4
7. Software Support ...................................................................................................................... 5
8. Certifications ............................................................................................................................. 5
9. Block Diagram........................................................................................................................... 6
10. PIN DIAGRAM....................................................................................................................... 7
11. Pin Descriptions ...................................................................................................................... 8
12. Architectural overview ......................................................................................................... 13
12.1 PCI Core ........................................................................................................................................13
12.2 UART Core....................................................................................................................................17
12.3 Parallel Port...................................................................................................................................18
13. External EEPROM ............................................................................................................... 22
13.1 Extended Modes through EEPROM................................................................................. 22
14. EEPROM Contents............................................................................................................... 23
15. Electrical Specifications........................................................................................................ 26
16. Mechanical Specifications – QFP 128 ................................................................................. 27
17. Contact information.............................................................................................................. 28
Revision history........................................................................................................................... 28

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1. General Description
The MCS9835CV-BA is a PCI based single function I/O Adapter. It has two 16C450/16C550 compatible
UART channels and one IEEE 1284 compliant parallel port.

The MCS9835CV-BA has 32-Byte transmit and receive FIFO for each UART channel. MCS8935CV-BA
performs serial-to-parallel conversions on data received from a Serial device, and parallel-to-serial
conversions on data received from its CPU.

Parallel Port interface in MCS9835CV-BA is an IEEE 1284 compliant SPP / PS2 / EPP / ECP Parallel
Port that fully supports Centronics interface.

The MCS9835CV-BA is ideally suited for PC applications, such as Add-On COM ports and Parallel
Ports. It is available in 128-Pin QFP package & fabricated using an advanced submicron CMOS process
to achieve low power drain and high-speed requirements.

MCS9835CV-BA is designed to be pin compatible with previous version of MCS9835CV. Existing

designs of MCS9835 can be migrated to MCS9835CV-BA without any modification to system design.
Software compatibility is also maintained between MCS9835 to MCS9835CV-BA.

2. Features
General
• 5V Operation
• Low Power
• Fully compliant with PCI Local Bus Specification 2.3
• Re-map function for Legacy Ports
• Microsoft WHQL Complaint Drivers
• 128 Pin QFP package, RoHS
• Commercial Grade, 0 to 70 deg C
• Advanced testability through scan addition

Serial Port
• Two 16C 450 / 550 compatible UARTs
• Supports RS232, RS485 & RS422 modes
• Bi-directional Speeds from 50 bps to 115200 bps / Port
• Full Serial modem control
• Supports Hardware Flow Control
• 5, 6, 7, 8-bit Serial format support
• Even, Odd, None, Space & Mark parity supported
• On Chip 32 Byte FIFOs in Transmit, Receive paths for both Serial Ports

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IEEE1284 Parallel Port
• Multi-mode IEEE1284 compliant controller (SPP, PS2, EPP, ECP)
• Faster data rates up to 1.5Mbytes/sec for Parallel Port

Miscellaneous
• Four -Wire SPI Interface for EEPROM
• EEPROM read through PCI

3. Applications
• Generic Serial attached devices like Modem & Serial Mouse
• Serial Networking / Monitoring Equipment
• Data Acquisition System
• POS Terminal & Industrial PC
• Parallel / Printer Port based applications
• Add-On I/O Cards – Serial / Parallel
• Embedded systems – For I/O expansion
• Industrial Control

4. Ordering Information
• Part Number : MCS9835CV-BA
• 128 Pin QFP
• ROHS
• Commercial Grade, 0 to 70 o C

5. Application Schematic
• PCI to 2S + 1 Parallel

6. Evaluation Board
• MCS98XXCV-BA EVB – Combo

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7. Software Support
SW Driver Support
• Windows 95/98SE/ME
• Windows 32bit - 2000 /XP /NT /2003 Server
• Windows 64bit XP / 2003 Server
• Windows Vista / 2008 Server (32 & 64 bit)
• Windows 7 (32 & 64 bit)
• Linux Kernel 2.4.X / 2.6.X
• DOS-6.22

SW Utility Support
• Windows XP based Diagnostic Utility
• DOS based diagnostic Utility

8. Certifications
• WHQL Certification of device drivers for Windows XP, Windows Vista & Windows 7
Operating Systems.

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9. Block Diagram

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10. PIN DIAGRAM

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11. Pin Descriptions
This section provides information on each Pin of MCS9835CV-BA

Name Pin # Direction Drive Description

Strength
CLK 122 I 33 MHz PCI System Clock input.

nRESET 121 I(PU) PCI system Reset (active low).Resets all internal
registers, sequencers, and signals to a consistent state.
During reset condition, AD[31-0] and nSERR are tri-
stated.
AD[31-29] 126-128 I/O Multiplexed PCI Address/Data bus.
During the address phase, AD[31-0] contain a physical
address. Data is stable and valid when nIRDY and
nTRDY are asserted (active).

AD[28-24] 2-6 I/O See AD[31-29] description.

AD[23-16] 11-18 I/O See AD[31-29] description.

AD[15-11] 34-38 I/O See AD[31-29] description.

AD[10-8] 40-42 I/O See AD[31-29] description.

AD[7-0] 46-53 I/O See AD[31-29] description.

nFRAME 23 I nFRAME is asserted by the current Bus Master to

indicate the beginning of an transfer. nFRAME
remains active until the last Byte of the transfer
is to be processed.

nIRDY 24 I Initiator Ready.

During a write, nIRDY asserted indicates that the
initiator is driving valid data onto the data bus. During a
read, nIRDY asserted indicates that the initiator is ready
to accept data from the target device.

nTRDY 25 O Target Ready (three-state). Asserted when the target is

ready to complete the current data phase.

nSTOP 27 O Asserted to indicate that the target wishes the

initiator to stop the transaction in progress on the
current data phase.

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Name Pin # Direction Drive Description
Strength
nLOCK 28 I Indicates an atomic operation that may require
multiple transactions to complete.
IDSEL 9 I Initialization Device Select. Used as a chip select
during configuration read and write transactions.
nDEVSEL 26 O Device Select (three-state). Asserted when the target
has decoded one of its addresses.

nPERR 29 I/O Parity Error (three-state).

Used to report parity errors during all PCI transactions
except a special cycle. The minimum duration of
nPERR is one clock cycle.
nSERR 30 O System Error (open drain). This pin goes low when
address parity errors are detected.

PAR 31 I/O Parity.

Even Parity is applied across AD31-0 and nC/BE3-0.
PAR is stable and valid one clock after the address
phase. For the data phase, PAR is stable and valid one
clock after either nIRDY is asserted on a write
transaction, or nTRDY is asserted on a read
transaction.
nC/BE3 8 I Bus Command and Byte Enable. During the address
phase of a transaction, nC/BE3-0 defines the bus
command. During the data phase, nC/BE3-0 are used
as Byte Enables. nC/BE3 applies to Byte “3”.

nC/BE2 22 I Bus Command and Byte Enable. During the address

phase of a transaction, nC/BE3-0 defines the bus
command. During the data phase, nC/BE3-0 are used
as Byte Enables. nC/BE2 applies to Byte “2”.
nC/BE1 32 I Bus Command and Byte Enable. During the address
phase of a transaction, nC/BE3-0 defines the bus
command. During the data phase, nC/BE3-0 are used
as Byte Enables. nC/BE1 applies to Byte “1”.

nC/BE0 43 I/O Bus Command and Byte Enable. During the address
phase of a transaction, nC/BE3-0 defines the bus
command. During the data phase, nC/BE3-0 are used
as Byte Enables. nC/BE0 applies to Byte “0”.

nINTA 120 O PCI active low interrupt output (open-drain). This

signal goes low (active) when an interrupt condition
occurs.

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Name Pin # Direction Drive Description
Strength
EE-CS 115 O 4mA External EEPROM chip select (active high). After
Power-On Reset, the EEPROM is read, and the
read-only configuration registers are filled
sequentially from the first 64 Bytes in the EEPROM.

EE-CLK 116 O 4mA External EEPROM clock.

EE-DI 118 I External EEPROM data input.

EE-DO 117 O 4mA External EEPROM data output.

EE-EN 123 I(PU) Enable EEPROM (active high, internal pull-up). The
external EEPROM can be disabled when this pin is
tied to GND or pulled low. When the EEPROM is
disabled, default values for PCI configuration
registers will be used.
XTAL1 62 I Crystal oscillator input or external clock input pin
(22.1184 MHz).
This signal input is used in conjunction with XTAL2
to form a feedback circuit for the internal timing. Two
external capacitors connected from each side of the
XTAL1 and XTAL2 to GND are required to form a
crystal oscillator circuit.

XTAL2 61 O Crystal oscillator output. See XTAL1 description.

UART_CLK 58 O 4mA Master clock divided by 12 (1.8432 MHz). Standard

UART clock for 115.2Kbps Baud rate.
Reserved 56 O Reserved. No Connection, leave it as NC at system
level.
Reserved 55 O Reserved. No Connection, leave it as NC at system
level.
ACLK 59 I(PU) UART-A clock input. ACLK should be connected to
UART_CLK output pin.

BCLK 57 I(PU) UART-B clock input. BCLK should be connected to

UART_CLK output pin.

TXA 105 O(PU) 12mA UART-A serial Data Output.

nRTSA 107 O(PU) 12mA UART-A Request-To-Send signal.

It is set high (inactive) after a hardware Reset or
during internal Loop-Back mode. When low, this
indicates that UART-A is ready to transfer data. nRTSA
has no effect on the transmitter or receiver.

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Name Pin # Direction Drive Description
Strength
nDTRA 106 O(PU) 12mA UART-A Data-Terminal-Ready signal.
It is set high (inactive) after a hardware Reset or
during internal Loop-Back mode. When low, this
output indicates to the modem or data set that
UART-A is ready to establish a communication link.
nDTRA has no effect on the transmitter or receiver.
RXA 109 I(PU) UART-A, serial Data Input.

nCTSA 111 I(PU) UART-A Clear-To-Send signal.

When low, this indicates that the modem or data set
is ready to exchange data. nCTSA has no effect on the
transmitter.
nDSRA 110 I(PU) UART-A Data-Set-Ready signal.
When low, this indicates the modem or data set is ready
to establish a communication link.

nCDA 112 I(PU) UART-A Carrier-Detect signal.

When low, this indicates the modem or data set has
detected the data carrier. nCDA has no effect on the
transmitter.

nRIA 113 I(PU) UART-A Ring-detect signal.

TXB 76 O(PU) 12mA UART-B serial Data Output.

nRTSB 74 O(PU) 12mA UART-B Request-To-Send signal.

It is set high (inactive) after a hardware Reset or
during internal Loop-Back mode. When low, this
indicates UART-B is ready to exchange data. nRTSB
has no effect on the transmitter or receiver.
nDTRB 75 O(PU) 12mA UART-B Data-Terminal-Ready signal.
It is set high (inactive) after a hardware Reset or
during internal Loop-Back mode. When low, this
indicates to the modem or data set that UART-B is
ready to establish a communication link. nDTRB has
no effect on the transmitter or receiver.

RXB 73 I(PU) UART-B, serial Data Input.

nCTSB 71 I(PU) UART-B Clear-To-Send signal.

When low, this indicates the modem or data set is ready
to exchange data. nCTSB has no effect on the
transmitter.

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Name Pin # Direction Drive Description
Strength
nDSRB 72 I(PU) UART-B Data-Set-Ready signal.
When low, this indicates the modem or data set is ready
to establish a communication link.
nCDB 70 I(PU) UART-B Carrier-Detect signal.
When low, this indicates the modem or data set has
detected the Data Carrier. nCDB has no effect on the
transmitter.

nRIB 69 I(PU) UART-B ring-detect signal.

SLCT 84 I(PU) Peripheral/printer selected (internal pull-up). This pin

is set high by peripheral/printer when it is selected.
PE 87 I(PU) Paper Empty(internal pull-up). This pin is set high by
Peripheral / Printer to indicate Paper Empty condition.

BUSY 85 I(PU) Peripheral/printer Busy (internal pull-up).

This pin is set high by peripheral/printer, when printer
or peripheral is not ready to accept data.

nACK 86 I(PU) Peripheral/printer data Acknowledge (internal pull-up).

This pin is set low by peripheral/printer to indicate a
successful data transfer has taken place.

nFAULT 83 I(PU) Peripheral/printer Data Error (internal pull-up). This

pin is set low by peripheral/printer during an error
condition.

nSTROBE 81 OD_O 12mA Peripheral/printer data Strobe (open drain, active low).
(PU) When low, data is latched into the printer.

nAUTOFDX 80 OD_O 12mA Peripheral/printer Auto Feed (open-drain, active low).

(PU) Continuous auto fed paper is selected when this pin is
set low.

nINIT 79 OD_O 12mA

(PU) Initialize the peripheral/printer (open drain, active
low). When set low, the peripheral/printer starts its
initialization routine.
nSLCTIN 78 OD_O 12mA Peripheral/printer Select (open-drain, active low).
(PU) Selects the peripheral/printer when it is set low.

PD[7-4] 98-95 I/O 12mA Peripheral / Printer bi-directional data bus

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Name Pin # Direction Drive Description
Strength
PD[3-0] 93-90 I/O 12mA Peripheral / Printer bi-directional data bus

Test_Mode_N 67 I(PU) Reserved.

PP_DIR 63 O 4mA For direction control, when used with External

IEEE1284 transceivers. Leave it as “NC” if not used
SCAN_EN 124 I(PD) Reserved.

NC 64,65,68, No Connection
100, 101,
102,103
GND 7,20,21,33, Gnd Power and Signal Ground.
44,45,60,77,
88,94,99,
108,119,125

Vcc 1,10,19,39, Pwr Supply Voltage 5V

54,66,82,89,
104,114

Note: -
I(PU) - Input – Internal Pull Up
I(PD) - Input – Internal Pull Down
O(PU) - Output – Internal Pull Up
OD_O(PU) – Open Drain Output – Internal Pull Up
I/O – Bi-directional Signal
Pwr - Power
Gnd - Ground

12. Architectural overview

Architecture of MCS9835CV-BA is mainly divided in to four parts

• PCI core
• UART core
• Parallel Port core
• EEPROM

12.1 PCI Core

12.1.1 PCI Bus Operation

The execution of PCI Bus transactions take place in broadly five stages: address phase; transaction
claiming; data phase(s); final data transfer; and transaction completion.

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12.1.2 Address Phase

Every PCI transaction starts with an address phase, one PCI clock period in duration. During the address
phase the initiator (also known as the current Bus Master) identifies the target device (via the address) and
type of transaction (via the command). The initiator drives the 32-bit address onto the Address/Data Bus
and a 4-bit command onto the Command/Byte-Enable Bus. The initiator also asserts the nFRAME signal
during the same clock cycle to indicate the presence of valid address and transaction information on those
buses. The initiator supplies the starting address and command type for one PCI clock cycle. The target
generates the subsequent sequential addresses for burst transfers. The Address/Data Bus becomes the
Data Bus, and the Command/Byte-Enable Bus becomes the Byte-Enable Bus for the remainder of the
clock cycles in that transaction. The target latches the address and command type on the next rising edge
of PCI clock, as do all other devices on that PCI bus. Each device then decodes the address and
determines whether it is the intended target, and also decodes the command to determine the type of
transaction.

12.1.3 Claiming the transaction

When a device determines that it is the target of a transaction, it claims the transaction by asserting
nDEVSEL.

12.1.4 Data Phase(s)

The data phase of a transaction is the period during which a data object is transferred between the initiator
and the target. The number of data Bytes to be transferred during a data phase is determined by the
number of Command/Byte-Enable signals that are asserted by the initiator during the data phase. Each
data phase is at least one PCI clock period in duration. Both initiator and target must indicate that they are
ready to complete a data phase. If not, the data phase is extended by a wait state of one clock period in
duration. The initiator and the target indicate this by asserting nIRDY and nTRDY respectively and the
data transfer is completed at the rising edge of the next PCI clock.

12.1.5 Transaction Duration

The initiator, as stated earlier, gives only the starting address during the address phase. It does not tell the
number of data transfers in a burst transfer transaction.

The target will automatically generate the addresses for subsequent Data Phase transfers. The initiator
indicates the completion of a transaction by asserting nIRDY and de-asserting nFRAME during the last
data transfer phase. The transaction does not actually complete until the target has also asserted the
nTRDY signal and the last data transfer takes place. At this point the nTRDY and nDEVSEL are de-
asserted by the target.

12.1.6 Transaction Completion

When all of nIRDY, nTRDY, nDEVSEL, and nFRAME are in the inactive state (high state), the bus is in
idle state. The bus is then ready to be claimed by another Bus Master.

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12.1.7 PCI Resource Allocation
PCI devices do not have “Hard-Wired” assignments for memory or I/O Ports like ISA devices do. PCI
devices use “Plug & Play” to obtain the required resources each time the system boots up. Each PCI
device can request up to six resource allocations. These can be blocks of memory (RAM) or blocks of I/O
Registers. The size of each resource block requested can also be specified, allowing great flexibility. Each
of these resource blocks is accessed by means of a Base-Address-Register (BAR). As the name suggests,
this is a pointer to the start of the resource. Individual registers are then addressed using relative offsets
from the Base-Address-Register contents. The important thing to note is: plugging the same PCI card into
different machines will not necessarily result in the same addresses being assigned to it. For this reason,
software (drivers, etc.) must always obtain the specific addresses for the device from the PCI System.

Each PCI device is assigned an entry in the PCI System’s shared “Configuration Space”. Every device is
allocated 256 Bytes in the Configuration Space. The first 64 Bytes must follow the conventions of a
standard PCI Configuration “Header”. There are several pieces of information the device must present in
specific fields within the header to allow the PCI System to properly identify it. These include the
Vendor-ID, Device-ID and Class-Code. These three fields should provide enough information to allow
the PCI System to associate the correct software driver with the hardware device. Other fields can be used
to provide additional information to further refine the needs and capabilities of the device.

As part of the Enumeration process (discovery of which devices are present in the system) the Base-
Address-Registers are configured for each device. The device tells the system how many registers (etc.) it
requires, and the system maps that number into the system’s resource space, reserving them for exclusive
use by that particular device. No guarantees are made that any two requests for resources will have any
predictable relationship to each other. Each PCI System is free to use its own allocation strategy when
managing resources.

12.1.8 Multi-Function Devices

MosChip uses the Subsystem-ID field to indicate how many Serial Ports and Parallel Ports are provided
by the current implementation. By changing the data in the Subsystem-ID field, and stuffing only the
appropriate number of external components, the same board could be used for products with either one or
two Ports. The least significant Hexadecimal digit of the Subsystem-ID field indicates the number of
Serial Ports that are currently being provided by the device.
The next higher digit indicates the number of Parallel Ports being provided. The table below shows
several different combinations and the types of Ports that would be enabled. Some MosChip devices
provide Serial Ports, some provide Parallel Ports, and some provide both types of Ports. This field is used
as an aid to the software Drivers, allowing them to easily determine how many of each Port type to
configure.

Subsystem-ID Parallel Ports Serial Ports

0001 0 1
0010 1 0
0012 1 2

This use of the term “Multi-Function Device” should not be confused with the more generic use of that
term by the PCI System. Each “Function” within a “Unit” (physical device) gets its own Configuration
Space Header. MosChip’s devices do not need this extra layer of complexity, the six Base Address
Registers provided by one PCI “Function” are more than adequate to allocate all of the desired resources.

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12.1.9 PCI Configuration Space Header
Default values for several key fields are shown in the table below.

AD 31-24 AD 23-16 AD 15-8 AD 7-0 Offset(Hex)

Device ID (9835) Vendor ID (9710) 00
Status Command 04
Class Code (078000) Revision ID (01) 08
BIST Header Type Latency Timer Cache Size (08) 0C
Base Address Register (BAR) 0 – “UART-A” (U1) 10
Base Address Register (BAR) 1 – “UART-B” (U2) 14
Base Address Register (BAR) 2 – “Standard Registers” (Y) 18
Base Address Register (BAR) 3 – “Extended Registers” (W) 1C
Reserved 20
Reserved 24
Reserved 28
Subsystem ID (0012) Subsystem Vendor ID (1000) 2C
Reserved 30
Reserved 34
Reserved 38
Max Latency (00) Min Grant (00) Interrupt Pin (01) Interrupt Line 3C
Reserved Loading Timers 40
EEPROM Register 44
raidreg2 raidreg1 4’h0 Test Bus Sel 16’h9710 48

Internal Address Select Configuration

The MCS9835 uses four Base Address Registers. These essentially act as internal “Chip Select” logic.
Registers are addressed by using one of the Base Addresses plus an offset.

PCI to Dual-Channel UART and a Printer Port

BAR Number Core Module
BAR0 UART 1
BAR1 UART2
BAR2 Standard registers for parallel port
BAR3 Extended registers for parallel port
BAR4 Reserved
BAR5 Reserved

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12.2 UART Core

12.2.1 Overview
There are 2 UARTs in the MCS9835 which are 16C450/16C550 specification. Both UARTs are similar in
operation and functionality, function of one UART described below.
Main features of Serial Port :

• Supports RS232, RS485 & RS422 modes

• Bi-directional Speeds from 50 bps to 115200 bps / port
• Full Serial modem control
• Supports hardware flow control
• 5, 6, 7 and 8 bit serial format support
• Even, Odd, None, Space & Mark parity supported

12.2.2 Operational Modes

The UART is compatible with the 16C450, 16C550 mode of operation.. The operation of the port
depends upon the mode settings, which are described below. The modes, conditions & corresponding
FIFO depth are tabulated below.

UART mode FIFO Size (Bytes) FCR [0]

450 1 0
550 32 1

12.2.3 450 Mode

After the hardware reset, bit 0 of the FIFO Control Register (FCR) is cleared, hence the UART is
compatible with the 16C450 mode of operation. The transmitter & receiver FIFOs (referred to as the
"transmitting Holding register" & "receiver holding register" respectively) have a depth of one byte. This
mode of operation is known "Byte Mode".

12.2.4 550 Mode

After the hardware reset, writing a 1 to FCR [0] will increase the FIFO size to 32, providing compatibility
to 16C550 devices. In 16C550 mode of operation, the device has the following features.

• RTS/CTS hardware flow control

• Deeper FIFOs

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12.3 Parallel Port

In computing, a parallel port is a type of physical interface used in conjunction with a cable to connect
separate peripherals in a computer system. In Parallel Port, binary information is transferred in parallel:
each bit in a particular value is sent simultaneously as an electrical pulse across a separate wire, in
contrast to a serial port, which requires each bit to be sent in series over a single wire. The number of
wires and the type of connector on a parallel port can vary.
The IEEE 1284 standard, which is an extension of the legacy unidirectional parallel port, allows for faster
throughput and bi-directional data flow with a theoretical maximum throughput of 4 Megabits per second,
with actual around 2 Megabits per second depending on hardware. The parallel port, as implemented on
the PC, consists of a connector with 17 signal lines and 8 ground lines. The signal lines are divided into
three groups:

• Control (4 lines)
• Status (5 lines)
• Data (8 lines)

As originally designed, the Control lines are used for interface control and handshaking signals from the
PC to the printer. The Status lines are used for handshake signals and as status indicators to do operations
such as paper empty, busy indication and interface or peripheral errors. The data lines are used to provide
data from the PC to the printer, in that direction only. Later implementations of the parallel port allowed
for data to be driven from the peripheral to the PC also.

Parallel port implemented in MCS9835CV-BA is compliant to IEEE 1284 Standard Parallel Port and
supports various IEEE 1284 modes through hardware. Following are the Parallel modes of operation
supported.

• SPP / Centronics / Compatibility Mode

• Nibble Mode
• Byte Mode (PS/2)
• Enhanced Parallel Port (EPP 1.9)
• Extended Capability Port (ECP) with and without RLE

12.3.1 SPP/Centronics/Compatibility Mode

This mode operates in the forward direction only. The DIR bit is forced to “1” and PD[7:0] are always set
to the output direction. All control signals are under software control. This mode operation is used in most
standard parallel ports on PC’s, for data transfer to printer. Data is placed on the PD[7:0] pins and printer
status is checked via the DSR register. If no error condition is flagged and the printer is not busy, software
toggles the nSTROBE pin to latch the PD[7:0] data into the printer. The printer acknowledges data receipt
pulsing the nACK and BUSY pins.

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12.3.2 Nibble Mode
The Nibble mode is the most common way to get reverse channel data from a printer or peripheral. This
mode is usually combined with the SPP mode to create a bi-directional channel. Printer status bits are
used as nibble bits for the reverse channel data. The same status bits are used for each nibble, so special
handshaking is required. When both nibbles have been received, the PC must combine them to form the
intended byte if data.
Bits used for Nibble Mode:

Pin Data Bit

BUSY Bit-7
PE Bit-6
SLCT Bit-5
nFAULT Bit-4
BUSY Bit-3
PE Bit-2
SLCT Bit-1
nFAULT Bit-0

12.3.3 Byte Mode (PS/2)

The Byte Mode protocol is used to transfer bi-directional data via the PD[7:0] Pins. The FIFO is not used
in this mode. The direction of the port is controlled with the DIR bit in the DCR register. Byte Mode
(PS/2) uses the same handshaking protocol as SPP Mode for data transfer.

12.3.4 Extended Capability Port(ECP)

ECP Mode is an advanced mode for communication with printers or peripherals. A 16-Byte FIFO
provides a high performance bi-direction communication path. The following cycle types are provided in
both the forward and reverse directions.

• Data Cycle
• Command Cycle
• Run-Length-Encoding(RLE)
• Channel Address
Run Length Encoding (RLE) provides data compression of up to 64:1. This is particularly useful for
printers and peripherals that transfer raster images with long strings of identical data. In order for RLE to
be enabled, both the Host and Peripheral must support this feature. Channel addressing supports multiple
logical devices within a single physical unit, like Scanner / Fax / Printer in one physical Package.

12.3.5 Enhanced Parallel Port Mode(EPP)

In EPP Mode several control signals are used for different purposes than those described for the default
SPP & PS/2 Modes. The nSLCTIN line is used as an “ADDRESS STROBE” and nAUTOFDX is used as
the Data Strobe signal. The appropriate strobe signal is automatically generated when data is read or
written to one of the EPP specific registers. The nSTROBE is re-defined to indicate whether the current
transfer is a write or read cycle. Separate I/O addresses are defined for “Data” and “Address” access and
when these locations are used, handshaking is performed automatically by the chip.

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12.3.6 FIFO Test Mode

In this mode the FIFO can be written and read, but no data will be transmitted to the printer. Whatever
data is in the FIFO may be output on the PD[7:0] Pins, but no control signal will be generated to signal a
transfer is to take place. All the status flags are optional in this mode, so the complete operation of the
FIFO can be observed without actually affecting the external device.

FIFO Register(C-FIFO)

Register C-FIFO Register

Name
Description The C-FIFO Mode allows writing data into and reading data back out of the
FIFO without actually transferring any data to the printer.
(i) Fast Centronics (mode =010)- Write only
(ii) ECP mode (mode =011) – Read/Write

Offset 0x00
Permissions R/W

Access --
Condition
Default 8’h00
Value

Bits Description

Bit Name Type Default Functional Description

7:0 CDAT-7:0 R/W 8'b0 C-FIFO register bit [7:0]

12.3.7 Config A/B Enable Mode

This mode must be selected whenever the Config-A or Confi g-B registers are accessed. The Config-
A register uses the same I/O Address as the FIFO Register. Only allowing access to the Configuration
Registers when this special Mode is selected prevents the two registers from interfering with each other.

Configuration ‘A’ register

Register Name Configuration A register

Description Configuration A register (read-only). Reading
this register returns 1001_0100. Writing to this
register has no effect and the data are ignored.
Offset 0x00
Permissions R
Access Condition --
Default Value 8’h94

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Bits Description

Bit Name Type Default Functional Description

In the case of an error, the unsent
1:0 Bit [1:0] R 2'b00
Byte is left in the FIFO.
The Byte currently in the transmitter
2 Bit [2] R 1'b1
Pipeline affects the “FIFO Full” flag.
3 Bit [3] R 1'b0 Reserved
“001”: The Port only accepts 8-bit.
6:4 Bit [6:4] R 3'b001
‘1’: Interrupts are Level-Triggered.
7 Bit [7] R 1'b1

Configuration ‘B’ register

Register Name Configuration B register

Description This register allows software to control the
selecting of interrupts. A read-write
implementation implies a “software-
configurable” device. Reading this register
returns the configured interrupt and interrupt
pin state.
Offset 0x01
Permissions R/W

Access Condition --
Default Value 8’h00

Bits Description

Bit Name Type Default Functional Description

CONFB-
5:0 R/W 6'b0 Interrupt pin select register
5:0
0: Configured printer interrupt pin is low.
6 CONFB-6 R 1'b0
1: Configured printer interrupt pin is high.
‘0’: RLE compression is not supported but RLE
7 CONFB-7 R 1'b0 decompression is supported.

12.3.8 Mode Changes

After a hardware reset, PS/2 mode is selected as the default mode. When changing to a different mode, it
is necessary to select mode 000 or 001 first, then any other desired mode can be selected.

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13. External EEPROM
Data is read from the EEPROM immediately after a Hardware Reset, and the values obtained are used to
update the Configuration before the PCI System first sees the device on the Bus. This allows a OEM
Customers to customize the vendor and product ID’s in place of Moschip ID’s. EEPROM can be used to
arrive at different product combination by setting appropriate sub-system ID’s. For this EE-EN (Pin#123)
to be left as No Connect at system level.

If external EEPROM is disabled by connecting the EE-EN (Pin#123) to ground, after hardware reset
default values of configuration are loaded by the ASIC.
Following are main features of Serial EEPROM Interface :
• Supports Serial EEPROM of 1K Bit Size with 16bit communication capability
• Configuration Space contents can be modified through EEPROM
• Changing configuration values, different modes can be selected
• Inter Character Gap in multiples of 1bit duration can be set for UART-A & UART-B

Following EEPROM types confirmed at MosChip with MCS9835 :

• Atmel AT93LC46B, AT93C46B

• MICROCHIP 93LC46B, 93AA46B, 93AA46C
• ST Micro Electronics M93C46-WMN

13.1 Extended Modes through EEPROM

Mode supported by MCS9835 configuration without using external EEPROM.

• PCI to 2 Serial + 1 Parallel

By using external EEPROM more Peripheral configurations can be derived with MCS9835, few such
configurations listed below:

• PCI to 1 Serial + 1 Parallel

• PCI to 2 Serial
• PCI to 1 Serial

Vendor ID, Product customizations can also be implemented in MCS9835, through external EEPROM.
Any change of Vendor ID, Product ID information requires customized device driver.

Note : EEPROM need to be programmed in external EEPROM burner, for all above configuration
support and for customizations.

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14. EEPROM Contents
Contents of the EEPROM (16-bit), values shown below are for 2S1P Mode
EEPROM HEX Description of Contents EEPROM HEX Description of
ADDRESS Data ADDRESS Data Contents
LOCATION (Word) LOCATION (Word)

0x00 9835 Device ID(changes 0x20 0000

according to mode)
0x01 0000 0x21 0000

0x02 9710 Vendor ID 0x22 0000

0x03 0000 0x23 0000

0x04 0000 {Intr_mask_reg[15:8], 0x24 0000

icg_reg1[7:0]}
0x05 0000 0x25 0000

0x06 0000 0x26 0000

0x07 0000 0x27 0000

0x08 0780 Class code(23-8) 0x28 0000

0x09 0000 0x29 0000

0x0A 0001 {class code (7-0), 0x2A 0000

Revision ID }
0x0B 0000 0x2B 0000

0x0C 0000 Header 0x2C 0012 Subsystem ID

(Changes according
to mode)
0x0D 0000 0x2D 0000

0x0E 0000 0x2E 1000 Subsystem Vendor

ID
0x0F 0000 0x2F 0000

0x10 0000 ICG_reg2[7:0] 0x30 0000

0x11 0000 0x31 0000

0x12 0000 0x32 0000

0x13 0000 0x33 0000

0x14 0000 0x34 0000

0x15 0000 0x35 0000

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EEPROM HEX Description of Contents EEPROM HEX Description of
ADDRESS Data ADDRESS Data Contents
LOCATION (Word) LOCATION (Word)
0x16 0000 0x36 0000

0x17 0000 0x37 0000

0x18 0000 0x38 0000

0x19 0000 0x39 0000

0x1A 0000 0x3A 0000

0x1B 0000 0x3B 0000

0x1C 0000 0x3C 0000 {Max_lat[7:0],

Min_gnt [7:0]}
0x1D 0000 0x3D 0000

0x1E 0000 0x3E 0100 Interrupt Pin

0x1F 0000 0x3F 0000

EEPROM Data Configuration Values

Description EEPROM Address Location Word/Byte Data

Device ID 0x00 9835

Vendor ID 0x02 9710

Class code 0x08 0780

Class code Interface 0x0A (Most Significant Byte) 00

Revision ID 0x0A (Least Significant Byte) 01

Header 0x0C 00
(Least Significant Byte)
Subsystem ID 0x2C 0012

Subsystem Vendor ID 0x2E 1000

Interrupt pin 0x3E (Most Significant Byte) 01

Icg_reg1[7:0] 0x04(Least Significant Byte) 00 (This value is used to put
Inter Character Gap setting the delay between each
register for UART-A character).
Icg_reg2[7:0] 0x10(Least Significant Byte) 00 (This value is used to put
Inter Character Gap setting the delay between each
register for UART-B character).
Intr_mask_reg[15:8] 0x04(Most Significant Byte) 00

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Icg_reg1 & 2 : Inter Character Gap register is used to set Inter Character Gap in multiples of 1bit
duration for UART-A & B Ports

Intr_mask_reg[15:0] : Interrupt Mask Register can be used to mask the interrupt from unused Serial or
Paralle ports.

Register(bit) Value(Default Description

for 2S+ 1P)
Intr_mask_reg[8] 0 UART-A Interrupt Mask register. By setting
this bit to “1” interrupts can be disabled from
this Port.
Intr_mask_reg[9] 0 UART-B Interrupt Mask register. By setting
this bit to “1” interrupts can be disabled from
this Port.
Intr_mask_reg[11] 0 Parallel Port Interrupt Mask register. By setting
this bit to “1” interrupts can be disabled from
this Port.

The EEPROM controller reads the least significant byte and then the most significant byte in the 16-bit
format. Therefore, when writing to each address in the EEPROM, the least significant byte must be
written first, followed by the most significant byte. For example, to write 9835 into address 0x00, the
value would be written as 35 98, where 35 is the least significant byte and is written first.

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15. Electrical Specifications
Absolute Maximum Ratings
Supply Voltage 6 Volts
Voltage at any pin GND - 0.3 V to VCC + 0.3 V
Operating Temperature 0 °C to +70 °C
Storage Temperature -40 °C to +150 °C
ESD HBM (MIL-STD 883E Method 3015-7 Class 2) 2000V
ESD MM (JEDEC EIA/JEDS22 A115-A) 200V
CDM (JEDEC JEDS22 C101-A) 500V
Latch up (JESD No. 78, March 1997) 200 mA, 1.5 x Vcc

Recommended Operating Conditions

Symbol Parameter Min Typ Max Unit Condition

Vcc Supply Voltage 4.75 5 5.25 V

Vin Input Voltage 0 Vcc

Icc Operating Current 70 mA No Serial Load

DC Electrical Characteristics : Ta = 0 to +70 °C, VCC = 4.75 to 5.25 V unless otherwise specified.

Symbol Parameter Min Typ Max Unit Condition

ViL Input Voltage (Low) 0.3 *Vcc V CMOS

ViH Input Voltage (High) 0.7 *Vcc V CMOS
ViL Input Voltage (Low) 0.8 V TTL
ViH Input Voltage (High) 2.0 V TTL
Vt- Schmitt Trigger 1.84 V CMOS
Negative-Going Threshold Voltage
Vt+ Schmitt Trigger 3.22 V CMOS
Positive-Going Threshold Voltage
Vt- Schmitt Trigger 1.10 V TTL
Negative-Going Threshold Voltage
Vt+ Schmitt Trigger 1.87 V TTL
Positive-Going Threshold Voltage
VoL Output Voltage (Low) 0.4 V IoL = 2 to 24 mA
VoH Output Voltage (High) 3.5 V IoH = 2 to 24mA
Ri Input Pull-Up/Pull-Down 50 KΩ ViL = 0V or
Resistance ViH = Vcc

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16. Mechanical Specifications – QFP 128

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17. Contact information
For Commercial information & availability write to : [email protected]

For Technical information write to : [email protected]

Revision history

Date Reason for change Version

16th Dec 2007 Initial release 0.1

1st May 2008 “Tentative Data Sheet” text removed in all pages & 1.0
document version changed to 1.0
9th March 2010 SW Support updated for Windows 7 and WHQL 1.1
drivers availability

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