Scribd
Upload
281 views

Assignment 3 Computer Organization & Architecture

This document contains questions related to computer organization and architecture. It covers topics like memory organization, cache memory, RAM, ROM, virtual memory, and addressing schemes. There are short 2-mark questions as well as longer 6, 10, and 16-mark questions involving concepts like memory mapping, cache replacement algorithms, and calculating access times. The questions require analyzing memory systems and determining parameters like chip counts, address mappings, page tables and cache configurations.

Uploaded by

Himanshu Gupta
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
281 views

Assignment 3 Computer Organization & Architecture

This document contains questions related to computer organization and architecture. It covers topics like memory organization, cache memory, RAM, ROM, virtual memory, and addressing schemes. There are short 2-mark questions as well as longer 6, 10, and 16-mark questions involving concepts like memory mapping, cache replacement algorithms, and calculating access times. The questions require analyzing memory systems and determining parameters like chip counts, address mappings, page tables and cache configurations.

Uploaded by

Himanshu Gupta
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

Computer Organization & Architecture

RCS-302
CSE 3rd Semester

2 mark questions
Q1 What is the smallest addressable unit in main memory? What are the other addressable units in
memory? Define them.
Q2 If a byte is stored at address $1000, can a word be stored adjacent to it? If the byte is stored at
address $1001, does it change your answer? If so, for what reason?
Q3 A byte organized memory chip with 11 bit address bus is used as a building block in a larger
memory organization.
(i) Calculate the capacity of the above chip.
(ii) If the above chip is used to build a 64 KB long word organized (32 bit) memory, calculate the
number of chips needed.
(iii) Specify the new Memory Address map, and the Memory Connections to the CPU for this new 32-
bit word-organized memory with 11-bit address bus.
Q4 Difference between primary memory and secondary memory. Explain MDR and MAR.
Q5 Cache memory is organized on what basis. List the advantages of using Cache memory
Q6 Differences between static RAM and dynamic RAM. Differentiate between synchronous DRAM
and Asynchronous DRAM.

6 mark questions
Q7 Explain different mapping procedures in organization of cache memory with diagram?
Q8 Explain about the cache replacement algorithms? Discuss the memory hierarchy in a computer
system with regard to speed, size and cost?
Q9
a. How many 128 x 8 RAM chips are needed to provide a memory capacity or 2048 bytes?
b. How many lines of the address bus must be used to access 2048 bytes of memory? How many of
these lines will be common 10 all chips?
c. How many decoder lines must be decoded for chip select? Specify the size of the decoder.
Q10 A computer employs RAM chips of 256 x 8 and ROM chips of 1024 x 8. The computer system
needs 2K bytes of RAM, 4K bytes of ROM, and four interface units, each with four registers. A
memory-mapped 1/0 configuration is used. The two highest-order bits of the address bus are assigned
00 for RAM, 01 for ROM, and 10 for interface registers.
a. How many RAM and ROM chips are needed?
b. Draw a memory-address map for the system.
c. Give the address range in hexadecimal for RAM, ROM, and interface.
Q11 A magnetic disk system has the following parameters:
Ts = average time to position the magnetic head over a track
R = rotation speed of disk in revolutions per second
Ni = number of bits per track
Ns = number of bits per sector
Calculate the average time T. that it will take to read one sector.

10 marks questions
Q12 A two way set associative cache memory uses blocks of 4 words. The cache can accommodate a
total of 2048 words from memory. The main memory size is 128K * 32.
a. Formulate all pertinent information required to construct the cache memory.
b. What is the size of cache memory?
Q13 A digital computer has a memory unit of 64K x 16 and a cache memory of 1K words. The cache
uses direct mapping with a block size of 4 words.
a) How many bits are there in the tag, index, block and word fields of the address format.
b) How many bits are there in each word of the cache, and how are they divided into functions?
Include the valid bit.
c) How many blocks can the cache accommodate?
Q14 The access time of a cache memory is 100 ns and that of main memory is 1000 ns. It is estimated
that 80% of the memory requests are for read and the remaining 20% are for write. The hit ratio for
read accesses only is 0.9. A write-through procedure is used.
a) What is the average access time of the system considering only memory read cycles?
b) What is the average access time of the system for both read and write requests?
c) What is the hit ratio taking into consideration the write cycles?
Q15 A virtual memory system has an address space of 8K words, a memory space of 4K words, and
page and block sizes of 1K words. The following page reference changes occur during a given time
interval. (Only page changes are listed. If the same page is referenced again, it is not listed twice.)
4 2 0 1 2 6 1 4 0 1 0 2 3 5 7
Determine the four pages that are resident in main memory after each page reference change if the
replacement algorithm used is
a. FIFO
b. LRU
Q16 The main memory of a computer is organized a s 64 blocks with a block size of 8 words. The
cache has 8 block frames.
a. Find the main memory address bits that identify the tag field, block number and the word
number if direct address mapped cache is used
b. Find the main memory address bits that identify the tag field and the word number if fully
associative cache is used.
c. Find the main memory address bits that identify the tag field, the set number and the word
number if two-way set associative cache is used.

You might also like