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VHDL Modeling and Synthesis of Sequential Logic Design: ELEC 4200

This document provides an overview, pre-lab assignment, lab exercise, and questions for a lab on VHDL modeling and synthesis of sequential logic design. The lab has students write a VHDL model for a finite state machine from a previous lab, simulate and verify it in ModelSim, synthesize it for an FPGA, and compare pre- and post-synthesis simulations to observe timing delays introduced during implementation. Students are asked to report their VHDL models, simulation results, FPGA resource usage, logic equations, and answers to questions about the impact of place and route on maximum clock frequency.

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44 views6 pages

VHDL Modeling and Synthesis of Sequential Logic Design: ELEC 4200

This document provides an overview, pre-lab assignment, lab exercise, and questions for a lab on VHDL modeling and synthesis of sequential logic design. The lab has students write a VHDL model for a finite state machine from a previous lab, simulate and verify it in ModelSim, synthesize it for an FPGA, and compare pre- and post-synthesis simulations to observe timing delays introduced during implementation. Students are asked to report their VHDL models, simulation results, FPGA resource usage, logic equations, and answers to questions about the impact of place and route on maximum clock frequency.

Uploaded by

ILikeScribd5050
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Sequential

Logic Design

ELEC 4200

Overview

Pre-lab

Lab

Questions &
VHDL Modeling and Synthesis of Sequential
Report
Logic Design

ELEC 4200

Auburn University

September 26th , 2011


Sequential
Logic Design Overview
ELEC 4200
• Write a VHDL model for the FSM from
Overview
Lab 2
Pre-lab
• Use the same specifications as Lab 2
Lab
• Make sure it includes the digital
Questions &
Report one-shot
• Use any valid sequential and
concurrent statements
• DO NOT use the Boolean equations
from Lab 2
• Simulate and verify design using
ModelSim, debugging as needed
• Synthesize, download, and verify design
Spartan3 FPGA
Sequential
Logic Design Pre-lab Assignment
ELEC 4200

Overview

Pre-lab

Lab

Questions &
Report

1 Write a VHDL model for you design using the same


specifications as the design for Lab 2
• Be sure to include the digital one-shot
2 Read “Overview of FPGA Editor” (3 pages) from lab web
page
Sequential
Logic Design Lab Exercise
ELEC 4200

Overview

Pre-lab
1 Simulate your VHDL and verify your design using
Lab
ModelSim, debug as necessary
Questions &
Report 2 Synthesize, download, and verify your design in the
Spartan3 FPGA using ISE
• Open the synthesis report file and record the number of
LUTs, FF/latches, slices, and maximum clock frequency
• Open your design in FPGA Editor and find the FFs for
your FSM, record the logic equations of the LUTs driving
these two FFs
3 Demonstrate your working circuit to your GTA

IMPORTANT
Save this VHDL model as you will be using it in the future
Sequential
Logic Design Lab Exercise continued
ELEC 4200

Overview

Pre-lab

Lab

Questions &
Report
4 Click and run the submenu under Place & Route menu
• Generate Post-Place and Route Simulation Model
5 Simulate this model
• The model can be found in the netgen/par subdirectory
6 Compare timing delays to original VHDL simulation
• This represent the delays in the actual FPGA
implementation
Sequential
Logic Design Questions
ELEC 4200

Overview 1 What is the difference between the ideal simulation and


Pre-lab the post place and route simulation?
Lab
2 How does this affect the maximum clock frequency?
Questions &
Report

Report Guidelines

1 Verfied VHDL models


2 Screenshot of your ModelSim simulation results
3 Number of LUTs, FF/latches, slices, and maximum clock
frequency
4 Logic Equations from FFs
5 Post Place and Route simulation observations
6 All of your pre-lab work
7 Answers to questions

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