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Low voltage analog circuit design techniques

Article  in  IEEE Circuits and Systems Magazine · September 2002

DOI: 10.1109/MCAS.2002.999703 · Source: IEEE Xplore

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 Low Voltage
Analog Circuit
Design Techniques
by S. S. Rajput and S. S. Jamuar

Abstract—Analog signal processing is fast and can address real world prob-
lems. The applications of battery powered analog and mixed mode electronic
devices require designing analog circuits to operate at low voltage levels. In this
paper, some of the issues facing analog designers in implementing low voltage
circuits are discussed, and possible low voltage design techniques are examined.
We do not intend to present a review of state-of-the-art technology, but we do
describe briefly almost all low voltage design techniques suitable for analog
circuit structures along with their merits and demerits.

weight. Solar power, fuel cells, RF

Introduction power, and so forth, are the most vi-

T he desire for portability of elec-

tronic equipment generated a
need for low power systems in battery-
able alternatives [1]. The biggest issue
that must be considered with these
power sources is their low voltage lev-
operated products like hearing aids, els. The voltage of a single solar cell
implantable cardiac pacemakers, cell- is about 0.5V (even lower for other
phones, and hand held multimedia ter- sources), which is well below the
minals. Low power dissipation is at- nominal voltage of dry cells or even
tractive, and perhaps even essential in their end-of-discharge values (0.9V).
these applications to have reasonable The design of integrated circuits (ICs)
battery life and weight. The ultimate capable of working with solar cells
goal in design is close to having bat- offers a wide range of possibilities in
tery-less systems, because the battery portable signal processing instruments.
contributes greatly to volume and But integrated circuits require much

1531-636X/4/$10.00©2002IEEE

24
higher voltages for their operation. A sign, and the circuit performance may
possible solution to get higher dc volt- degrade. Simple circuits, which have
age on-chip is voltage multiplication. fewer MOSFETs, will have minimum
This technique is noisy and not com- stray and device capacitances and are ex-
patible with sensitive analog circuits. pected to perform better. It is desirable
Furthermore, analog designers would to have efficient and simple circuit struc-
have the additional burden of taking tures for low voltage operations [2].
care of Power Supply Rejection (PSR) Low voltage analog circuit design
in these circuits, an issue usually dis- techniques differ considerably from
regarded in battery-powered equip- those of high voltage analog circuit
ment. Increasing demands of such design. This generates a need for ad-
products obviously encourage research aptation of alternative design tech-
and development efforts in designing niques to suit the low voltage environ-
and perfecting low voltage circuits ments. The current mode approach
with low power consumption. proves a better alternative for low volt-
Circuit operation at reduced volt- age high performance analog circuit
ages is a common practice adopted to design in which the circuit designer is
reduce power consumption. However, more concerned with current levels for
the circuit performance degrades and the operation of the circuits. The volt-
one gets low circuit bandwidth and age levels present at various nodes are
voltage swings at low voltages. Scal- immaterial.
ing down the threshold voltage of This paper is aimed at providing a
MOSFETs compensates for this per- comprehensive treatment of all pos-
formance loss to some degree, but this sible low voltage design techniques
results in increased static power dissi- prevalent today for analog circuits. The
pation. Analog circuits benefit margin- selection criteria along with their merits
ally from scaling, as the minimum size and demerits have been presented.
transistors cannot be used in analog
circuits because of noise and offset Analog Signal Processing
voltage constraints. However, scaling Analog signal processing (ASP)
results in better performance in digi- has gone through a dramatic change in
tal circuits [2]. the last decade and is an essential ele-
Furthermore, heat removal and in-
ternal power distribution pose major
problems in the growth of CMOS cir- Analog signal processing (ASP) has gone
cuits. The cost of heat removal (i.e. through a dramatic change in the last decade
cooling) has resulted in significant in- and is an essential element in real time signal
terest in power reduction even in non-
portable applications [2]. But, low processing applications because all physical
voltage operation complicates the de- phenomena are analog in nature. Advances in
technology, increased market demands, and
S. S. Rajput is with the National Physical
Laboratory, Dr. K. S. Krishnan Road, New Delhi,
sophisticated and innovative information pro-
India. Email: [email protected]
S. S. Jamuar is with the Department of Elec-
cessing applications have motivated renewed
trical Engineering, Indian Institute of Technology, interest in analog system design.
New Delhi, India.

25
 ment in real time signal processing have high voltage swings. For better
applications because all physical phe- signal to noise ratio (SNR), higher sup-
nomena are analog in nature. Ad- ply voltages are required [7].
vances in technology, increased mar- If the input and output signals are
ket demands, and sophisticated and currents, some of the above demerits
innovative information processing ap- could be eliminated. In current mode
plications have motivated renewed in- circuits (CMCs), the currents deter-
terest in analog system design. The in- mine the complete circuit response.
terdisciplinary view of VLSI is par- The voltage signals are irrelevant in
ticularly important for analog design determining the circuit performance.
because VLSI technology and CAD The sensitive nodes inside CMCs are
tools have been developed primarily low impedance nodes, where the re-
for digital VLSI design. If we have sultant voltage swings are also small.
analog cells as in digital system design This results in low time constant cir-
then the analog systems can also be cuits with high bandwidth. The slew
designed like digital systems. This will rate for CMCs is also high. CMCs have
make the design process simpler. Field simple architectures and are suitable
programmable analog arrays (FPAA) for integration in CMOS technology.
[3], configurable and modular analog Analog circuits should have rail-
circuits [4, 5], fall in this category. Ana- to-rail input and output voltage swing
log VLSI has tremendous potential for capability. Many conventional circuit
addressing real world problems [6]. topologies have been replaced by new
The behavior of electrical circuits innovative design. Simple CMC struc-
is always the result of interplay be- tures, especially those circuits that are
tween voltage and current. All conven- capable of operating at low voltages
tional analog circuits like operational [2], have been invented. A most impor-
amplifiers (op amps) are voltage mode tant and common CMC structure is the
circuits (VMCs). They suffer from the current conveyor (CC) introduced in
drawback that the output voltage does 1968 [8].
not change instantly, due to stray and
circuit capacitances, when there is a Critical Issues
sudden change in the input voltage. The speed and bandwidth of ana-
The bandwidth of VMCs is usually log circuits depend strongly on circuit
low. The slew rate (SR) is also not very capacitances, which arise partly be-
high. VMCs are not suitable for use in cause of MOSFET intrinsic capaci-
high frequency applications and do not tances and partly because of intercon-

S. S. Rajput received the B.E. in electronics and communication engineering and the M. E. in
solid state electronics engineering from University of Roorkee, India, (Now Indian Institute of Tech-
nology, Roorkee) in 1978 and 1981, respectively, and was awarded the University gold medal in 1981.
He joined National Physical Laboratory, New Delhi, India, as Scientist B in 1983, where he is presently
serving as Scientist EII. He has worked for the design, development, testing and fabrication of an in-
strument meant for space exploration under the ISRO-NPL joint program for development of scientific
instruments for the Indian Satellite SROSS-C and SROSS-C2 missions. His research interests include
low voltage analog circuit design, instrument design for space applications, digital signal processing
applications, fault tolerant design, and fault detection. He joined the Ph.D. program of Indian Institute
of Technology, Delhi, under the supervision of Professor S. S. Jamuar and submitted a thesis on low
voltage current mode analog circuit structures and their applications. He has more than 20 publications
in national and international journals

26
nect parasitic capacitances. In deep power due to non-zero current of
sub-micron technologies, interconnect MOSFETs in the OFF state in digital
capacitance dominates; and simple re- circuits or biasing current in analog cir-
duction of the transistor sizes will not cuits, and the short-circuit power due
have a proportional impact in band- to current flowing during the lapse of
width improvement. This is due to time when both PMOS and NMOS
higher aggressiveness of device scal- transistors are in the on state.
ing in comparison with interconnect The total power (PTOTAL) consump-
scaling. As die sizes are also getting tion of a circuit can be approximated
larger, correspondingly longer wiring as the sum of NC eq V 2 DD and
lengths worsen the distributed RC de- I offVDD.Thus the main interest is to
lays and susceptibility for substrate minimize PTOTAL and the obvious way
noise coupling, cross talk and other to reduce it would be to operate the cir-
phenomena. cuits at low supply voltages (VDD).
Voltage reductions guarantee the
reliability of devices as the lower elec- Low Voltage Design
trical fields inside oxide layers of a Applications do exist where it is
MOSFET produce less risk to the thin- crucial that current levels are ex-
ner oxides, which result from device tremely small and supply voltage be
scaling. Thus one of the solutions of also low. These applications include
all the problems lies in the adoption of low voltage circuits in biomedical en-
low voltage techniques in analog cir- gineering and mobile communication,
cuit designs so that these MOSFETs by way of example.
can operate at low voltage levels. At low voltage, the main con-
Today’s design strategies are di- straints faced are the device noise level
rected toward achieving higher speed and the threshold voltage (VT). Reduc-
and large dynamic range. One of the tion in VT is dependent on the device
factors which affects these parameters technology. Higher VT gives better
is power dissipation in the circuit. So noise immunity and the lower VT re-
it is essential to identify the agents of duces the noise margin to result in poor
power consumption and minimize SNR. Hence, for present day CMOS
them. There are three main compo- technology, reduction in VT is limited
nents of power dissipation in any cir- to the noise floor level, below which
cuit, namely, dynamic power caused further reduction will introduce an
by charging and discharging of (usu- amount of noise sufficient to result in
ally parasitic) capacitance, static very complex circuits. The restriction

S. S. Jamuar was born on November 27, 1949. He received the B.Sc. Engineering Degree in elec-
tronics and communication from Bihar Institute of Technology, Sindri, in 1967, and the M.Tech and
Ph.D. degrees in electrical engineering from Indian Institute of Technology, Kanpur, India, in 1970 and
1977, respectively. He worked as research assistant, senior research fellow and senior research assistant
between 1969 and 1975 at IIT Kanpur. During 1975–76, he was with Hindustan Aeronautics Ltd.,
Lucknow. Subsequently he joined the Lasers and Spectroscopy Group in the Physics Department at IIT
Kanpur, where he was involved in the design of various types of laser systems. He joined IIT Delhi in
1977. Presently he is professor in the Department of Electrical Engineering at IIT Delhi since 1991. His
area of interest includes electronic circuit design, instrumentation and communication systems. He was
recipient of Meghnad Saha Memorial Award from IETE in 1976 and the Distinguished Alumni Award
from BIT Sindri in 1999. Dr. Jamuar is senor member of IEEE and Fellow member of IETE (India).

27
 cuits are available, for instance,
MOSFETs operating in the sub-thresh-
old region [6, 9–14], bulk driven tran-
sistors [9, 10, 12–15], self-cascode
VDG ID structures [9, 12, 13], floating gate ap-
proach [6, 9, 16–21] and the level
IG shifter techniques [9, 12, 22–27]. Use
of low voltage high performing build-
VDS ing blocks in low voltage analog cir-
cuits is another promising approach
and yields a modular design concept in
analog circuits as well [9, 13]. We will
VGS briefly look into these techniques.
Sub-Threshold Circuits
Circuits operating in the sub-
threshold region have gained impor-
Figure 1. A MOSFET model. tance in recent years because of the
need for low voltage and low power
battery powered circuits in human im-
on further reduction in VT paves the plantable biomedical instruments.
way to have simpler, smarter and effi- When the applied drain source
cient circuits [2]. Many new design voltage in a MOSFET (Fig. 1) exceeds
techniques for low voltage analog cir- the threshold voltage, the drain current

V in VB

I in I out

M1 M2

V GS1 VGS2
V SS

Figure 2. Current mirror (CM) based on sub-threshold MOSFETs.

28
 -0.4

Input voltage in volts

-0.6

-0.8

-1.0
0 200 400 600 800 1000
Input current in nA
Figure 3. Input voltage characteristics of the CM.

in the sub-threshold region [26] is where n is the sub-threshold slope fac-

given by tor and lies between 1.2 and 2. Param-
K' W  V DS  eters q, k, VTN, and T represent the elec-
I DS = (V − V ) − V DS (1)
L  2  tronic charge, Boltzman constant,
GS T

threshold voltage of NMOSFET and

and the drain current is zero when
temperature respectively.
VDS < VT.
In sub-threshold region, MOSFETs
This model was derived for small
have low saturation voltages
values (both positive and negative) of
(≈ 100mV). This gives larger voltage
VDS, which correspond to the ohmic
swings at low-supply voltage even in
region of operation. In the above equa-
cascaded MOSFET structures. Similar
tion W, L, and K’ (µCox) represent the
to a bipolar transistor, the trans-con-
channel width, channel length and
ductance (gm) equals (q IDS / nkT) and
trans-conductance parameter respec-
is expected to be large. However, it
tively. The drain current (IDS) is as-
may be noted that the current IDS itself
sumed to be zero for VGS < VT and non-
is low in sub-threshold region, and gm
zero for VGS > VT. In a physical device,
cannot be high as in the case of bipo-
such an abrupt change does not occur.
lar transistors.
IDS is, however, much smaller for VGS
As an example the circuit diagram
< VT than for VGS > VT and is attributed
of a CM based on sub-threshold
to diffusion in the region (VGS < VT,
MOSFETs is shown in Fig. 2, which
known as the sub-threshold region). In
is similar to any conventional CM. The
the sub-threshold region IDS is given by
simulated output current characteris-
[6, 11, 13, 26, 27]
tics of the CM are shown in Fig. 3.
2
2K' W  nkT   q(VGS − VTN )  Though these characteristics are simi-
  exp  (2) lar to any conventional CM, the re-
L  qe  nkT
29
 1.2
I in = 1.0 µA
1.0
Output current in micro amp

I in = 0.8 µA
0.8
I in = 0.6 µA
0.6
I in = 0.4 µA
0.4
I in = 0.2 µA
0.2

0.0
-1.0 -0.5 0.0 0.5 1.0
Applied voltage in volts
Figure 4. Output current voltage characteristics of the CM.

quired input compliance voltage is 12–15] for low voltage analog circuits.
only a few hundred millivolts (≈ 500mV For a MOSFET to perform any signal-
for a current of 1µA). This compliance processing task, there should be some
voltage can further be decreased if we biasing current through its drain. This
use the level shifter technique dis- biasing current in a conventional gate
cussed later. The current voltage char- driven MOSFET comes when the ap-
acteristics are shown in Fig. 4, which is plied gate bias overcomes the thresh-
quite similar to any conventional CM. old voltage. However, in the bulk
There are several limitations of driven technique shown in Fig. 5, a
devices operating in sub-threshold re- MOSFET is biased in saturation mode
gion. First, the frequency response of so as to have a continuous drain cur-
devices is poor. Second the drain and
source substrate currents associated
with the reverse biased moat-substrate VDD
junction are not necessarily negligible
compared to sub-threshold drain cur-
rent. Third, the linearity is quite poor M
for VDS < 3Vther (Vther = kT / q). This
makes the low voltage circuit design
V in
quite complicated. Further, these cir-
cuits are meant for very low currents
and are not suitable for medium power
instruments.
Bulk-Driven MOSFETs VSS
Blalock et al. have adopted the bulk Figure 5. Bulk-driven MOSFET structure.
driven MOSFETs technique [9, 10,

30
 V DD

Bulk Source Drain

n+ n Channel n+

p Substrate

Figure 6. JFET equivalent of bulk-driven MOSFET.

rent; and the input signal is applied at bulk driven n-type MOSFETs. The
the bulk contact. A close look at bulk structure of the current mirror re-
driven MOSFETs suggests that the sembles a conventional mirror, where
bulk driven MOSFET structure acts M1 and M2 are used in the conven-
similarly to a JFET. The resultant JFET tional way except that the gate of both
is shown in Fig. 6. Because of the ap-
plied gate voltage, a channel exists
between the source and drain of the VDD
MOSFET. The channel width is con-
stant as long as gate bias does not
change as the case is for bulk-driven
MOSFETs. The bulk contact serves the
function of the gate of the virtual JFET I DSS I DSS
and modulates the channel width ac-
cording to the applied voltage. Thus I in I out
the bulk driven MOSFET operates as
a depletion type device; and it can
work with negative, zero or slightly
positive bias voltages also. The other
major advantages offered by bulk VB VB
driven MOSFETs are their large volt- M1 M2
age ON/OFF ratio, which can be used
for modulation.
We take the example of a simple
current mirror shown in Fig. 7 to ex- VSS
plain the functionality of the bulk Figure 7. CM based on bulk-driven MOSFETs.
driven devices. This circuit utilizes

31
 Low Voltage
Analog Circuit
Design Techniques
as simple depletion type n-JFETs,
where the bulk of the device serves as
the gate for the JFET. The equivalent
circuit of the bulk-driven MOSFET
I in I out based current mirror is shown in Fig. 8,
which is similar to any conventional
CM with similar input output charac-
teristics. The required input compli-
ance voltage is sufficiently low in this
M1 case and is about VT.
M2 Another example of bulk-driven
MOSFET based circuit structure is a
differential pair, as shown in Fig. 9 [9,
10, 12–15]. The circuit operation can
easily be understood if we again con-
sider bulk driven MOSFETs as JFETs
(Fig. 10).
V SS The bulk driven technique re-
moves the threshold voltage require-
Figure 8. JFET equivalent circuit of CM based on bulk-driven MOSFETs. ments, and these devices can work
even at 0.9V (for VT ≈ 0.8V). However
the foremost disadvantage of the bulk
M1 and M2 are tied to positive supply driven technique requires all the
in this configuration. The currents MOSFETs to have isolated bulk termi-
through the MOSFETs M1 and M2 are nals. Other disadvantages of the bulk
equal to drain saturation current, and driven technique for low voltage cir-
are supplied by two current sources as cuit applications are as follows.
shown in the figure. The input current I. gm of a bulk driven MOSFET is
is injected into the input port formed substantially smaller than a gate
at the drain of M1. This current can driven MOSFET, and the two
only flow through the drain of M1 bandwidths are related as [9, 10,
when the width of the MOSFET (M1) 12–15]:
channel changes. The channel width η
fT, bulk – driven ≈ fT, gate – driven (3)
can either change by changing the gate 3.8
bias (which is now fixed and tied to where η is the ratio of gmb to gm and
positive supply voltage) or by modu- typically has a value in the range
lation of channel through the bulk. It of 0.2 to 0.4.
may be noted that the MOSFETs act II. The polarity of the bulk-driven

32
 Current mirror
I out I in

Vb
M1 M2
MOSFETs is process related. For V i+ V i–
P-well process, only N-channel
bulk driven MOSFETs are avail-
able, and for N-well process, only
P-channel MOSFETs are avail-
able. Thus, bulk-driven MOSFETs
cannot be used in CMOS struc- I bias
tures where both N and P type
MOSFETs are required.
III. Bulk driven MOSFETs are fabri-
cated in differential wells to have
isolated bulk terminals and the
matching between bulk-driven Figure 9. Differential pair based on bulk-driven MOSFETs.

MOSFETs in differential wells

suffers. Thus analog circuits with
tight matching between MOSFETs
are difficult to fabricate.
IV. There is a likelihood to have latch
up problems because of potential
Current mirror
turning ON of the parasitic BJT. I out I in
Self-Cascode Approach
As device sizes are shrinking, the
output impedance of the MOSFET is
also becoming smaller because of M1 M2
V i+ V i–
channel length modulation. For high
gain, one needs high output impedance
of the devices, and short channel
MOSFETs cannot provide high gain
structures. To obtain high output im-
pedance, one uses cascode structure as I bias
shown in Fig. 11, where two
MOSFETs are placed one above the
other [9, 12–14]. The use of cascode
structure increases the gain but it de-
creases the output signal swing at the
same time. The output signal swing Figure 10. JFET equivalent circuit of the circuit shown in Fig. 9.
reduces at least by one VT if used in the

33
 Figure 11. A cascode CM.

Iin Iout

used in low voltage systems [9, 12–14].

M4 M3 If this circuit is modified in such a
way that the biasing of the transistor
M2 does not affect the output voltage
swing, the output impedance of the
structure can be increased to have high
M1 gain structures at low voltage levels.
M2 This is achieved by having an indepen-
dent biasing for M2 as shown in
Fig. 12 [12]. Although high gain is pro-
vided by the structure shown in Fig. 12
it uses a large number of transistors
increasing the silicon area. Thus there
V SS
is interest in alternative schemes. An-
other possibility is to use the same gate
design of current mirrors. This decrease bias for both M1 and M2. Because the
in the output voltage is due to the struc- gate biasing is the same, it is called a
ture followed in the design of cascode self-cascode structure. A self-cascode
biasing. Because VT is of the order of does not require high compliance volt-
0.75V, cascode structures cannot be ages at output nodes and provides high

Figure 12. Independent biasing for

MOSFET used in cascode.
Iin Iout Iref

M4
M3

M1
M2

V SS

34
 D

ID2
M2 D
output impedance to give high output m W/L
gains. This approach has potential ap- ID
plications in low voltage design.
A self-cascode is a 2-transistor
structure as shown in Fig. 13 (a). This G V GS2 X G
structure can be treated as a single ID1
composite transistor as shown in
Fig. 13 (b). The composite structure has M1 W/L VX V GS
much larger effective channel length and
the effective output conductance is VGS1
much lower. The lower transistor M1
is equivalent to a resistor whose value S
is input dependent. For optimal opera- S
tion, the W/L ratio of M2 is kept larger (a) (b)
than that of M1, that is, m > 1. For the
composite transistor, the effective
transconductance (gm(effective)) will Figure 13. (a) Self-cascode structure
(b) Equivalent composite transistor.
be gm2 / m, which is equivalent to the
transconductance of M1 (gm1). Now
the drain current (ID) through M1 and
M2 will be βeffective (Vin – VT)2 / 2, where Figure 14. A CM structure based on
βeffective equals β1β2 / (β1 + β2), which self-cascode MOSFETs.

can be approximated by β1 when m is

large [9].
The voltage between source and Iin Iout
drain of M1 is small, and there is no
appreciable difference between the
VDSAT of composite and simple transis-
tors; and a self-cascode can be used in M3
low voltage operation. For a self-
cascode VDSAT = VDSATM2 + VDSATM1.
The operating voltage of a regular
cascode is much higher than that of a
self-cascode. The advantage offered by
self-cascode structure is that it offers M1
high output impedance similar to that M2
of a cascode structure while output
voltage requirements are similar to
those of a single transistor.
A current mirror developed using
self-cascode structure is shown in
Fig. 14. The output current transfer V SS

35
 0.6

I in = 0.5 mA
0.5
I in = 0.4 mA
Output current in mA

0.4

I in = 0.3 mA
0.3
I in = 0.2 mA
0.2

I in = 0.1 mA
0.1

0.0
-1.0 -0.5 0.0 0.5 1.0
Applied voltage in volts
Figure 15. Output current characteristics.

characteristics of the CM are shown in In this article, we emphasize the

Fig. 15. The output impedance of the use of FGMOSFET devices for low
CM is large. Input current versus in- voltage design. Low voltage analog
put voltage characteristics are shown design is possible through the use of
in Fig. 16. It may be noted that this tech- FGMOSFET devices because thresh-
nique does not provide any benefit in old voltage tuning is possible, which
input compliance voltage at input front. reduces the headroom to a minimum.
Now one can use these devices in ana-
Floating Gate MOSFETs log circuits for designing the circuit
Floating gate (FG) MOSFETs are structures, which can operate at ultra-
being utilized in a number of new and low voltage supplies. Several such
exciting analog applications. These structures have been presented in the
devices are available in standard literature [12, 15–21]. Now we will
CMOS technology because they are discuss this aspect of floating gate
being widely used in digital circuits. MOSFETs in detail.
Thus floating gate devices are now The gate of an FG MOSFET is
finding wider applications by analog normally floating, with an electrical
researchers. As a result the floating charge residing. This charge dis-
gate devices are not only used for charges very slowly because of very
memories but are also being used as good insulation properties of SiO2.
circuit elements. FG MOSFETs are When the floating gate transistor is
used as analog memory elements, as bathed in UV light for some time, the
part of capacitive biased circuits, and charge on the floating gate disappears.
as adaptive circuit elements. For low voltage analog circuits, an

36
 0.0

-0.2
Input voltage in volts

-0.4

-0.6

-0.8

-1.0
0.00 0.02 0.04 0.06 0.08 0.10

Input current in mA
Figure 16. Input voltage characteristics.

FG is assumed to have no charge ac- able to get a MOSFET where V T

cumulation. A multi-input floating gate (equivalent) is lower than the normal
(MIFG) MOSFET, like the one shown VT. If gm(FG) is the trans-conductance
in Fig. 17, is used for analog circuit seen from the floating gate, the gm of
design. For a 2-input MIFG MOSFET, the combined structure equals gm(effective)
a higher dc voltage (Vb) is applied at = k2gm(FG) [9, 13, 14].
one gate (bias gate) and the signal is
applied at a second gate (signal gate). D
The VT for the MOSFET adjusts itself
to a new value VT (equivalent) which
is (VT – Vbk1) / k2 [16] where k1 equals FG ID
CG1 / CTOTAL and k2 equals CG2 / CTOTAL.
CG1 and CG2 are the capacitances be- V G1
tween floating gates and control gates. V G2
CTOTAL is the sum of the capacitances
between control gates and floating
gates, capacitance between floating
gate and drain, capacitance between V Gn
floating gate and source, and capaci- V GS
tance between floating gate and bulk
[9, 13, 14].
We find that the VT (equivalent) Figure 17. Multi-input
will be less than VT if we select Vb, k1 floating gate MOSFET.
and k2 properly. Thus we have been S
37
 Here, gm(effective) is less than gm(FG) by nique is now undergoing experimen-
a factor of k2. Because there is DC and tal study in low voltage analog circuit
AC feedback from drain to floating design. Researchers have used floating
gate through Cgd, the output impedance gate MOSFETs for the design of an
is less than that of a MOSFET work- ultra-low-voltage transconductor [18,
ing in the same biasing condition. 19], CMOS op amp [20], auto zeroing
When Cgd and go are the gate-to-drain amplifiers, and so forth [21].
capacitance and output conductance of The circuit diagram of a current
a MOSFET, the effective output con- mirror based on FGMOS technology
ductance go(effective) of the floating gate is shown in Fig. 19. The voltage Vb is
MOSFET equals (go + (Cgd gm/CTOTAL)). used to adjust the threshold voltage of
Thus the floating gate technology the input MOSFET. The functioning of
can be used in low voltage analog de- the circuit is similar to that of any CM.
sign. A differential pair using the float-
ing gate technique is shown in Fig. 18. Level Shifter Approach
The output impedance of a floating In this technique, MOSFETs are
gate transistor is lower, and only low either operating in saturation or in the
gain structures can be realized. Further, sub-threshold region [6, 22–25]. To
this technique requires fabrication of understand the technique, we take the
the floating gates. Hence the conven- example of a simple current mirror,
tional technology cannot be used, and shown in Fig. 2, in which the input cur-
this results in increased cost. The tech- rent (I D1 ) flowing through M1 is

Current mirror
I out I in

Vb

M1 M2
V i+ V i–

Figure 18. Differential pair based on I bias

FGMOSFETs.

38
K’W(VGS1 – VT)2 / 2L for W, L, K’, VGS1
and VT having their usual meanings. Figure 19. CM structure
based on FGMOSFETs.
Thus the minimum voltage required at
the input has to be more than VT for the I in I out
operation of this circuit. So it is not
possible to use these mirrors for input
voltage levels less than VT.
If this circuit is modified as shown
in Fig. 20, the input voltage require- Vb
ments of one VT can be removed. The
required input voltage (V in) equals M1 M2
VGS1 – VGS3. We find that the input and
output resistances are the same as two
MOSFET structures; but the input
voltage requirements are smaller.
A drawback in this circuit is the
offset current (Ioffset) flowing into the
output transistor for zero input current.
One finds that VGS2 depends on VDS1 and through this bias voltage (VDS2 is quite
Ibias. For low input current (Iin ≤ 1µA), high due to applied bias voltage) [18].
VDS2 is nearly equal to zero volts and Thus the offset current will be given by
Ibias alone decides VGS2. Ibias drives VGS2
W2 L3 I DO2  ∆VT 
to be near VT1 even for zero Iin . Vin will Ioffset ≈ Ibias exp  (4)
also be zero. But VDS2 increases inde- L2 W3 I DO3  η Vther 
pendently with VB . Under this condi- where ∆VT is the mismatch between
tion, a current flows through M2 (even the threshold voltages of NMOS and
though Iin is zero), because Ibias decides
the gate bias for M2 and VDS2 increases
independently with VB . This condition V in V DD VB
drives M2 into the sub-threshold re-
gion and a small current, known as the
offset current (Ioffset), flows through
M2. This effect is more troubling when
the input current is of the order of the I in V GS3 I bias I out
offset current. Ioffset decides the range
of operation for such circuits.
Interestingly, Ibias decides the op-
erational regime. If Ibias is low enough,
M3
M3 operates in the sub-threshold re-
gion. However when Ibias is high, M3 M1 M2
operates in saturation mode. We can
calculate Ioffset accordingly. V DS1
Ioffset is defined as the current flow-
ing through the transistor M2 when the V GS1
input current is zero. This condition
establishes that M1 and M2 operate
V SS
also in sub-threshold region. So, the
Figure 20. Modified CM based on level shifter technique.
output current through M2 is decided

39
 . . . we have presented techniques which
promise low voltage design. The comparative higher bandwidth at low voltage. The
analysis of these techniques is given in input resistance is also low, which is
Table 1. Depending upon the nature of the ap- desirable for current mode circuits.
These circuits have the capability for
plication, one can choose an appropriate tech- rail-to-rail operation, both at input and
nique or a combination of these techniques output ends.
for the intended analog circuit design. Use of Low Voltage Analog Cells
Inasmuch as all analog circuits can
be built using MOSFETs, and the
PMOS and Vther equals 26mV at room properties of the MOSFETs determine
temperature. When the threshold volt- the circuit properties, similarly all ana-
ages of the PMOS and NMOS are per- log circuits can be decomposed into
fectly matched and I DO2 = I DO3, the several sub-circuits, which may be re-
minimum Ioffset equals W2L3Ibias / L2W3. garded as analog cells. The properties
This can further be tailored according of these analog cells decide the char-
to the designer’s specifications by acteristics of the resultant circuit struc-
choosing appropriate values for tran- ture. If these analog cells can be de-
sistor aspect ratios. signed to operate at low voltages, then
When Ibias is sufficiently high, it the circuits in which they are used can
drives M3 into the saturation region; be expected to operate at low voltages
but M1 will be in linear mode due to as well. This technique is now gaining
low input current. However, M2 will more attention and has been used by
operate in the saturation region be- the authors in the design of various low
cause the external bias voltages will voltage analog circuits [9, 28, 29]. As
decide its drain voltage. In this situa- an example of the technique we have
tion the offset current is given by used a low voltage CM [9, 13] in the
2
β  2Ibias  design of low voltage analog circuit
Ioffset = 2 + VTP3 − VTN 2  . (5) structures.
2  β3 
The circuit given in [30] has been
For the condition where threshold volt- modified to include low voltage CMs
ages of PMOS and NMOS are [22]. The resultant structure is now
matched, the minimum offset current capable of operating at much lower
is K’2W2L3Ibias / K’3L2W3. voltages. This structure is then suitably
Thus, Ioffset is sufficiently high in modified to act as different types of
the case when M3 is operated in the CCs. These resultant structures are
saturation region. This follows because found to be high performing and
Ibias is higher and K2’ / K3’ equals 3. modular in nature [29].
Here K2’ and K3’ are the trans-conduc-
tance parameters (= µCOX) for M2 and Conclusions
M3 respectively. In this paper, we have presented
In this configuration, the number techniques which promise low voltage
of MOSFETs increases, which is likely design. The comparative analysis of
to increase the power dissipation. The these techniques is given in Table 1.
most desirable characteristics include Depending upon the nature of the ap-

40
plication, one can choose an appropri- MOSFET Trans-Conductance”, Electronic
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[5] M. Ismail and S. Bibyk, “CAD Latches
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Table 1. Characteristics of Various Techniques for CMOS Design

Technique Available Supply Voltage Power Technology
BW Requirements Consumption Requirements
Sub-threshold MOSFETs Low ≈ 2VT Low Standard
Bulk-driven MOSFETs Low ≈ 2VT High Special
Self-Cascode MOSFETs Medium > 2VT High Standard
Floating gate MOSFETs Medium < 2VT Medium Special
Level shifter MOSFETs High < 2VT Medium Standard
Use of low voltage cells High < 2VT Medium Standard

41
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