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04-Chap5-Internal Memory RAM

This document discusses different types of computer memory, including dynamic RAM (DRAM), static RAM (SRAM), and read-only memory (ROM). It describes the basic structure and operation of memory cells and chips. DRAM uses capacitors to store data and must be periodically refreshed, while SRAM uses flip-flops and does not require refreshing. The document outlines how memory is organized into modules using multiple memory chips and addresses.

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abdul shakoor
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104 views10 pages

04-Chap5-Internal Memory RAM

This document discusses different types of computer memory, including dynamic RAM (DRAM), static RAM (SRAM), and read-only memory (ROM). It describes the basic structure and operation of memory cells and chips. DRAM uses capacitors to store data and must be periodically refreshed, while SRAM uses flip-flops and does not require refreshing. The document outlines how memory is organized into modules using multiple memory chips and addresses.

Uploaded by

abdul shakoor
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CS-213 COMPUTER ORGANIZATION

AND ASSEMBLY LANGUAGE

Chapter 5
Internal Memory

Overview
• Dynamic RAM (DRAM) & Static RAM (SRAM)
— Properties
— Structure
— Difference
— Chip Logic
— Chip Packaging
— Module Organization
• Error Detection & Correction
— Hamming Code
— Single Error Correcting & Detecting (SEC-SED)
• Advanced DRAM Organization
— Synchronous DRAM (SDRAM)
— Double Data Rate DRAM (DDRRAM)
— Rambus RAM (RDRAM)
— Cache DRAM (CDRAM)

1
Semiconductor Memory
• Earlier computers had an array of doughnut-
shaped ferromagnetic loops called core used as
RAM - vanquished by microelectronics
• Two basic forms of semiconductor random access
memory are DRAM & SRAM
• Another form of semiconductor random access
memory is ROM
— ROM
— PROM
— EPROM
— EEPROM
— Flash Memory

Semiconductor Memory Types

• Word RAM misused as all semiconductor memory is random access

2
RAM
• RAM
—Read/Write
—Volatile
—Temporary storage
—Static or dynamic
• Basic element of semiconductor memory
is a memory cell
—Exhibits two stable states 0, 1
—Capable of being written (set the state)
—Capable of being read (sense the state)

Memory Cell Operation

• Three functional terminals capable of carrying the signal

• The details of the internal organization depend on the IC technology used and is out
of the scope of this course, except for a brief summary

3
Dynamic RAM
• DRAM is made with cells that store data as charge
in capacitors

• Capacitors have natural tendency to discharge


• Need refreshing even when powered
• Simpler construction
• Smaller per bit why?
• Less expensive why?
• Need refresh circuits
• Slower why?
• Main memory
• Essentially analogue - Level of charge determines
value

Dynamic RAM
Structure & Operation

• Address line active when bit read or


written
— Transistor switch closed (current
flows)
• Write
— Voltage to bit line
– High for 1 low for 0
— Then signal address line
– Transfers charge to capacitor
• Read
— Address line selected
– transistor turns on
— Charge from capacitor fed via bit
line to sense amplifier
– Compares with reference value to
determine 0 or 1
— Capacitor charge must be restored

4
Static RAM
• Bits stored as on/off switches
• No charges to leak
• No refreshing needed when powered
• More complex construction
• Larger per bit
• More expensive
• Does not need refresh circuits
• Faster
• Cache
• Digital
—Uses flip-flops

Static RAM Structure


& Operation

• Transistor arrangement
gives stable logic state
• State 1
— C1 high, C2 low
— T1 T4 off, T2 T3 on
• State 0
— C2 high, C1 low
— T1 T4 on, T2 T3 off
• Address line transistors T5 T6
is switch
• Write – apply value to B &
compliment to B
• Read – value is on line B

5
SRAM v DRAM
• Both volatile
—Power needed to preserve data
• Dynamic cell
—Simpler to build, smaller
—More dense How?
—Less expensive
—Needs refresh
—Larger memory units
• Static
—Faster
—Cache

Read Only Memory (ROM)


• Permanent storage
—Nonvolatile
• Applications
—Microprogramming (see later)
—Library subroutines
—Systems programs (BIOS)
—Function tables
• Data is actually wired into the chip as part
of the fabrication process

6
Types of ROM (1/2)

• Written during manufacture


—Very expensive for small runs
• Programmable (once)
—PROM
– Needs special equipment to program
– Electrically written
– Can be performed after fabrication but only once
• Read ―mostly‖
—Erasable Programmable (EPROM)
– Erased by Ultraviolet radiations
– Before write, all the storage cells must be erased to
the same initial state by exposing the chip to UV
– Erasure process can take as long as 20 minutes

Types of ROM (2/2)

• Read ―mostly‖
—Electrically Erasable (EEPROM)
– Takes much longer to write than read
– Write operation does not need prior erasing of cells
– Only the addressed bytes can be updated
—Flash memory
– Introduced in mid 1980s
– Erase whole memory electrically in few seconds
– Can allow to erase individual blocks but no byte level
erasure
– Can erase a section of memory in one action or flash
– One transistor per bit, so high density

7
Organisation in detail (1/2)

• As with other IC products, semiconductor


memory comes in packaged chips
• Each chip contains an array of memory cells
• Key design issue for semiconductor memory is
the number of bits that can be read/written at a
time… i.e. how these arrays of cells are arranged
• For example a 16Mbit chip can be organised:
— as 1M of 16 bit words i.e 1M x 16
— as 4M of 4 bit words i.e 4M x 4
— as 16M of 1 bit words i.e 16M x 1 (1 bit per chip
organization)
• A bit per chip system has 16 lots of 1Mbit chip
with bit 1 of each word in chip 1 and so on

Organisation in detail (2/2)

• A 16Mbit chip can be organised as a 2048 x 2048


x 4bit array
— Reduces number of address pins
– Multiplex row address and column address
– 11 pins to address (211=2048)
– Adding one more pin doubles range of values so x4
capacity
• Refreshing
— Refresh circuit included on chip
— Disable chip
— Count through rows
— Read & Write back
— Takes time
— Slows down apparent performance

8
Typical 16 Mb DRAM (4M x 4) – Chip Logic
• Horizontal line connects to sel terminal
• Vertical line connects to sense terminal
• Row decoder selects the row
• Column decoder selects the cell in row
• The 22 required address lines are
passed through select logic external to
chip and multiplexed onto 11 pins

Packaging
• 1M x 8 EPROM • 4M x 4 DRAM
• One word per chip package •11 pins used for address
• 20 Address lines needed to address 1 M words • 4 data pins
• 8 Data pins • NC is no connect to make the pins even

9
256kByte Module
Organisation

• If a RAM chip contains 1 bit per word, then


we need number of chips equal to number of bits
per word
• Example: Memory module consisting of 256 K
8-bits words is organized into 512 x 8
• For 256 words, 18 bits address is supplied to
the module from external source
• The address is presented to all the chips , each
of which inputs/outputs one bit

1MByte Module Organisation


• The organization works as long as the memory
is small
• if larger memory is required then we organize
the chips in arrays
•256 K is organized into 512 x 8

10

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