RAM-stands for Random Access Memory

There are two types of RAM

DRAM -Dynamic Random Access Memory

-more common than SRAM
-needs to be refreshed thousands of times per second.
-supports access time of 60 nanoseconds

DRAM is a type of random access memory that stores each bit of data in a separate
capacitor within an integrated circuit. Since real capacitors leak charge, the information
eventually fades unless the capacitor charge is refreshed periodically. Because of this
refresh requirement, it is a dynamic memory as opposed to SRAM and other static
memory.

SRAM -Static Random Access Memory

-does not need to be refreshed
-supports access time of 10 nanoseconds
-much more expensive than the DRAM

SRAM is a type of semiconductor memory where the word static indicates that, unlike
dynamic RAM (DRAM), it does not need to be periodically refreshed, as SRAM uses
bistable latching circuitry to store each bit. SRAM exhibits data remanence, but is still
volatile in the conventional sense that data is eventually lost when the memory is not
powered.

Some Types of DRAM

FPM DRAM

Fast page mode DRAM is also called FPM DRAM, Page mode DRAM, Fast page mode
memory, or Page mode memory.

In page mode, a row of the DRAM can be kept "open" by holding /RAS low while
performing multiple reads or writes with separate pulses of /CAS so that successive reads
or writes within the row do not suffer the delay of precharge and accessing the row. This
increases the performance of the system when reading or writing bursts of data.

EDO DRAM

EDO DRAM, sometimes referred to as Hyper Page Mode enabled DRAM, is similar to
Fast Page Mode DRAM with the additional feature that a new access cycle can be started
while keeping the data output of the previous cycle active. This allows a certain amount
of overlap in operation (pipelining), allowing somewhat improved performance. It was
5% faster than Fast Page Mode DRAM, which it began to replace in 1995, when Intel
introduced the 430FX chipset that supported EDO DRAM.
BEDO DRAM

An evolution of the former, Burst EDO DRAM, could process four memory addresses
in one burst, for a maximum of 5-1-1-1, saving an additional three clocks over optimally
designed EDO memory. It was done by adding an address counter on the chip to keep
track of the next address. BEDO also added a pipelined stage allowing page-access cycle
to be divided into two components. During a memory-read operation, the first component
accessed the data from the memory array to the output stage (second latch). The second
component drove the data bus from this latch at the appropriate logic level. Since the data
is already in the output buffer, quicker access time is achieved (up to 50% for large
blocks of data) than with traditional EDO.

Synchronous DRAM

SDRAM is dynamic random access memory (DRAM) that has a synchronous interface.
Traditionally, dynamic random access memory (DRAM) has an asynchronous interface,
which means that it responds as quickly as possible to changes in control inputs. SDRAM
has a synchronous interface, meaning that it waits for a clock signal before responding to
control inputs and is therefore synchronized with the computer's system bus. The clock is
used to drive an internal finite state machine that pipelines incoming instructions. This
allows the chip to have a more complex pattern of operation than an asynchronous
DRAM, which does not have a synchronized interface.
Direct Rambus DRAM or Rambus DRAM

DRDRAM or RDRAM is a type of synchronous dynamic RAM, designed by the

Rambus Corporation.

Rambus's RDRAM saw use in three video game consoles, beginning in 1996 with the
Nintendo 64. The Nintendo console utilized 4 MB RDRAM running with a 500 MHz
clock on a 9-bit bus, providing 500 MB/s bandwidth. RDRAM allowed N64 to be
equipped with a large amount of memory bandwidth while maintaining a lower cost due
to design simplicity. RDRAM's narrow bus allows circuit board designers to use simpler
design techniques to minimize cost. The memory, however, was disliked for its high
random access latencies. In the N64, the RDRAM modules are cooled by a passive heat
spreader assembly.

Sony uses RDRAM in the PlayStation 2. The PS2 was equipped with 32 MB of the
memory, and implemented a dual-channel configuration resulting in 3200 MB/s available
bandwidth. The PlayStation 3 utilizes 256 MB of Rambus' s XDR DRAM, which could
be considered a successor to RDRAM, on a 64-bit bus at 400 MHz with an octal data rate
(cf. double data rate) providing a clock rate of 3.2 GHz, allowing a large 204.8 Gbit/s
(25.6 GB/s) bandwidth.

Dual Data Rate Synchronous DRAM

Compared to the preceding single data rate (SDR) SDRAM, the DDR SDRAM interface
makes higher transfer rates possible by more strict control of the timing of the electrical
data and clock signals. Implementations often have to use schemes such as phase-locked
loops and elf-calibration to reach the required timing accuracy. The interface uses double
pumping (transferring data on both the rising and falling edges of the clock signal) to
lower the clock frequency. One advantage of keeping the clock frequency down is that it
reduces the signal integrity requirements on the circuit board connecting the memory to
the controller. The name "double data rate" refers to the fact that a DDR SDRAM with a
certain clock frequency achieves nearly twice the bandwidth of a single data rate (SDR)
SDRAM running at the same clock frequency, due to this double pumping.
Dual Data Rate 2 Synchronous DRAM

DDR2 SDRAM is a double data rate synchronous dynamic random access memory
interface. It supersedes the original DDR SDRAM specification and the two are not
compatible. In addition to double pumping the data bus as in DDR SDRAM (transferring
data on the rising and falling edges of the bus clock signal), DDR2 allows higher bus
speed and requires lower power by running the internal clock at one quarter the speed of
the data bus. The two factors combine to require a total of 4 data transfers per internal
clock cycle.

Dual Data Rate 3 Synchronous DRAM

DDR3 memory provides a reduction in power consumption of 30% compared to DDR2

modules due to DDR3's 1.5 V supply voltage, compared to DDR2's 1.8 V or DDR's 2.5
V. The 1.5 V supply voltage works well with the 90 nanometer fabrication technology
used in the original DDR3 chips. Some manufacturers further propose using "dual-gate"
transistors to reduce leakage of current.

----Upcoming----

Dual Data Rate 4 Synchronous DRAM

DDR4 SDRAM will be the successor to DDR3 SDRAM. It was revealed at the Intel
Developer Forum in San Francisco, 2008, that it is currently in the design phase and has an
expected released date of 2012.

The new chips are expected to run at 1.2 V or less, versus the 1.5 V of DDR3 chips and
have in excess of 2 billion data transfers per second. They are expected to be introduced
at clock speeds of 1600 MHz, estimated to rise to a potential 3200 MHz (3.2 GHz) and
lowered voltage of 1.0 V by 2013.