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Real-Time Systems

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RTS notes-2013

Semester: VII Subject: REAL-TIME SYSTEMS

Branch: ECE/TCE Subject Code: 10EC762

Course Facilitator: Mr. Anand Raj S N

Assistant Professor,
Department of Telecommunication Engineering
JNNCE,
Shivamogga-577204,
Karnataka
Mobile:9845579713
Suggestions and Feedback: [email protected]

This note of Real-time systems covers five major units of the syllabi and the
students can answer for 100 marks in the theory examination. Each time I taught the
subject, I actually felt that providing very good notes can minimize the burden of
students who are in the verge of improving their percentile and also i have used my
own way of giving real-life examples for the clear understanding of the concepts of
the subject.

The students following this note are expected to be familiar with basics of
computer architecture, programming, computer communications, computer hardware
and operating systems.

Finally, I wish all the very best to the student community who are the future
engineers of modern India.

Anand Raj S N, Asst Professor, JNNCE, Shivamogga

RTS notes-2013

Syllabus covered:

PART - A

UNIT - 1

INTRODUCTION TO REAL-TIME SYSTEMS: Historical background, RTS Definition,

Classification of Real-time Systems, Time constraints, Classification of Programs.

UNIT - 2

CONCEPTS OF COMPUTER CONTROL: Introduction, Sequence Control, Loop

control, Supervisory control, Centralised computer control, Distributed system,
Human-computer interface, Benefits of computer control systems.

UNIT - 3

COMPUTER HARDWARE REQUIREMENTS FOR RTS: Introduction General purpose

computer, Single chip microcontroller, Specialized processors, Process-related
Interfaces, Data transfer techniques, Communications, Standard Interface.

PART - B

UNIT - 5 & 6

OPERATING SYSTEMS: Introduction, Real-time multi-tasking OS, Scheduling

strategies, Priority Structures, Task management, Scheduler and real-time clock
interrupt handles, Memory Management, Code sharing, Resource control, Task co-
operation and communication, Mutual exclusion, Data transfer, Liveness, Minimum OS
kernel, Examples

Anand Raj S N, Asst Professor, JNNCE, Shivamogga

RTS notes-2013

Unit-1

Introduction to Real-Time systems

Historical Background:

 The earliest proposal to use a computer operating in Real-time as part of control

system was made by Brown and Campbell (1950): (in paper only) limited only to
the analog computing elements.
 The 1st digital computers developed specifically for R.T.S. were for airborne
operating. In 1954 a digital computer was successfully used to provide an
automatic flight and weapons control system.
 The 1st industrial installation of a computer system was in September, 1958 for
plant monitoring at power station in sterling, Louisiana.
 The 1st industrial computer control installation was mad by the Texaco Company
who installed an RW-300 system at their port Arthur refinery in Texas on
15/03/1959
 The 1st DDC computer system was the Ferranti Argus 200 system installed in
 November, 1962 at the ICI, Lancashire, UK. It has 120 control loops and 256
Measurements. The technological developments in IC and construction techniques
for circuit boards led to an increase in reliability of computer systems.
 The advent of the Microprocessor in 1974 made economically possible the use of
DDC and distributed computer control systems.

Elements Of A Computer Control System:

Consider the hot- air blower as an example to illustrate the various operations of a
computer control system. The following section explains about the operations of hot-air
blower.

 A centrifugal fan blows air over a heating element and into a tube
 A thermostat is used to detect the temperature
 The position of the air-inlet cover to the fan is adjusted by a reversible DC motor
(constant speed)
 A potentiometer is attached to the air-inlet cover
 Two 8-switches are used to detect when the cover is fully open or fully closed
 The operator is provided with a panel from which the control system can be
switched from automatic to manual control panel. Lights indicate: Fan ON, Heater
ON, Cover fully-open, Cover fully-closed, Auto/Manual status.

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RTS notes-2013

Fig: 1.1 A simple plant – a hot –air blower

 The information is available from the plant instrument in the following two forms:
– Analog signals: Air Temp., Fan-inlet cover position.
– Digital signals: Fan-inlet cover position (Fully-open, Fully-closed)
– Status signals: Auto/Manual, Fan motor ON, Heater ON
 The operation of this simple plant using a computer requires a computer software
be provided to support monitoring, control and actuation of the plant.
 Monitoring involves obtaining information about the current state of the plant
 Control involves the digital equivalent of continuous feedback control for the DDC.

Anand Raj S N, Asst Professor, JNNCE, Shivamogga

RTS notes-2013

Fig 1.2 computer control of a hot-air blower

Fig 1.3 Generalised computer control of a hot-air blower

Anand Raj S N, Asst Professor, JNNCE, Shivamogga

RTS notes-2013

Real-Time System Definition:

“A real-time system is the one whose output is not only dependent on the input
of the system but also depends on the timeliness of the system”

OR

“Any system. in which the time at which the output is produced is significant.
This is usually because the input corresponds to some movement in the physical
world, and the output has to relate to that some movement. The lag from input time
to output time must be sufficiently small for acceptable timeliness”

OR

“Real-Time systems are those which must produce correct responses within a
definite time limit. Should computer responses exceed these time bounds then
performance degradation and/or malfunction results”

Real-Time Program:

“A program for which the correctness of operation depends both on the logical
results of the computation and at which the results are produced”

Fact: All real-time systems are embedded systems but all embedded systems are not
real-time systems.

Fig 1.4 Few applications of RTS

Anand Raj S N, Asst Professor, JNNCE, Shivamogga

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Classification Of Real-Time Systems:

RTS are classified based on the tasks into the following three categories:

 Clock- based tasks (cyclic, periodic)

 Event –based tasks(aperiodic)
 Interactive systems

Synchronization between the external processes and internal actions (tasks) carried out
by the computer may be defined in terms of the passage of time, or the actual time of
day, in which case the system is said to be “Clock-based system” or it may be defined in
terms of events, and the system is said to be “Event-based system”.
If the relationship between the actions in the computer and the system is much more
loosely defined, then the system is said to be “interactive system”.

 Clock-Based Tasks: (Cyclic and Periodic):

– The completion of the operations within the specified time is dependent on the
number of operations to be performed and the speed of the computer.
– Synchronization is usually obtained by adding a clock to the computer system,
and using a signal from this clock to interrupt the operation of the computer at
predetermined fixed time interval.
 Event-Based Tasks: (A periodic):
– Action are to be performed not at particular times or time intervals but in
response to some event . The system must respond within a given max. Time to a
particular event.
– Events occur at non-deterministic intervals and event-based tasks are referred to
as “a -periodic” task.
 Interactive Systems:
- They represent the largest class of RTSs such as automatic bank tellers,
reservation systems for hotels, airlines and car rental……etc.
The real-time requirement is usually expressed in terms such as “the average
response time must not exceed some predetermined time”
Example: an automatic bank teller system might require an average response time
not exceeding 20 sec
- An interactive system responds at a time determined by internal state of the
computer without reference to the external environment.

Classification Based On Timing Constraints:

Based on timing constraints real-time tasks are classified into two types

Anand Raj S N, Asst Professor, JNNCE, Shivamogga

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 Hard real-time(these are systems that must satisfy the deadlines on each and
every occasion)
 Soft real-time (these are systems for which an occasional failure to meet a
deadline does not comprise the correctness of the system)

Mathematical Modelling Of Time Constraints:

Table1: modelling time constraints

Classification Of Programs:

Programs can be broadly classified into the following 3 categories:

 Sequential
 Multi-tasking
 Real-time

Sequential:
- Actions are ordered as a time sequence, the program behaviour depends only on the
effects of the individual actions and their order but not on the time taken to perform
those actions
Multi-tasking:

Anand Raj S N, Asst Professor, JNNCE, Shivamogga

RTS notes-2013

-Actions are not necessarily disjoint in time, it may be necessary for several actions to be
performed in parallel. Hence in multitasking programs various tasks are executed con-
currently and communicate through shared variables and synchronization signals
Real-Time:
- Actions are not necessarily disjoint in time, and the sequence of some of program
actions is not determined by the designer but the environment (by events occurring in the
outside world which occur in real-time and without reference to the internal operations
of the computer).

Summary:

The key ideas described in this chapter are:

 A brief history of computer control.
 Digital computers are sequential devices.
 Real-time systems have to carry out both Periodic and a-periodic activities.
 Real-time systems have to satisfy time constraints that can be either a hard or a
soft constraint.
 Real-time software is more difficult to specify, design and construct than non-
real-time software.

Anand Raj S N, Asst Professor, JNNCE, Shivamogga

RTS notes-2013

UNIT - 2
CONCEPTS OF COMPUTER CONTROL:

The chapter covers the various concepts of computer that is used to control and
co-ordinate the various activities of a plant (external environment or controlled
environment)
Computer controlled applications are mainly classified into:
 Batch
 Continuous
 Laboratory (or test)

Batch applications: (example: rolling of sheet steel)

 In this process, sequences of operations are carried out to produce a
product – the BATCH and then the sequence is repeated to produce further
batch products.
 The specification of the product can be varied between the run.
 A typical example of batch production is rolling of sheet steel- here an
ingot(mass of molten metal) is passed through the rolling mill to produce a
particular gauge of steel, next ingot may be either of a different
composition or rolled to a different thickness and hence will require
different settings of the rolling mill.
 Two important measure in batch production are:
1. Set-up time: (change over time)
 Time taken to prepare the equipment for the next production
batch, this is the wasted time in that no output is being produced.
2. Operation time:
 Time taken to produce the product
 The ratio between the operation time and set-up time determines the
suitable batch size.

Continuous applications: (example: catalytic cracking of oil)

 The term continuous is used for systems in which production is maintained
for long periods of time without interruption
 The example for continuous system is the catalytic cracking of oil in which
the crude oil is separated to get different products.
 Here specifications can be changed without halting the process.
 A problem which occurs in continuous processes is that during change-over
from one specification to another, the output of the plant is not within the
product tolerance and the process must be started from the beginning.
Hence change over should be made as accurately, quickly and smoothly as
possible.

Anand Raj S N, Asst Professor, JNNCE, Shivamogga

RTS notes-2013

 As a usual practise, continuous and batch processes are mixed together,

example of mixed mode systems is in baking industry wherein the bread
dough(flour moistened and Kneaded) is produced in batches but continuous
ovens are frequently used to bake it, whereby the loaves are placed on
conveyor which moves slowly through the oven.

Laboratory systems: (example: testing of an audiometer)

 Operator–initiated type in that the computer is used to control some
complex experimental test or some complex equipment used for routine testing.
 Typical example is testing of an audiometer-a device used to test hearing.
The audiometer has to produce sound levels at different frequencies; this is a
complex process because actual level produced is a function of frequency since
sensitivity of the human ear varies with frequency. Each audiometer has to be
tested against a sound level meter and a test certificate is produced. This is done
by using a sound level meter connected to a computer and using the output from
the computer to drive the audiometer through its frequency range. The results
printed out from the test computer provide the test certificate.

The activities being carried out by a computer, in a RTS, will include the following:
 Data acquisition.
 Sequence control.
 Direct digital control (DDC).
 Supervisory control (SC).
 Data analysis.
 Data storage.
 Human – computer interface (HCI).

The objectives of using a computer in a RTS will include the following:

 Efficiency of operation
 Ease of operation.
 Safety.
 Improved products
 Reduction in waste.
 Reduced environmental impact.
 Reduction in direct labour.

Sequence control:

 Sequence control occurs predominately in batch process.

 Sequence control systems are widely used in the food processing and chemical
industries.
 The procedure for simple reactor vessel as shown in fig 2.1 are:
Anand Raj S N, Asst Professor, JNNCE, Shivamogga
RTS notes-2013

1. Open valve A.
2. Check the level of chemical 1.
3. Start the stirrer to mix the chemical reactor.
4. Repeat steps 1 and 2 with valve B.
5. Switch ON the PID controller.
6. Monitor the reaction temp, when it reaches the set-point, start a timer.
7. When the timer indicates that the reaction is complete, switch OFF the
controller and open valve C to cool down the reactor contents. Switch OFF the
stirrer.
8. Monitor the temp, when the contents have cooled, open valve E to remove the
product from the reactor.

Typical reactor vessel for this purpose is illustrated in the below figure 2.1

Fig 2.1 A simple chemical reactor vessel

All the above actions and timings are based on software, for a large
chemical plant, such sequences can become lengthy and complicated to ensure
efficient operating; several sequences take place in parallel.

Fig 2.2 shows how sequences can be carried out in parallel.

 In this process, two reactor vessels (R1 and R2) are used alternatively, so
that the processes of preparing for next batch production and cleaning up
after the production can be carried out in parallel.

Anand Raj S N, Asst Professor, JNNCE, Shivamogga

RTS notes-2013

 Assuming R1 has filled with the mixture and the catalyst and the reaction is
in progress.

Fig 2.2 Typical chemical batch process

 At the same time vessel R2 will be cleaned-the wash down sequence – and the next
batch of raw material will be measured and mixed in the mixing tank.
 In parallel the previous batch will be thinned down and transferred to the
appropriate storage tank and if any change in the composition is required, the thin
down tank will be cleaned.
 Once this is done the next batch can be loaded into R2 and then assuming that the
reaction in R1 is complete, the contents of R1 will be transferred to the thin down
tank and the wash down procedure for R1 is initiated.
 The various sequences of operations required can become complex and there may
also be complex decisions to be made as to when to begin a sequence.
 The sequence initiation may be left to a human operator or the computer may be
programmed to supervise the operations.

Anand Raj S N, Asst Professor, JNNCE, Shivamogga

RTS notes-2013

An example of continuous systems involving sequence, loop and

supervisory control:

Consider the float glass process shown in the below figure 2.3.

Fig 2.3 Schematic of float glass process.

 The raw materials sand, powdered glass and fluxes are mixed in batches and fed in
to the furnace.
 The mixture melts rapidly to form a molten mixture which flows through the
furnace.
 As the molten glass moves through the furnace it is refined.
 Here controlling temperature is very important to maintain quality and to keep fuel
costs minimum.
 The molten glass flows out of the furnace and forms a ribbon on the float bath;
again temperature control is important as the glass ribbon has to cool sufficiently so
that it can pass over rollers without damaging the surface.
 The continuous ribbon passes into the lehr where it is annealed and again
temperature control is an important factor.
 From the lehr the glass ribbon moves down the line towards the cutting station at a
speed which is too great for manual inspection so automatic inspection is used and
faults are being marked by spraying paint on to the ribbon.
 The glass ribbon is passed under a cutter which cuts it to the sheets of required size
and automatic stackers lift the sheets from production line.
 The whole process is controlled by several computers.

Loop Control(Direct Digital Control):

In direct digital control (DDC) the computer is in feedback loop as shown in the
below fig 2.4. A consequence of the computer being used in the feedback loop is that it
forms a critical component in terms of the reliability of the system and hence great care
is needed to ensure that in the event of failure or malfunctioning the plant must remain
in safe condition.

Anand Raj S N, Asst Professor, JNNCE, Shivamogga

RTS notes-2013

Fig 2.4 Direct Digital Control

 The usual means of ensuring safety is to limit DDC unit to make incremental
changes to the actuators on the plant and to limit the rate of changes of the
actuator.
 A- Actuator: An actuator is a type of motor for moving or controlling a mechanism
or system. It is operated by a source of energy, usually in the form of an electric
current, hydraulic fluid pressure or pneumatic pressure, and converts that energy
into some kind of motion. An actuator is the mechanism by which an agent acts
upon an environment. The agent can be either an artificial intelligence agent or
any other autonomous being (human, other animal, etc.).
 Advantages of DDC are as follows:

1. Cost- cheaper than analog control as a single digital computer can

control a large number of loops
2. Performance- digital control offers simpler implementation of a wide
range of control algorithms, improved controller accuracy and
reduced drift.
3. Safety- modern digital hardware is highly reliable with long mean
time between failures and hence can improve the safety of systems.

Anand Raj S N, Asst Professor, JNNCE, Shivamogga

RTS notes-2013

PID control :( proportional integral derivative)

 For wide range of industrial application overall performance can be improved by

using either PI or PID control.
 For majority of the systems, PI control is sufficient, using a control signal that is
made proportional to the error between the desired value of an output and actual
value of the output.
 The ratio between the control signal and the error signal can be adjusted using
proportionality constant(Kp)
 Choosing Kp value is difficult,
 A high value of Kp gives a small steady state error and a fast response but
response is oscillatory which is not acceptable in many applications.
 A low value of Kp gives a slow response and a large steady state error
 By adding the integral action term the steady state error can be reduced to zero
since integral term integrates the error signal with respect to time.
 A purely proportional controller operates correctly under only one condition; any
change in environment would result in a steady state error. These errors are
reduced by employing integral term.
 For few processes which are subjective to sudden disturbances, derivative term
would compensate for the changes.
 PID controller gives well behaved controller hence used extensively.

PID control algorithm has the general form,

Where, Kp = overall controller gain

e (t) = r (t) - c (t)

c (t) is the measured variable,

r (t) is the reference value or set point

e (t) is the error,

Ti is the integral action time,

Td is the derivative action time.

Anand Raj S N, Asst Professor, JNNCE, Shivamogga

RTS notes-2013

DDC applications:

 DDC loops may be applied to a single loop systems implemented on a small

microprocessor or to a large system involving hundred loops.
 A typical example is a steam boiler control system as shown in the Fig 2.5

Fig 2.5 Steam Boiler Control System

A typical example of DDC application is a steam boiler control system, which

involves the following operations to be controlled.
 A particular mixture of air & fuel is supplied to control the steam pressure
 The steam pressure control system generates an actuation signal which is fed to
an auto / manual bias station
 If the auto switch is ON then actuation signal is supplied to the next level
 If the manual mode is selected then signal which is entered manually is supplied
to the next level.
 The signal from bias station is connected to two units high signal and low signal
selector, each of which as two inputs and one output. The high signal selector
selects higher of the two input signal and transmits.
 Low selector transmits the lower of two inputs.
 Low selector provides set point for DDC loop controlling oil flow and high selector
provides set points for air flow controller.
 The ratio unit R is installed in the air flow measurement line.

Anand Raj S N, Asst Professor, JNNCE, Shivamogga

RTS notes-2013

 A signal from the controller which monitors the combustion flames directly is
added to the air flow signal to provide the input to the air flow controller.

DDC technique Are also used for inferential, feed-forward and adaptive or self tuning
controller.

Inferential controller:

It is applied to control system, where the variables on which feedback control is to

be based cannot be measured directly, but have to be inferred from measurements of
some other quantity.

Fig 2.6 General Structure Of Inferential Control Configuration

The above fig. 2.6 illustrate the general structure of inferential control
configuration, some measurements can be measure directly but some measurements
cannot be done directly, hence some other process measurement is made and from this
the value of the controlled variables is inferred.

Inferential control are usually used in distillation column control, schematic

diagram of binary distillation is shown in below fig 2.7

Anand Raj S N, Asst Professor, JNNCE, Shivamogga

RTS notes-2013

Fig 2.7 Binary Distillation column

 The four independent variables usually controlled are liquid levels Ha and Hb in
the accumulator and reboiler, compositions X a and Xb of the top and bottom
products
 The compositions can be measured directly by spectrographic techniques but it is
more usual to measure the temperature at point Y a and Yb near the top and
bottom of the column and pressure P in the column.
 The temperature represents the boiling points of the mixture at the position in
the column.
 From measurements of pressure and temperature the composition can be
inferred.
Feed forward control:

 It is frequently used in the process industries.

 It involves measuring the disturbances on the system rather than measuring the
outputs.

Anand Raj S N, Asst Professor, JNNCE, Shivamogga

RTS notes-2013

Fig 2.8 General Structure Of Feed Forward Control System

The general structure of feed forward system is as shown in the above fig 2.8

 Example: in the hot rolling of sheet steel, if the temperature of the billet is
known as it approaches the first stage mill, the initial setting of the roll gap can
be calculated accurately and estimates of the reduction at each stage of the mill
can be made, hence initial gap for the subsequent stages can also be calculated.
If this is done time taken to get the gauge of the steel within tolerance can be
reduced and hence quantity of scrap steel is reduced.
 The effect of introducing feed forward control is to speed up the response of the
system to disturbances.

Adaptive control:

Adaptive control can take several forms, three among the most common are as
follows

 Pre-programmed adaptive control

 Self tuning
 Model reference adaptive control

Pre-programmed adaptive control:

 The adaptive are adjustment mechanism makes preset changes on the basis of
changes in auxillary process measurements.

Anand Raj S N, Asst Professor, JNNCE, Shivamogga

RTS notes-2013

Fig2.9 pre-programmed adaptive control.

The above fig 2.9 illustrates programmed adaptive control for auxillary process
measurements.

Example:

 In a reaction vessel a measurement of the level of liquid in the vessel might be

used to change the gain of the controller.
 In many aircraft controls the measure air speed is used to select controller
parameters according to a preset schedule.

Fig2.10 pre-programmed adaptive control (external environment)

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Fig 2.10 illustrates programmed adaptive control for external environment in

which measurements of changes in the external environment are used to select the
gain or other controller parameters.

Example:
 In an aircraft auto- stabiliser control parameters may be changed according to
the external air pressure.

Self tuning adaptive control:

 It uses identification techniques to achieve continual determination of the

parameters of the process being controlled.
 Changes in the process parameters are then used to adjust the actual controller.
 An alternative form is to inject a small disturbance to the process and measures
the response, then response is compared to some desired response and controller
parameters are adjusted to bring the response closer to the desired response.

Fig 2.11self-tuning adaptive control

Model reference adaptive control:

Anand Raj S N, Asst Professor, JNNCE, Shivamogga

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Fig 2.12 mode-reference adaptive control

 It relies on the ability to construct an accurate model of the process and to

measure the disturbances which affect the process.

Supervisory control:

 Computers are not only used to directly control the operation the plant, but also
it can provide managers and engineers with a comprehensive picture of the status
of the plant operators. It is the supervisory role.
 The basic idea is as shown in the below fig.2.11

Fig 2.13 supervisory control

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 The circles labelled C represents individual controllers in the feedback loop,

these can be digital computers or some other form of controllers.
 An example of supervisory control is shown in the below fig.2.12

Fig 2.14 example of supervisory control

 Two evaporators are connected in parallel and material which is in liquid form
(solution) is fed to each unit.
 The purpose of the plant is to evaporator as much as water as possible in the
solution.
 Steam is supplied to a heat exchanger linked to the first evaporator and the
steam for the second evaporator is supplied from the vapours boiled of from the
first stage.
 To achieve maximum evaporation the pressures in the chambers must be as high
as safety permits
 Also it is necessary to achieve a balance between the two evaporators.
 A supervisory control scheme can be design to balance the operation of the two
evaporators to obtain the best overall evaporation rate.
 Supervisory are based upon the steady state characteristics of the plant. In some
plants control algorithms have also been used to increase plant profitability.
 currently, expert system (an expert system is an interactive computer based
decision tool that uses both facts and heuristics to solve difficult decision making

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RTS notes-2013

problems, based on knowledge acquired from an expert) are used for supervisory
control.

Centralized computer control:

 A general purpose computer can be program to perform all the require tasks, the
timing differences and the security requirements for the various categories of the
task make the programming job difficult.
 Around 1970s the cost of the computer hardware had reduced to such an extent
that it became feasible to consider the use of dual computer system as shown in
the fig 2.13 below

In the event of failure of one of the computers the other takes over.

 In some schemes the change over is manual in others automatic failure detection
and change over is incorporated.
 These schemes have number of contemporary issues like
 Cabling and interface equipment is not usually duplicated
 Automatic failure and change over equipment when used becomes itself a
critical component.
 Designing, programming, testing and maintaining software becomes very
difficult.
 Multicomputer systems are of two types namely
 Hierarchical system
 Distributed system

Hierarchical system:

 Tasks are divided according to function example one computer is used for DDC
calculations and other is used for supervisory control etc.
 Typical company decision making structure is shown in the below fig 2.14
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 Each decision element receives commands from the level above and sends
information back to that level.
 On the basis of information received from the elements below and from
constraints imposed by elements at the same level, sends commands to the
elements below and information to the elements of same level.
 At the bottom of the hierarchy, a fast response to simple problems is required.
 As system progresses up, the complexity of the calculation increases as does the
time allowed for the response.
 A typical example of hierarchical system is the batch system as shown in the fig
2.15

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RTS notes-2013

 This system has three levels which are called as manager, supervisor and unit
control. It is assumed that single computer is used for the managerial role and
supervisory role and each process is controlled by unit control (computers which
are connected through data highway).
 At the managerial level function such as resource allocation, production
scheduling and process accounting are carried out.
 The important information may be sales order, stock levels, selling cost,
operating cost, etc..,
 The information regarding the production schedule is transferred to the
supervisor.
 It is assumed that supervisor has a store of the operation sequences for making
the product when particular unit is selected, the information are loaded into the
unit controller, also supervisors will receive information regarding status reports
of the productions.
 At the lowest level the unit controllers will operate the plant and will report the
same to the level above them.

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Distributed system:

 In recent schemes a mixture of distributed and hierarchical approach is used as

shown in the fig2.19

 The assumption involved in distribution system are

 Each unit is carrying out essentially similar tasks to all the other units.
 In the event of failure are overloading of particular unit, all or some of the
work can be transfer to other units.
 Here total work is divided up and spread across several computers.
 The disadvantage of such an approach is both hardware and software.
 The advantages of mixed mode system are as follows
 The sharing of task between the processors enhances the system
capabilities. The burden of computation for a single processor become very
great if all the described control features are included.
 The system is more flexible then the use of a single processor.
 Failure of a unit will cause much less disruption in that only a small portion
of the overall system will not be working.
 It is much easier to make a changes to the system, in the form of either
hardware replacements or software changes
 Linking by serial highway means that the computer units can be widely
dispersed.
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Human computer interface(HCI):

 The key to successful adaption of a computer control scheme is often the

facilities provided for the plant operator or user of the system.
 All the relevant information of the current state of its operation should be readily
available and facilities to enable interaction with the plant should be provided.
 The major process control equipment companies have developed extensive
scheme for the presentation of information.
 A typical operator stations has specially designed keyboards and several displays,
video units are frequently provided to enable the operator to see the parts of the
plant.

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Unit 3

Computer hardware requirements for real time application

In this chapter we will discuss the hardware requirements and various issues
related to the design of real time systems also an effort is being made to explain the
concept like interrupts, real time clock and data transfer techniques.

General purpose computer:

 Some of the general purpose computers include XX86 series, Motorola 68XX
series, National 32XX series and Zilog Z80 and Z8000 series.
 A characteristics of computers used in control system is that they are modular
i.e. they provide the means of adding extra units.
 The overall performance of the system depends on the capabilities of basic unit
in terms of its processing power, storage capacity, input/output bandwidth and
interrupt structure.
 Schematic diagram of a general purpose digital computer is shown in fig 2.17
 General purpose computer includes arithmetic and logic, control, register,
memory, input/output units.
 The input/output channels are also very important which provide a means of
connecting process instrumentation to the computers.
 Displays and input devices are provided for the operator.

Central processing unit:

 The arithmetic and logic unit along with control unit and general purpose registers
together make up the CPU.
 ALU contains the circuits necessary to carry out arithmetic and logic operations,
and also contains hardware units to perform multiplication and division of fixed
point numbers.
 General purpose register it can be used for storing data temporarily i.e. while it is
being processed.
 Early computers had a very limited number of general purpose registers.
 Most of the computers now have CPU with many general purpose registers and
hence many computations can be held in CPU without frequently accessing the
main memory.
 The control unit continually supervises the operations within the cpu, it fetches
program instructions from main memory, decode the instructions and sets up
necessary data paths and timing cycles for the executions.
 The features of the cpu which determines the processing power are as follows
1. Word length
2. Instruction set

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3. Addressing method
4. Number of registers
5. Information transfer rates
6. Interrupt structure
 The basic instruction set of the CPU is also important in determining its overall
performance. Features which are desirable are
1. Flexible addressing modes for direct and immediate addressing,
2. Relative addressing modes
3. Address modification by the use of index registers,
4. Instructions to transfer variable length blocks of data between storage units
or locations within memory single commands to carry out multiple
operations.
 These features reduce the number of instructions required perform housekeeping
operations and hence both reduce storage requirements and improve over all speed
of operation by reducing the number of accesses to main memory required to carry
out the operations.

Storage:

 The storage used on computer control system divides into two main categories,
1. Fast access storage
2. Auxillary storage
 The fast access memory is that part of memory which contains data, programmes
and results which are currently being operated on.
 In addition to RAM it is now common to have ROM, PROM or EPROM for the
storage of critical code or predefined functions.
 The use of ROM has eased the problem of memory protection to prevent loss of
programs through power failure or corruption by mall functioning of the software.
 An alternative to ROM is the use of memory mapping technique the trap the
instructions which attempt to store in protected area.
 The auxillary storage medium is typically disk or magnetic tape. These devices
provide bulk storage for programs or data which are required infrequently at
much lower cost than fast access memory.
 The disadvantage is a much longer access time and need for interface boards and
software to connect them to the cpu.
 For real time system use of cpu to carry out the transfer is not desirable as it is
slow and no other computation can take place during transfer.
 For efficiency of transfer it is sensible to transfer large blocks of data rather than
a single word or byte. The approach frequently used is direct memory access
(DMA).
Input and output:

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 The input/output (I/O) interface is one of the most complex areas the computer
system.
 The part of complication arises because of the wide verity of the devices which
have to be connected and wide variations in the rates of data transfers.
 The i/o system of most control computers can be divided into three sections
1. Process i/o
2. Operator i/o
3. Computer i/o

Bus structure:

 Bus is the collection of the conductors which carry electrical signals.

 Buses are characterized in three ways
1. Mechanical (physical) structure
2. Electrical
3. Functional
 The physical form of bus represents the mechanical characteristics of the bus
system.
 The electrical characteristics of the bus are the signal levels, loading and type of
output gates.
 The functional characteristic describes the type of information which the
electrical signals flowing along the bus conductors represent.
 The bus lines can be divided into three functional groups
1. Address lines
2. Data lines
3. Control and status lines

Single chip microcomputers and microcontrollers:

 Many integrated circuit manufacturers produce microcomputers in which all the
components necessary for a complete computer are provided on a single chip.
 Typical single chip device is shown in fig 3.2

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Fig 3.2 A typical single-chip computer.

 The microcontroller is similarly a single chip device that is specifically intended for
embedded system applications.
 The main difference between microcontroller and microcomputer is that
microcontroller will have on-board chip a multiplexed ADC and some form of
process output for example a pulse width modulator unit.
 The chip may also contain a real-time clock generator and a watchdog timer.
Specialised processors:
 Specialised processors have been developed for two main purposes namely
1. Safety critical applications and
2. Increased computation spead
 For safety critical applications the approach is to simplify the instrunction set
which is called RISC(reduced instruction set computer).
 The advantage of simplifying the instruction set is the possibility of formal
verifications.
 Second advantage of RISC machine is that it is easier to write assembler and
complirs for the simple instruction set.
 Increasing the processor speed can increase throughput but eventually system will
reach a physical limit because of the fundamental limitations on the speed at which
an electronic signal can travel.
 The search for increased processing speed has let to the abandonment of von
Neumann architecture for high speed computing.

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Parallel computers:
 Many different forms of parallel computer architecture have been device, they can
be summerised as belonging to one of the four categories
1. SIMD – Single instruction stream, multiple data stream
2. MISD- multiple instruction stream, Single data stream
3. MIMD- multiple instruction stream, multiple data stream
4. SISD- Single instruction stream, Single data stream

 Among all MIMD system are most powerful class of parallel computers as each
processor can pottentialy be excuting a different program on a different data set.
 The most widly used MIMD system is the INMOS transputer.
 Each transputer chip has a CPU, on board memory, an external memory interface
and communication links for direct point to point connection to other transputer.
 An individual chip can be used as a standalone computer, however power of the
transputer is obtained when several transputer are interconnected to form a
parallel processing network.
 INMOS developed a special programming language, OCCAM for use with the
transputer.
Digital signal processor:
 In applications such as speech processing, telecommunications, radar and hi-fi
systems analog techniques have been used for modifying the signal characteristics.
 There are advantages to be gained if such processing can be done using digital
techniques in that the digital devices are inherently more reliable and do not drift.
 Special purpose integrated digital circuits optimised to meet the signal processing
requirements have been developed.
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 They use Harvard architecture in which separate paths are provided for data and
for instructions.
 They are difficult to program as few high level language compilers are available.
 DSPs typically use fixed point airthametic and the instruction set contains
instructions for manipulating complex numbers.
Process related interfaces:
 In many operations there is a need to convert digital quatity to a physical quantity
or vice versa. Most devices can be allocated to one of the following four categories
1. Digital quantities
2. Analog quantities
3. Pulses and pulse rates
4. Telemetry
 Digital quantities: These can be either binary or generalized digital quantity i.e, a
valve open or closed, a switch on or off etc..,
 Analog quantities: The characteristics of these signals is that they are continous
variables and have to be both sampled and digitized. Examples are output from
thermocouples, strain guage etc..,
 Pulses and pulse rates: A number of measuring instruments like flow meters,
provide output in the form of pulse trains. Stepping motors as actuators requires
the provision of pulse outputs.
 Telemetry: The data may be transmitted by landline, radio or the public telephone
network, it is characterized by sending data in serial form usually encoded in
standard ASCII characters. For small quantities of data the transmission is usually
asynchronous.
Digital signal interfaces:
 A simple digital input interface is shown in fig 3.4
 It is assume that the plant output are logic signal which appear on lines connected
to the digital input register.
 It is usual to transfer one word at a time to the computer, so normally the digital
input register will have the same number of input lines as the number of bits in the
computer word.
 To read the lines connected to the digital input register computer as to place
address of the register on the address bus and address decoder selects the
appropriate digital input register.
 In addition to the SELECT signal, an ENABLE signal may also be required

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 In response to select and enable signals the digital input register enables its output
gates and puts data on to the computer data bus.
 The timing of the transfer of information will be governed by cpu timing. A typical
example is shown in fig 3.5
 For this system, it is assume that the transfer requires three cycles T1,T2 and T3.
 The address lines begin to change at the commencement of the cycle T1 and sure
to be valid by the start of the cycle T2, also at the start of T2 the READ line
becomes active.
 For correct read operation the digital input register has to provide stable data at
the negative going edge of the clock during T1.

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Fig 3.5 simplified READ (INPUT) timing diagram.

Digital output interface:
 A simple digital output interface is shown in fig 3.6

Fig 3.6 simple digital output interface.

 A digital output interface requires a register or latch which can hold the data
output from the computer.
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 The enable signal is used to indicate the device that data is stable on the bus and
can be read.
 The output from the latch is a set of logic level typically from 0 to 5v.
 If this logic levels are not adequate to operate actuators, some conversion is done
this conversion is often performed by using low level signals to operate relays
which carry higher voltage signals.
 An advantage of using relays is that there is electrical isolation between plant and
the computer system.
Pulse interfaces:
 In its simplest form, a pulse input interface consists of a counter connected to a
line from the plant.
 The counter is reset under program control and after fixed length of time the
contents are read by the computer.
 Fig 3.7 shows a simple pulse input and output interface.

Fig 3.7 pulse input and output interface.

 The measurement of the length of time for which the count proceeds can be done
either by a logic circuit in the circuit or by computer.
 If the timing is done by computer then enable signal must inhibit the further
counting of pulses.
 Pulse outputs can take variety of forms
1. A series of pulses of fixed duration
2. A single pulse of variable length
3. Pulse width modulation
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 For type 1 the computer turns a pulse generator on or off, or loads a register with
the number of pulses to be transmitted. The pulse output is sent to the process
and used to decrement the register contents, when the register reaches zero the
pulse output is turned off. Example controlling a stepper motor.
 For type 2 the computer raises or lowers a logic line and thus sends a variable
length pulse to the plant. Example controlling of valves.
 For type 3 Pulse width modulation (PWM), special purpose interface chip are used
to generate the pulses.
 Close the related to pulse counters are hardware timers. The hardware timer is
normally a continuously running accurate pulse generator.
 Hardware timers can be used to set the maximum time allowed for the response
from an external device, a special form of this is the watch-dog timer.
 Watch-dog timer is often used on process control computers. The timer is reset at
fixed intervals, usually when the OS kernel is entered, if the watch-dog timer
„times-out‟ it indicates that for some reason the OS kernel as not been entered at
the correct time.
Analog interfaces:
 The analog measurements are converted to digital measurements in two steps like
Sampling and quantization.
 Fig 3.8 shows simple analog input interface.

Fig 3.8 Analog Input System.

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 Sample and hold unit is used to prevent a change in the quantity being measured
while it is being converted to a discrete quantity.
 To operate the analog input interface the computer issues a start or sample signal,
typically a short pulse and in response ADC switches the sample-hold into sample
for a short period after which quantization begins.
 On completion of the conversion the ADC raises a ready or complete line which is
either polled by computer or is used to generate interrupt.
 Multiplexer is used to switch the input from several input lines to single ADC since
using a separate ADC for each analog input is expensive.
 For high level (0 to 10V) signals, the multiplexer usually used is a solid state
device.
 For low level signals, a programmable gain amplifier is usually used between
multiplexer and sample-hold unit.
 Digital to analog conversion is simpler than analog to digital conversion and it is
also possible to provide one convertor for each output.
 A simple analog output system is shown in the fig 3.9

Fig 3.9 Analog output system.

 Each DAC is connected to the data bus and appropriate channel is selected by
putting the channel address on the computer address bus.
 The DAC acts as a latch and holds the previous value sent to it until the next value
is sent.
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Real-time clock:
 A real-time clock is a vital supporting device for control computer systems. The
hardware unit given the name real-time clock is a pulse generator with a precisely
control frequency.
 A common form of the clock is based on using the AC supply line to generate pulses
at 50 or 60 times per second.
 By using slightly more complicated circuitry higher pulse rates can be generated.
 The pulses are used to generate interrupt and the interrupt handling software
counts the interrupts and hence keeps time.
 A fixed frequency pulse generator decrements a counter which, when it reaches
zero, generates an interrupt and reloads the count value.
 The interrupt activates the real-time clock software.
 The interval at which the timer generates an interrupt and precision of clock is
control by the count value loaded into the hardware timer.
 The choice of basic clock interval is a compromise between timing accuracy and
load on the cpu.
 If small interval is chosen i.e., higher precision, then cpu will spend a large
proportion of its time simply servicing the clock and will not be able to perform
any other work.
 The RTC based on the use of an interval timer and interrupt driven software
suffers from the disadvantage that the clock stops when the power is lost and the
restart the current value of the real time as to be entered.
 But at the present time, RTC units with battery backup are available which saves
the time even when the power goes off.
 RTCs are also used in batch processing and online computer system.
 In batch processing systems, they are used to provide date and time on printouts
and for accounting purposes in online system user expects the terminal to appear
as if it is the only terminal connected to the system.

Fig: Dallas semiconductor real-time

Fig: This chip, labelled ODIN, is a
clock from an older PC. This versionData transfer techniques:
generic equivalent to a particular
alsoThe characteristic
contains of most
a battery backed SRAM.interface devices is that they operate synchronously
Dallas RTC
respect the computer and operate at much lower speeds.

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 Programmed transfer is the method in which direct control of the interface devices
by computer and involves use of CPU.
 Programmed transfer gives maximum flexibility of operation but because of
difference in operating speed in CPU and many interfacing devices it is inefficient.
 Another approach is DMA-direct memory access, the transfer requirements are
setup using program control but data transfer takes place directly between the
device and memory without disturbing the operation of CPU.
 In online computing, buffers have been used to collect information before invoking
the program requesting the input.
 This approach is now being extended through the provision of i/o processor for
real-time systems.
 A major problem with data transfer is timing. In program transfer the computer
can make unconditional transfer i.e., the computer can read or write at any time
to the device.
 Another transfer is the conditional transfer where the computer must be sure that
the device ready to accept the next data.
 Conditional transfer can be used for digital inputs.
 Unconditional transfer can be used for analog inputs and pulse inputs.

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Polling:

 Considering the example of printer, the computer will first find whether the device
is ready, if the device is ready then transfer take place. If not, the computer will
keep on checking the status of the device. Hence most of the time is wasted in
waiting rather than performing actual job.
 A software timing loop can be used as an alternate method to a status line on the
interface.
 For example, a delay can be created by loading the register with a number and
repeatedly decrementing register until it reads zero.
 Code snippet- LD B,25 ; Load register B with time delay
LOOP DEC B ; Decrement B
JR NZ, LOOP; Repeat until B is zero
 To ensure that no transfer is made before peripheral is ready, time delay must be
slightly greater than maximum delay, thus this method also inefficient in terms of
CPU use. But reduces the cost.
 An alternate arrangement for conditional transfer is the one shown in fig 3.11
 Here the computer instead of waiting for the device to get ready, checks the
status of the device if ready, transfer takes place if not continuous with the
process and comes back after some time interval to check the status of the device.
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Interrupts:
 An interrupt is a mechanism by which the flow of program can be temporarily
stopped to allow a special piece of software (ISR) interrupt service routine to run.
 When the routine has finished, the program which was temporarily stopped is
resumed.

 Interrupts are mainly used for

1. Real time clock
2. Alarm inputs
3. Manual override
4. Hardware failure indication
5. Debugging aids
6. Operating system
7. Power failure warning
Saving and restoring registers:
 Since an interrupt can occur at any point in a program, precautions have to be
taken to prevent information which is being held temporarily in CPU registers from
being overwritten.
 All CPUs automatically save the contents of the program counter.
 The methods are commonly used are
1. Store the contents of the registers in a specified area of memory.
2. Store the register on memory stack.
3. Use of an auxillary set of registers.

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 The use of automatic storage of the working registers is an efficient method if all
register are to be used.
 The machine status must be restored on exit from the interrupt routine.
Interrupt input mechanism:
 A simple form of interrupt input is shown in fig 3.13

 In between each instruction CPU checks the IRQ line, if it is active, which indicates
interrupt is present, and the interrupt service routine is entered.
 If it is not active then next instruction is fetched and cycle repeats.
 A common arrangement is to have interrupt lines as shown in the fig 3.14

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 One of the lines IRQ is enabled and disabled using software and hence the
computer can run in a mode in which external events cannot disturb the processing
 A second interrupt line is provided; this interrupt cannot be turned off by software
and hence it is said to be a non maskable interrupt(NMI)
 NMI is typically used to provide the power failure detect interrupt.

Interrupt response mechanisms:

 The cpu may respond to the interrupt in any of the following methods
1. Transfer control to a specified address usually in the form of CALL
instruction.
2. Load the program counter a new alue from a specified register or
memory location.
3. Excecute a CALL instruction but to an address supplied from the external
system.
4. Use an output signal- an interrupt acknowledge to fetch an instruction
from an external device.
 Method 1&2 are said to be software biased that is external hardware are not much
involved and rely on software to determine the interrupt source and appropriate
ISR .
 Methods 3&4 are said to be hardware biased i.e they require external hardware
but can identify the interrupt source and can directly transfer the control to ISR.

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Hardware vectored interrupts:

 Hardware biased interrupts require some form of vectored interrupt structure to

identify which of the external device is requesting the service.
 They also require a mechanism to avoid more than one source activating the IRQ
line. The process of arbitration involves assigning priorities to various interrupts.
 A common method is daisy chain arrangement in which an acknowledge signal is
transferred through devices until it is block by the interrupting device.
 Fig 3.15 shows daisy chain arrangement.

Fig 3.15 daisy chain interrupts structure.

 Each unit has an IEI pin (interrupt enable input) and an IEO pin (interrupt enable
output)both pins are active high pins .
 The first IEI is always set high and for any device IEO is high only when interrupt is
not present .
 If IEI is high and IIEO is low,then the device is requesting service .
 If devices requesting any service but IEI pin is low then those devices are not
serviced .
 The above diagram illustrates various devices connected in daisy chain interrupt
structure and the services provided according to the device priority.
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Interrupt vectoring using priority encoding circuit:

 In daisy chain arrangement the device priority is determined by the position of the
device in the chain and cannot be changed by software.
 The determination of interrupt priority can be performed using priority encoder
circuits.
 In this system an interrupt occurring on any line causes the interrupt line (IRQ) to
become active and also places a 3bit code specifying the number of interrupt line
which is active on the data bus.
 In the event of more than one line being active the priority encoder supplies the
number of the highest priority interrupt.

Multilevel interrupts:
 In most of real-time systems a single interrupt level is unacceptable;
 A typical multilevel interrupt is shown in the fig.3.17

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Fig.3.17 Multi-level interrupts.

 An application program is interrupted at regular intervals by clock interrupt which

is the highest priority interrupt.
 When the interrupt occurs control is passed to the clock interrupt service
routine(ISR0).
 During the servicing of the clock interrupt the printer generates an interrupt
request, but since printer is of lower priority than clock, the interrupt from printer
is not serviced until clock ISR is completed.
 When clock ISR is completed, instead of passing the control to main program
control is transferred to printer ISR.
 If the printer ISR does not complete before next clock interrupt, printer ISR is
halted and control is transferred to clock ISR, served and printer ISR is resumed
after completing the printer job, the control is transferred to the main program.
 The interrupts interrupting any other service routine should be restricted to only
higher priority interrupts. This is achived by using a mask register which can be
loaded from software and can be used to inhibit lowest priority interrupts. This
arrangement is shown in fig.3.18

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Fig.3.18 interrupt masking.

Functions performed by ISR:

 Fig.3.19 shows the function performed by an interrupt service routine.

 First the working environment is saved, also current mask register contents are
saved and new mask register values are sent out.

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 The interrupts are now enabled and actual servicing of interrupts starts.
 When servicing are completed, interrupts are disabled, previous mask register
values are restored and working environment is resumed.
 Interrupts can be enabled now and interrupt service routine are exited.

Direct memory access(DMA):

 Data transfers take place directly between the device and memory without
disturbing operation of CPU.
 Three methods are normally used-burst, distributed mode and cycle stealing.
 In burst mode, the DMA controller takes over the data highways of the computer
and locks out the CPU for period of time.
 In distributed mode the DMA controller takes occasional machine cycles from the
CPU control and uses each cycle to transfer a byte of information between fast
memory and backing memory.
 The cycle stealing method only transfers data during cycles when the CPU is not
using the data bus. Therefore the program proceeds at the normal rate and is
completely unaffected by the DMA data transfers.

Comparison of data transfer techniques:

 The polling provides simplest method of data transfers.
 The use of interrupts result in software which is much less structured.
 Interrupt driven system are much more difficult to test since many of errors may
be time dependent.
 In alternative for high rates of transfer is to substitute hardware for software
control and use DMA techniques.

Communications:
 The use of distributed computer system implies the need of communication
between the instruments of plant and lower level computers.
 At the plant level, communication system involve parallel analog and digital signal
transmission since the distances involved are small and high speed is required.
 At higher level, serial communication is used as communication distances are more
hence use of parallel communication increases the cost.
 Parallel digital systems are also limited for short distances as it increases the cost
when used for long distances.
 Fig.3.20 illustrate data transmission links.

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Fig.3.20 Data transmission links.

 Serial communication techniques can be categories in several ways.

1. Mode: synchronous and asynchronous
2. Quantity: character by character and block
3. Distance: local and the remote
4. Code: ASCII and other
 Synchronous and asynchronous transmission techniques.
 Asynchronous transmission implies that both transmitter and receiver circuits use
their own local clock signals to get data from transmission lines.
 For proper data transmission, transmitter periodically sends synchronization
information down the transmission.
 An alternate method is to use a physical connection-a clock wire and periodically
to send a synchronizing signal. The most common form of asynchronous
transmission is the character by character system and was first introduced for
telegraph lines.
 It is also called as “STOP-START system” in this system each character is preceded
by a start bit and followed by one or two stop bits.
 This protocol is shown in fig.3.21

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Fig.3.21 Asynchronous transmission.

 The advantage with stop-start system is that at lower transmission rates frequency
of the clock signal generators need not be closely matched.
 The disadvantage is that for each character three or four extra bits have to be sent
and thus overall information rate is high.
 To overcome the problem of transmitting redundant bits, synchronous system
designed to transmit large volumes of data over short periods use clock
transmissions.
 To establish effective communication more than just a synchronization signal,
additional information called protocol are sent.
 A simple protocol is shown in fig.3.22

Fig.3.22 Synchronous transmission.

 At start of the transmission, bit synchronization is achieved by the transmitter
sending out the sequence of zeros and ones followed by the ASCII code SYN.
 The transmitter will continue sending SYN code until receiver responds by sending
back the ACK code.
 If time elapses, transmitter will resend the sequence.

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 The line will be completely idle when an EOT(end of transmission) character has
been sent by the transmitter.
 The text is broken up into blocks and each block is preceded by an STX character
and ended by ETX character. Followed by ETX will be an integrity check on the
data.
 There are two main standards of synchronous transmission systems,
 BISYNC- binary synchronous communication
 HDLC- high level data link control
 With synchronous transmission there is no need to transmit extra bits to enable
receiver clock hence data transmission rate is high.
 The advantage of block transmission is that a much higher ratio of data bits to
control bits can be obtained.
Local and wide area networks:
 Wide area network operate over wide geographical area at moderate speeds.
 Local area network operate at a wide range of transmission media such as a
twisted pair, co-axial cable, and fibre optics; they use range of different protocols
and topologies.

Fig.3.23 LAN topologies: (a) data bus; (b)star; (c)hierarchy or tree; (d)ring; (e)mesh.

 Data bus: is the simplest of all the LAN topologies. The bus is normally passive and
all the devices are connected to transmitting medium.
 Star network: depends on a central switching node to which all other nodes are
connected by a bidirectional link.
 Hierarchy: the system as many switching nodes, the addition of new nodes is
difficult.
 Ring: this is most used network the ring is typically an active transmission system
i.e, ring itself contains regeneration circuit which amplifies the signal.
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 Mesh: this topologies allows for random interconnections between the various
nodes it provides a means by which alternative routes between nodes can be
found. The prevailing standard is now the HDLC protocol.

Standard interfaces:
 The ISO(international organization for standardisation) have formulated a standard
protocol system in the OSI model.
 This is a layered model with seven layers running from the basic physical
connection to the highest application protocol.
 General structure is illustrated in fig.3.25

Fig.3.25 ISO/OSI seven layer model.

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Unit 5&6

Operating system

What is an Operating System?

 A program that acts as an intermediary between a user of a computer and the
computer hardware.
 Operating system goals:
1. Execute user programs and to resolve user problems easily.
2. Make the computer system convenient to use.
3. Use the computer hardware in an efficient manner.
 Few examples of operating systems.

Fig.5.1 Few Example Of Operating Systems.

 An operating system for a given computer converts the hardware of the system
into a virtual machine with characteristics defined by operating systems.
 Operating systems were developed to assist the operator in running a batch
processing computer later developed to support both real time systems and multi-
access online systems.

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 The most common approach is to incorporate all the requirements in a general

purpose operating system as shown in fig.5.2

Fig.5.2 General purpose operating system.

 Access to the hardware of the system and I/O devices is through operating
systems.
 In addition to supporting and controlling the basic activities, operating systems
provide utility programs for example loaders, linkers, assemblers, and debuggers
as well as real-time support for high level language.
 A general purpose operating systems will provide facilities that are not required in
a particular applications, such features can be omitted during installation.
 Recently, operating systems which provide only a minimum kernel have become
popular, additional features can be added.

Fig.5.3 minimal operating system.

 The relationship between the various section of a simple operating system,
computer hardware and user is shown in fig.5.4

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Fig.5.4 general structure of a simple operating system.

 The command processor provides means by which the user can communicate with
operating system through computer console system.
 Through command processor, the user issues commands to the operating system
and it provides the user with information about the action performed by operating
system the actual processing of commands is performed by BDOS(basic disk
operating system) which also handles input and file operations on the disks.
 Application program will communicate with hardware of the system through
system calls which are processed by BDOS.
 BIOS(basic input and output system) contains various device drivers which
manipulate the physical device.
 Devices are treated as logical are physical units, logical devices are software
construct used to simplify user interface.
 User performs input and output to logical devices and BDOS connects logical device
to the physical device the actual operations of the physical device is performed by
BIOS.
 Access to the operating system is by means of subroutine calls.
 Programmers using high level language cannot call function directly. Hence there
is an isolation between operating system and programs this is usually called
information hiding.
 In such cases connection between operating system and high level language is
performed by complier through provision of run time support routines which
converts operating system to a virtual machine described by high level language.
 Information hiding is used in that details of the physical implementation on the
CPU and I/O devices are hidden within operating system and hence operations are
performed on the operating system virtual machine.
Real time multitasking operating system:
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 Until early 1980s there was a clear distinction between operating systems designed
for use in real-time applications and other types of operating systems.
 But in recent years this distinction has become less.
 The function of a multiuser operating system is as shown in fig.5.5

Fig.5.5 Multi-user operating system.

 The operating systems ensures that each user can run a single program as if they
had the whole of the computer system for their program.
 Although at any given instance it is not possible to predict which user will have the
use of the CPU.
 A primary concern of the operating systems is to prevent, one program from
corrupting another program. Each user program runs in its own protected
environment.
 A multi-tasking operating systems is illustrated in fig.5.6
 In multi-tasking operating systems, it is assumed that single user performs many
tasks and various tasks co-operate to serve the requirements of the user.
 A fundamental requirement of the operating system is to allocate resources of the
computer to various activities(tasks) which have to be performed.
 In real-time operating systems this allocation procedure is complicated since some
activities are time critical and hence has higher priority than others.
 Hence an allocating scheme an scheduling to tasks is a must.
 A task may require to communicate with another task, hence an operating system
must enable tasks to either share memory for exchange of data or to provide a
mechanism by which tasks can exchange messages.

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Fig.5.5 multitasking operating system.

 Also tasks may need to be invoked by external events. Hence operating system
must support interrupts.
 Also tasks may need to share data and may need to access hardware and software
components.
 As a whole real-time multi-tasking operating system can be summarized as follows
1. Task Management: the allocation of memory and processor time
(scheduling) to tasks.
2. Memory Management: control of memory allocation.
3. Resource control: control of all shared resources.
4. Intertask communication and synchronisation.

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 Along with the above functions, the system provides standard features such as disk
files, basic input/output device drivers and utility programs.
 Task management module has the overall control which is responsible for
allocating the use of CPU. This module is often referred to as the monitor or as the
executive control program.
 At the user level, system tasks is also shown since in many operating system some
operations performed by the operating system and the utility programs run in the
memory space allocated to the user or applications- this space is sometimes called
working memory.

Scheduling strategies:

 There are two basic strategies; cyclic and pre-emptive.

Cyclic Strategy:
 The task uses the CPU for as long as it wishes.
 It is a very simple strategy which is highly efficient in that it minimizes the time
lost in switching between tasks.
 It is an efficient strategy for small embedded systems for which the execution
times for each task run are carefully calculated and for which the software is
carefully divided into appropriate task segments.
 This approach is too restrictive since it requires that the task units have similar
execution times.
 It is difficult to deal with random events using this approach.

Pre-emptive Strategies:

 There are many pre-emptive strategies; all involve the possibility that a task will
be interrupted before it has completed a particular invocation.
 The simplest form of pre-emptive scheduling is to use a time slicing approach.
 Using this strategy each task is allocated a fixed amount of CPU time (number of
clock ticks), and at the end of this time it is stopped and the next task in the list is
run.
 If a task completes before the end of its time slice, the next task in the list is run
immediately.
 A common strategy used in real-time operating system is Priority Scheduling
Mechanism.
 Tasks are allocated a priority level and at the end of a predetermined time slice,
the task with highest priority of those ready to run is chosen and is given control of
the CPU.
 Task priorities may be fixed (static priority system) or may be changed during
system execution (dynamic priority system).
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 Dynamic priority schemes can increase the flexibility of the system. Changing
priorities is risky as it makes it much harder to predict and test the behavior of the
system.
 The task management system has to deal with the handling of interrupts. These
may be hardware interrupts caused by external events, or software interrupts
generated by a running task.

Priority structures:

 In a real-time system the designer has to assign priorities to the tasks in the system.
 The priority will depend on how quickly a task will have to respond to a particular
event.
 Most RTOSs provide facilities such that tasks can be divided into three board
levels:
1. Base level
2. Clock level
3. Interrupt level

Fig.5.7 priority levels of RTOS.

 Interrupt Level: At this level are the service routines for the tasks and devices
which require very fast response (measured in msec.) Example: real-time clock
task.

 Clock Level: At this level are the tasks which require accurate timing and
repetitive processing, such as the sampling and control tasks.
 One interrupt level task will be the real-time clock.

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 Typical values 1-200 msec.

 Each clock interrupt is known as a tick and represents the smallest time interval in
the system.
 The function of the clock interrupt handling routine is to update the time of day
clock in the system and to transfer control to dispatcher.
 The scheduler selects which task is to run at a particular clock rate.
 Clock level tasks divided into two categories;
 Cyclic: these are tasks which require accurate synchronization with outside world.
 Delay: these tasks simply wish to have a fixed delay between successive
repetitions or to delay their activities for a given period of time.

 Base Level: tasks at this level are of low priority and either have no deadlines to
meet or are allowed a wide margin of error in their timing. Tasks at this level may
be allocated priorities or may all run at a single priority level.

Cyclic Tasks:

 Cyclic tasks are ordered in a priority which reflects the accuracy of timing required
for the task, those which require high accuracy being given the highest priority
 Tasks of lower priority within clock level will have some jitter since they will have
to await completion of the higher-level tasks.
 Three tasks A, B, and C are required to run at 20 msec, 40 msec and 80 msec
intervals. If the clock interrupt rate is set at 20 msec. if the task priority order is
set as A,B,and C with A as the highest priority.
 The following figures 5.8 and shows task activation diagram for this example in two
cases;
 Case (a): Task priorities are: A, B, then C.
 Case (b): Task priorities are: C, A, then B.

Fig 5.7 task activation diagram for case(a0 and case (b)

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 Now assume that task C takes 25 msec to complete, task A takes 1 msec and task B
takes 6 msec. if task C is allowed to run until completion then the activity diagram
is given bellow.
 Task A will be delayed by 11 msec at every fourth invocation.

Fig.5.8 task activation diagram.

Task States:

 Tasks are in one of four states:

1. Running
2. Ready to run (but not running)
3. Waiting (for something other than the CPU.)
4. Inactive
 Only one task can be Running at a time(unless we are using a “multi-core”CPU).
 A task which is waiting for the CPU is Ready. When a task has requested I/O or put
itself to sleep, it is Waiting.
 An Inactive task is waiting to be allowed into the schedule. It is like Microsoft Word
when you are NOT running it.

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Fig.5.9 tasks states.

Task Descriptor:
 Information about the status of each task is held in a block of memory by the
RTOS.
 This block is called Task Descriptor (TD), or Task Control Block (TCB) or Task Data
Control (TDC).
 The information is held in the TD will vary from system to system, but will
typically consist of the following:
– Task Identification.
– Task Priority.
– Current state of task.
– Area to store volatile environment (or a pointer to an area for storing the volatile
environment).
– Pointer to next task in list.
Example:
 The fig.5.10 shows list structure for holding task state information:
 There is one active task (task ID=10).
 There are three tasks ready to run (ID=20, ID=9 and ID=6). The entry held in the
executive for the ready queue head points to task 20, which in tern points to task
9 and so on.
 The advantage of the list structure is that the actual TD can be located anywhere
in the memory and hence the OS is not restricted to a fixed number of tasks as the
case in older Oss which used fixed length tables to hold task state information.

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Fig.5.10 list structure for holding task state information.

Scheduler and real-time clock interrupt handler:

 The real-time clock handler and the scheduler for the clock level task must be
carefully design as they run at frequent intervals.
 System commands which change tasks status (transition commands).
 The range of system commands affecting task status varies with the operating
system.
 Tasks which are suspended awaiting the passage of time these tasks are marked as
delayed and those tasks waiting for an event or a system resource are marked as
locked out.
 The system does not support base level tasks but lowest four priority level of the
clock level tasks can be used to create a base level system.
 Typical states and commands are shown in fig.5.11

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Fig.5.12 RTOS task state diagram.

 FTX (free time executive) is provided which if used at priority level n-3 where n is
the lowest priority task number.
 The FTX is used run task at priority level n-2, n-1 and n.
 It also provides support for the chaining of tasks.
 The dispatcher is unaware of the fact that tasks at these three priority are being
changed.
 Dispatcher simply treats whichever tasks are in the lowest three priority levels as
low-priority tasks.
 Tasks run under the FTX do not have access to the system commands.

Fig.5.12 RTOS task structure diagram.

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Dispatcher-search for work:

 The dispatcher/scheduler has two entry conditions:
1. The real-time clock interrupt and any interrupt which signals the completion
of an I/O request.
2. A task suspension due to a task delaying, completing or requesting an I/O
transfer.
 This is explained in the flow chart fig.5.13

Fig.5.13 RTOS search for work by the dispatcher.

Memory management:
 The problem of memory management is simpler than for multiprogramming, online
systems because majority of control application software is static.
 With permently resident software fast access memory can be divided as shown in
the fig.5.14
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Fig.5.14 non partitioned memory.

 The user space is treated as one unit and the software is linked and loaded as a
single program into the user area.
 The information about the various tasks is conveyed to the operating system by
means of a create tasks statement.
 The general form of the create tasks statement may be of the form.
Create (tasks id, priority, start address, work space)
 An alternative arrangement is shown in fig.5.15

Fig.5.15 partitioned memor.y

 The available memory is divided into pre-determined segments and the tasks are
loaded into the segments by command processor.
 Partitioned memory or divided memory was used in many early RTOS.
 There was of course a need to keep any tasks in which timing was crucial in fast
access memory permanently.
 To overcome problem of fixed partitions, one method called as floating memory
was used.
 In floating memory the available memory is divided into small blocks and memory
mapping was done i.e., linking and loading of a particular segment of memory
whenever and wherever required.
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 Other systems which permit dynamic allocation of memory allow the tasks
themselves to initiate program segment transfer either by chaining or overlaying.
 Task chaining involves division of task into several segments which run
sequentially. On completion of one segment the next segment is loaded from
memory into the area occupied by the previous segment.
 Task swapping involves one task invoking another task.
 The first task is transferred to backing store and the second task brought into
memory and made available to run.
 Task chaining and swapping is shown in fig.5.16

Fig.5.17 task chaining and swapping.

 The difference between chaining and overlaying is that in overlaying a part of the
task, the root task, remains in memory and the various segments are brought into
overlay area of memory.
 In multitasking system there may be several different overlay areas which may be
shared by several tasks.
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 Dynamic memory allocation is complex to handle and should be avoided wherever

possible in embedded real-time systems.
 RAM is now more affordarable that the cost of adding extra memory is usually
much less than the cost of programming to provide Dynamic memory allocation.
 Dynamic memory allocation should never be used in safety-critical applications.
 Task overlaying is shown in fig.5.18

Fig.5.18 Task overlaying.

Code sharing:

 In many applications same actions have to be carried out in several different tasks.
 In a convential program the action would be coded as a subroutine and one copy of
the subroutine would be included in the program.
 In a multitasking system each task must have its own copy of the subroutine or
some mechanism must be provided to prevent one task interfering with the use of
code by another task.
 The problem which can arise are illustrated in fig.5.19
 If two task share subroutine S. if task A is using S before it finishes some event
occurs which causes rescheduling of the tasks and task B runs and uses S, then
when a return is made to task A, the locally held data will be changed.
 Two methods can be used to overcome this problem:
1. Serially reusable code, and
2. Re-entrant code.

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Fig.5.19 sharing a subroutine in a multitasking system.

Serially reusable code:

 Some form of lock mechanism is placed at the beginning of the routine such that if
any task is already using the routine, the calling task will not be allowed entry
until the task which is using the routine unlock it.
 The use of a lock mechanism to protect a subroutine is an example of the need for
mechanism to support mutual exclusion when constructing an operating system.

Fig.5.20 serially reusable code.

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Re-entrant code:

 If the subroutine can be coded such that it does not hold within it any data i.e., a
pure code (data like intermediate results are stored in the calling task are in a
stack).
 Then the subroutine (pure code) is said to be re-entrant.
 Task descriptor for each task contains a pointer to a data area, swapping between
tasks will not cause any problems.
 Re-entrant routines can be shared between several tasks since they contain no
data relevant to a particular task and hence can be stopped and restarted at a
different point in the routine without any loss of information.
 Device drivers in conventional operating system are frequently implemented using
re-entrant code.

Fig.5.21 use of re-entrant code for code sharing.

Resource Control:
 One of the most difficult areas of programming is the transfer of information to
and from external devices.
 The availability of a well-designed and implemented I/O subsystem (IOSS) in an OS
is essential for efficient programming.
 This enables programmer to perform input output by means of system calls either
from a HLL or from the assembler.
 The IOSS handles all the details of the devices.
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 A typical IOSS will be divided into two levels.

 The I/O manager accepts the system calls from the user tasks and transfers the
information contained in the calls to the device control block (DCB) for the
particular device.
 The information supplied in the call by the user task will be;
1. the location of a buffer area in which the data to be
2. transferred is stored (o/p) or is to be stored (i/p),
3. the amount of data to be transferred,
4. type of data,
5. direction of transfer, and
6. the device to be used.

Fig.5.22 general structure of IOSS.

Detailed arrangement of IOSS:

 The actual transfer of the data between the user task and the device will be
carried out by the device driver and this segment of code will make use of other
information stored in the DCB.
 A separate device driver may be provided for each device.
 A single driver may be shared between several devices; however, each device will
require its own DCB.
 The OS will normally be supplied with DCBs for the more common devices.

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Fig.5.23 Detailed arrangement of IOSS.

Device queues and priorities:
 In real-time system a simple device queue based on a FIFO organization can cause
problems in that the tasks requesting a device effectively loses its priority.

Fig.5.24 printer queue a) buffer request, b) non buffer request.

 In buffered request, the higher priority task including the very high priority task 5
will not gain access to the printer until task 76 releases it.
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 If the tasks have made a non buffered request they will be locked out until they
reach the head of the printer queue.
 However if task 5 has made a buffered request it will be able to continue and if it
runs frequently, then after short period of time the printer queue will continue
several request from tasks 5.
Task co-operation and communication:
 In real-time system tasks are designed to full fill a common purpose and hence
they need to communicate with each other.
 For task co-operation and communication we have the following solutions:
1. Mutual exclusion (MUTEX)
2. Synchronization and
3. Data transfer.
 Mutual exclusion: a multitasking operating system allows the sharing of resources
between several concurrently active tasks.
 The use of some resources is restricted to only one task at a time.
 Some problems can arise if two tasks share a data area and both tasks can write
the data area.
 In abstract terms mutual exclusion can be expressed in the form of
Remainder1
Pre-protocol (necessary over head)
Critical section
Post protocol (necessary over head)
Remainder2
 Remainder1 and remainder2 represents sequential code does not require access to
particular resource are to a common area of memory.
 Critical section is the part of the code which must be protected from interference
from another task.
 Pre-protocol and post-protocol called before and after the critical sections are
code segment that will ensure that the critical section is executed so as to
exclude all other tasks.
 Critical section and protocols must be much shorter than the remainders.
 The protocols represent the over head which has to be paid in order to obtain
concurrency.
 In considering solutions to MUTEX problem it is normal to assume that a number of
so called primitive instructions exists.
 The most widely used form of primitive for the purpose of binary semaphore.
 The semaphore mechanism was first proposed by E.W.Dijkstra in 1968.
 A binary semaphore is condition flag which records wheather or not a resource is
available.
 If for a binary semaphore s, s=1, then the resource is available and the task may
proceed.
 If s=0, then the resource is unavailable and the task must wait.
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 To avoid processor waiting for a resource to become available task have to be

suspended until the semaphore becomes s=1.
 A typical mechanism for doing this is to associate with each semaphore a queue.
 There are only three permissible operation on a semaphore, initialize, secure and
release.

Fig.5.25 example of a task which requires access to a printer.

 Fig.5.26 illustrates the underlying operations which take place as several tasks
attempt to access the same resource.
 The semaphore printer access is initialized to the value1 in step 1,

Fig.5.26 MUTEX using binary semaphore.

The monitor:

 Monitor is a set of procedure that provides access to data or a device.

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 Monitor is used to control resources to achieve MUTEX.

 The procedures are encapsulated inside a module that has the special property
that only one task at a time can be actively executing a monitor procedure.
 The user tasks thus communicates with the monitor rather than directly with the
resource.
 Fig.5.27 shows a simple monitor with two procedures writedata and readdata,
provide access to the data.

Fig.5.27 A simple monitor

 Fig.5.28 shows a more complicated monitor with three entry points and two
conditions.

Fig.5.28 A general monitor.

 The advantage of a monitor over the use of semaphores or other mechanism to

enforce MUTEX is that the exclusion is implicit.
 The only action required by the programmer of the task requiring to use the
resource is to invoke the entry to the monitor.

Inter-task communication:

 We can divide the issues of Synchronisation and communication into three areas.
1. Synchronisation without data transfer.
2. Data transfer without Synchronization.
3. Synchronization with data transfer.
 Task Synchronisation without data transfer
 Signal is a mechanism which is used to inform about the task status.

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 Signal is defined as a binary variable such that if s=1, then a signal has been sent
but not yet being received .
 Associated with a signal is a queue.
 Permissible operations on a signal are initialize, wait and send.
 Differences between signal and semaphore: clearly a signal is similar to
semaphore. The following are the differences;
1. A semaphore is used to secure and release a resource and as
such the calls will both be made by one task.
2. A signal is used to synchronize the activities of two tasks and
one task will issue the send and the other task the wait.
 Data transfer without Synchronization:
 RTOS support pool and channel mechanism for the transfer or sharing of data
between tasks.
 Pool holds data common to several tasks, the write operations on a pool is
destructive and the read operation is non destructive.
 Channel support communication between producers and consumer of data the read
operation is destructive in channel where as write operation is non destructive.
 Channels provide a direct communication link between tasks, normally on a one to
one basis.
 One task is seen as the producer and the other as the consumer.
 There are two basic implementation mechanism for a channel:
1. Queue (linked list) and
2. Circular buffer
 The advantage of the queue is that number of successive messages held in a
channel is not fixed.
 The length of the channel can grow only limit is amount of available memory.
 The disadvantage of the queue is that access time increases as the length of the
queue increases.
 The circular buffer uses a fixed amount of memory, the being defined by the
design of the application.
 Synchronization with data transfer:
 The two main forms of Synchronization with data transfer are
1. The message from the producer task.
2. The signal for consumer task indicating exchange of data.
 Signal is sent each time a message is placed in the channel, either a semaphore or
signal that counts the number of sends and waits, or a counter has to be used.

Liveness:

 An important property of a multitasking real-time system is liveness.

 A system is said to possess liveness if it is free from livelock, deadlock, and
indefinite postponement .
Anand Raj S N, Asst Professor, JNNCE, Shivamogga
 RTS notes-2013

 Livelock is the condition under which the tasks requiring mutually exclusive access
to a set of resources, both enter busy wait routines but neither can get out of the
busy wait because they are waiting for each other. The CPU appears to be doing
useful work and hence the term livelock.
 Deadlock is the condition in which a set of tasks are in a state such that it is
impossible for any of them to proceed.
 The CPU free but they are no tasks to run.
 Indefinite postponement is the condition that occurs when a task is unable to gain
access to the resource because some other tasks always gains access ahead of it.

Minimum operating system kernel:

 In recent years the idea of providing a minimum kernel of RTOS support

mechanisms and constructing the required additional mechanism for a particular
application has been developed.
 One possible set of functions and primitives for RTOS is:
 Functions:
1. A clock interrupt procedure that decrements a time count for
relevant tasks.
2. A basic task handling and context switching mechanism that will
support the moving of tasks between queues and the formations of
tasks queues.
3. Primitive device routines.
 Primitives:
1. WAIT for some condition
2. SIGNAL condition and thus release one or all tasks waiting on the
condition.
3. ACQUIRE exclusive rights to a resource.
4. RELEASE exclusive rights to a resource.
5. DELAY task for a specified time.
6. CYCLE task, i.e., suspend until the end of its specified cyclic period.

Anand Raj S N, Asst Professor, JNNCE, Shivamogga

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