Michel A Lemoupa Fokou

Dodji Monglo

Final Project EE330: Digital Stopwatch/Timer

Introduction
For this final project that we had chosen, we had decided to create a digital stopwatch. The
design will be based of the 0.5µ CMOS process. The project will consist of a few components to
implement the circuit such as the 7-seven segment display to display the stopwatch time. We also
included the use of the modulo-6 counter and the modulo-10 counter to display the output. As we
are using a clock, we have designed a ring oscillator to be set as the timer for the design. The
completed output will be through the post layout simulation.

Part 1 Basics of the Design

There are many different approach that we could take to start the design. However, we started
the implementation of the design using a technique that is familiar with us and that is the use of
verilog. Since we want to test the verilog that we create, we will be using a program that we used
in CprE 281 known as Quartus Prime with testing it on the motherboard Altera. We began with
the verilog of units such as the modulo-6 and the modulo-10 counter. We first began by creating
the verilog of the two counter which then we managed to create the schematic diagram from. We
then proceeded into connecting those counters to the seven segment display which we had used
in our previous time of CprE 281. We then adjust a few components such as including the clock
generator and then start to run the program. We managed to get the overall circuit to be as
following:

Figure 1: Overall design of the Stopwatch

From this overall diagram, we managed to set the clock generator to increment the time of the
clock by every 1.3 seconds. The calculations of this can be seen below on how we managed
to get this timing:
 Clock Speed = 50MHz
Flip-flop = 26 flip flops
50MHz/2^26 = 0.7451 Hz
1/0.7451= 1.3 seconds

We managed to delay the clock by using the combination of flip flops and different logic gates.
There are 26 flip flops that are being used to help delay the current clock of the Altera. With this,
we managed to test if the verilog that we made is done correctly. We then managed to create the
clock generator as shown below:

Figure 2: Clock generator circuit diagram

We managed to test and design the circuit for the clock generator using Cadence. We created the
a ring oscillator to simulate the same clock speed as we got when we used Altera. Below is the
full ring oscillator connection.
 Figure 3: Ring Oscillator
We then designed the inverters appropriately with the given sized to create our intended output
of the clock timing.

Figure 4: Inverter from Ring Oscillator

We then proceeded to test the ring oscillator numerous amount of times to ensure that we
managed to create the most suitable clock timer. We tested the given ring oscillator using
Cadence which we then managed to achieve our intended clock speed of 50MHz. We run the
ADE L that we had used previously in our lab sessions to display the output.
Figure 5: Virtuoso Analysis of Ring Oscillator

Figure 6: Clock Speed of 50MHz

We then create the layout of the inverter when the sizing is differed from the one we used to
during one of the lab session that we had.

Figure 7: Inverter Layout

Part 2 Modelsim Testbench
After we had derived and extracted the verilog of the diagram and for each of the components
used, we then proceed to test thPart 2 Modelsim Testbenche components again. However, this
time, we will test the verilog code using the a program that we had used for this class for labs
and homework, which is Modelsim. From Modelsim, we compile the code to check whether it is
correct and after create a testbench for the verilog code to be simulated.
2.1 Modulo-10 Counter
We first begin with testing the verilog code of the modulo-10 counter and creating the testbench
for the verilog code that we received from the Quartus Prime and adjusted it slightly. Below are
the two verilog codes for modulo-10 counter.

Figure 8: Verilog Modulo-10 Counter

 Figure 9: Testbench Modulo-10 Counter
After we had created the testbench for the verilog code for the modulo-10 counter, we can then
proceed to simulate it. Since we are used to the program and have used it before, we run the
simulation as accordingly and the output is displayed.
 Figure 10: Simulation of Modulo-10 Counter Testbench
We can see that from the simulation, when the enable is turned on, the clock will run up to 9 and
then return back to 0 as it is a modulo-10 counter.

2.2 Modulo-6 Counter

For this section of the design, we will be conducting and adjusting the verilog code to match our
intended output similarly to what we did for modulo-10 counter. We checked and altered the
verilog code and created the testbench for the code.
 Figure 11: Verilog Modulo-6 Counter

Figure 12: Testbench Modulo-6 Counter

Similarly to what we did with the modulo-10 counter, we then proceed to simulate the testbench
of modulo-6 counter.

Figure 13: Simulation of Modulo-6 Counter Testbench

For this simulation, we can see that the simulation runs through the wave from 0 to 5 and then
return back to 0 as it is a modulo-6 counter.

2.3 Overall Design

We then proceed into implementing the full design of stopwatch using only Modelsim and the
use of the verilog given. We managed to get the verilog similarly to how we did in previous
cases and created the testbench as shown below.
 Figure 14: Overall Verilog

Figure 15: Stopwatch Verilog Testbench

We then proceed to run the simulation and managed to get our intended output. The simulation
can be seen as below:

FIgure 16: Overall Design Simulation

From the simulations shown above, we can see that the modulo-10 counter will represent the first
second counter and when it reaches a value after 9, the modulo-6 will be active and will be set as
1 which will represent the value 10. This will continue up to 59 minutes and 59 seconds. We can
also see that whenever the reset is enabled, the stopwatch will reset when it has been stopped.
The reset can be seen with the waveform below.
 Figure 17: When reset is in effect
Part 3 RTL Compiler and Layout
3.1 Modulo-10 Counter
Since the project asks us to simulate the design post layout, we will create the layout for each
individual component that we are using. We will start with the modulo-10 counter. Since we
have the verilog of the unit, we will create the layout similarly to how we did during lab 11. We
will use the RTL compiler and also the encounter to create the intended layout.
We first use the RTL compiler to get the schematic given:

Figure 18: RTL Compiler of Modulo-10 Counter

After that, we proceed to import the circuit into Cadence by following the steps during lab 11
and managed to get the schematic shown below:
 Figure 19: Schematic Diagram in Cadence
Moreover, we then must proceed to create the layout of the modulo-10 counter which we will
use encounter to create based on the verilog and the schematic that we had created. The output
layout will then be:
 Figure 20: Modulo-10 Counter Layout
Once we have the layout, we must run the DRC test and extract the layout. Once it passes the
DRC and the layout is extracted correctly, we can then run the LVS to see if all netlist matches
between the layout and the schematic. It was shown to be matching.
3.2 Modulo-6 Counter
We will then repeat the same steps for the modulo-6 counter by using the RTL compiler,
encounter and the layout. We then will run DRC, extract and then run the LVS.
 FIgure 21: RTL Compiler of Modulo-6 Counter

Figure 22: Schematic Diagram of Modulo-6 Counter

 Figure 23: Layout of Modulo-6 Counter
The layout of the counter has all the netlist matching with the schematic, therefore the LVS was
passed.
3.3 Overall Design
Since we have all the pieces of the puzzle, with the presence of the counters, the ring oscillator,
and the clock generator, we managed to recreate the schematic diagram that we had done in
Quartus Prime and translated it to Cadence. The given circuit diagram below is the end result of
the circuit implementation.
 Figure 24: Overall Schematic Diagram

Conclusion
In the end, we managed to simulate the stopwatch using a hardware known as Altera that could
count upwards and can be start and stopped. The stopwatch could also be reset when we want to.
The components used manage to be implemented as layouts and help create the intended output
which is the digital stopwatch. By using the knowledge we have from the whole semester, we
managed to create the digital stopwatch.