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    ECE270: Embedded Logic Design Mid-Semester Exam (15 Marks) : Date: 16/10/2020 Deadline: 11 AM (Read It As 10.45 Am)

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    Ankit Garg
    1) The document provides details for the mid-semester exam for the course ECE270: Embedded Logic Design. It includes 5 questions worth a total of 15 marks and specifies the deadline, penalty details, and submission instructions. 2) The questions cover topics such as drawing block diagrams from Verilog code, AXI transactions timing diagrams, designing counters with minimum FFs, differences between FPGA LUT architectures, and logic vs bitwise operators. Students are expected to provide code, diagrams, and detailed explanations in their responses.

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    ECE270: Embedded Logic Design Mid-Semester Exam (15 Marks) : Date: 16/10/2020 Deadline: 11 AM (Read It As 10.45 Am)

    Uploaded by

    Ankit Garg
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    1) The document provides details for the mid-semester exam for the course ECE270: Embedded Logic Design. It includes 5 questions worth a total of 15 marks and specifies the deadline, penalty details, and submission instructions. 2) The questions cover topics such as drawing block diagrams from Verilog code, AXI transactions timing diagrams, designing counters with minimum FFs, differences between FPGA LUT architectures, and logic vs bitwise operators. Students are expected to provide code, diagrams, and detailed explanations in their responses.

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    1) The document provides details for the mid-semester exam for the course ECE270: Embedded Logic Design. It includes 5 questions worth a total of 15 marks and specifies the deadline, penalty details, and submission instructions. 2) The questions cover topics such as drawing block diagrams from Verilog code, AXI transactions timing diagrams, designing counters with minimum FFs, differences between FPGA LUT architectures, and logic vs bitwise operators. Students are expected to provide code, diagrams, and detailed explanations in their responses.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    45 views2 pages

    ECE270: Embedded Logic Design Mid-Semester Exam (15 Marks) : Date: 16/10/2020 Deadline: 11 AM (Read It As 10.45 Am)

    Uploaded by

    Ankit Garg
    1) The document provides details for the mid-semester exam for the course ECE270: Embedded Logic Design. It includes 5 questions worth a total of 15 marks and specifies the deadline, penalty details, and submission instructions. 2) The questions cover topics such as drawing block diagrams from Verilog code, AXI transactions timing diagrams, designing counters with minimum FFs, differences between FPGA LUT architectures, and logic vs bitwise operators. Students are expected to provide code, diagrams, and detailed explanations in their responses.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
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    ECE270: Embedded Logic Design

    Mid-Semester Exam (15 Marks)


    Date: 16/10/2020
    Deadline: 11 AM (Read it as 10.45 am): 1) 50% Penalty for submission up to 11.10 am, and
    2) 100% Penalty thereafter.
    Where to submit: Google Classroom

    1. For the Verilog Code given below, draw the block diagram consisting of FFs, adder,
    multiplier depicting the functionality of the code. Explain the block diagram in detail.

    3 Marks
    2. Draw the timing diagram for AXI LITE Write transactions consisting of clk, reset, write
    address, address valid, address ready, write data (32 bit), write strobe, write valid, write
    ready, response data, response valid and response ready. Clearly indicate the master
    and slave for each signal. Show two transactions where first transaction transfers 16-
    bit data while second one transfers 16-bit data.
    2 Marks

    Explain how the above transaction can be improved using AXI Memory Mapped
    protocol and corresponding gain in the throughput. Demonstrate the same using
    timing diagram with all the necessary signals.
    2 Marks

    3. Consider the two counter designs: 1) Counter 1: It is sequential down counter with
    counting sequence of 14,12,10,…,0, 14,12,10,…,0 and so on. 2) Counter 2: It is up
    counter with counting sequence of 1,2,7,1,2,7,1… and so on. Write separate Verilog
    codes for both the counters such that it will use MINIMUM number of FFs when
    implemented on 7-series FPGA. Note that counter has only clock as input. Explain
    the design in detail.

    3 Marks

    Evaluation: Verilog code should be correct in terms of functionality and syntax.


    Code without comments and correct explanation will carry zero marks.

    4. Consider two different FPGAs: 1) FPGA with SLICEL having 4-input LUT (internally
    implemented as two 3-input LUTs in parallel), and 2) FPGA with SLICEL having 8-input
    LUT (internally implemented as two 7-input LUTs in parallel). Explain the differences
    between them in terms of the number of arithmetic/logic functions which can be
    realized along with input size, output size and input constraints, if any.
    4 Marks
    Evaluation: For each LUT size, all the constraints should be clearly mentioned. 0.5
    marks for each important constrained. You should be aware of the constraints (in
    terms of input size etc.) which are important for a given size LUT.

    5. Explain the difference between logic and bitwise operators in Verilog with suitable
    example.

    1 Mark

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