This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2526973, IEEE
Transactions on Power Electronics
1

MultiTrack Power Conversion Architecture

Minjie Chen, Member, Khurram K. Afridi, Member, Sombuddha Chakraborty, Member, and
David J. Perreault, Fellow

Abstract—This paper introduces a MultiTrack power con- Each stage can be optimally designed to only address a portion
version architecture that represents a new way of combining of the system requirements. As a result, the overall system
switched-capacitor circuits and magnetics. The MultiTrack ar- performance is often better, while the total component count
chitecture takes advantages of the distributed power process-
ing concept and a hybrid switched-capacitor/magnetics circuit and complexity is usually higher. In many cases, a multi-
structure. It reduces the voltage ratings on devices, reduces the stage architecture may process the full system energy multiple
voltage regulation stress of the system, improves the component times, imposing a penalty on efficiency. Merged multi stage
utilization, and reduces the sizes of passive components. This power conversion - in which portions of a multi-stage system
architecture is suitable to dc-dc and grid-interface applications are partly merged together, reducing component count and
that require both isolation and wide voltage conversion range. An
18 V–80 V input, 5 V, 15 A output, 800 kHz, 0.93 inch2 (1/16 brick redundancy of power processing while preserving flexibility
equivalent) isolated dc-dc converter has been built and tested to - can thus be a desirable middle ground between true single-
verify the effectiveness of this architecture. By employing the stage and multi-stage conversion.
MultiTrack architecture, utilizing GaN switches, and operating There has been significant recent work in hybridizing
at higher frequencies, the prototype converter achieves a power switched-capacitor and magnetic conversion, with consequent
density of 457.3 W/inch3 and a peak efficiency of 91.3%. Its
power density is 3x higher than the state-of-the-art commercial advantages. Building or merging multi-stage systems incorpo-
converters with comparable efficiency across the wide operation rating switched-capacitor circuits, switched-inductor circuits
range. and magnetically-coupled circuits (e.g., “dc transformers”)
Index Terms—DC-DC power conversion, Switched capacitor has been one fruitful approach [2]–[23]. These three groups
circuits, Magnetic circuits, Passive circuits, Resonant power of circuits are often used as the basic building blocks of
conversion. multi-stage systems. They have complementary advantages
and limitations. Switched-inductor circuits are popular for
their voltage regulation capability. However, basic switched-
I. I NTRODUCTION
inductor circuits suffer in terms of size and performance at

P OWER electronic designs have generally been cost

driven. Simple circuit topologies with low complexity,
low component count, and simple controls have traditionally
high voltage conversion ratios, and their power density is typ-
ically limited by the bulky power stage magnetics. Switched-
capacitor circuits, by contrast, can provide balanced efficiency
been preferred in practical designs. However, with increasing and power density tradeoffs for fixed voltage conversion ratios,
electronic content in industrial and consumer applications, but can not efficiently regulate voltage and have limited volt-
and wider deployment of renewable energy systems, power age conversion ratio options with reasonable component count.
electronics are required to have much higher performance. At Magnetic isolation circuits, i.e. , isolated converters with fixed
the same time, the relative cost of power devices and control voltage conversion ratio (“dc transformers”) can provide high
circuitry has fallen (following the general trend in the semi- voltage conversion ratio, galvanic isolation and soft-switching.
conductor industry). Hence, enhancing system performance However, they often do not maintain high performance across
through more sophisticated circuit architectures is an attractive wide operation range.
option and presents many emerging design opportunities [1]. Leveraging of these different kinds of stages in multistage
Power conversion systems can generally be grouped into architectures has often proved beneficial. For example, a
single-stage architectures and multi-stage architectures. In a switched-capacitor voltage divider and a multi-phase buck
single-stage architecture, multiple tasks (e.g., output voltage converter were cascaded to implement a high performance
modulation, input current shaping) are realized in a single laptop power supply in [12]. The wide-input-range converter
power stage. They have low circuit complexity and simple presented in [13] likewise incorporated a switched-capacitor
control, but cannot achieve high performance while meeting circuit with a switched-inductor circuit in a manner to best
requirements such as wide operating ranges and high power leverage their benefits in low-voltage CMOS. Clever usage
density. Multi-stage architectures have multiple power conver- of switched-capacitor and magnetic stages likewise has been
sion stages with each stage performing one or more functions. demonstrated in multi-output converters [14]. Integrated tech-
niques were applied with switched-capacitor converters at
M. Chen and D. J. Perreault are with the Department of Electrical higher voltages: an on-chip switched-capacitor converter was
Engineering and Computer Science, Massachusetts Institute of Technology,
Cambridge, MA 02139 USA (e-mail: [email protected]; [email protected]). combined with capacitive isolation circuits and magnetics
K. K. Afridi is with the Department of Electrical, Computer, and Energy as the dc-dc portion of a LED driver in [15]. Innovative
Engineering, University of Colorado Boulder, Boulder, CO 80309 USA (e- structures combining switched-capacitor circuits and multi-
mail: [email protected]).
S. Chakraborty is with Texas Instruments Kilby Labs, Santa Clara, Cali- winding coupled magnetics in ac-dc and dc-dc applications
fornia, TX 95052 USA (e-mail: [email protected]). were proposed in [16], [17].

0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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Transactions on Power Electronics
2

More highly coupled use of switched capacitor/magnetic Merged Regulation Stage Multiple Power Tracks
conversion has also been exploited to advantage. For example,
in [18], [19], it was shown that significant system benefits Switched Switched Magnetic
can be obtained by merging the operation of the magnetic Inductor V1 Capacitor Isolation &
V2 Rectification
and switched-capacitor stages through “soft charging” of the
V3
capacitor elements, enabling one or both of higher effi-
Vin Rload
ciency and smaller capacitor size. A few high-performance
high-frequency grid-interfaced LED drivers using merged
circuit architectures were presented in [20]–[22]. Resonant Multiple Voltage
switched-capacitor circuits and other “merged” switched- Merged Isolation Stage
Domains
capacitor/magnetics techniques have also proven advantageous
[24]–[26]. By adding one or more inductive components into Fig. 1. The proposed MultiTrack power conversion architecture comprising
the switched-capacitor circuit structure, enhanced performance multiple voltage domains and multiple power tracks. Its regulation and
isolation stages are merged, hence reducing the amount of power that is “re-
with reasonable regulation capability and/or minimization of processed” by the two-stages.
passive component size can be achieved.
This paper introduces a MultiTrack power conversion ar-
chitecture that represents a new way of utilizing switched- circuit (for transformation and galvanic isolation). While the
capacitor and magnetic circuit elements. It incorporates a hy- circuit subsystems are actually merged, one can understand its
brid switched-capacitor/magnetics circuit structure that splits operation considering the multiple circuit functions as if they
the wide voltage conversion range into multiple smaller ranges, were performed independently: the switched-inductor portion
delivers power in multiple tracks, and functionally merges the of the circuit is principally responsible for voltage regulation;
regulation stage and the isolation stage. The system operates the magnetic isolation portion of the circuit offers isolation
in multiple modes across the wide operation range, with its and voltage scaling (and - if needed - a secondary means of
performance optimized for each operation mode. Compared voltage regulation); and the switched-capacitor circuit creates
to conventional two-stage designs, it gains advantages through multiple related voltage levels (V1 , V2 , V3 , etc.) and many
distributed parallel power processing, rather than multiple stacked current tracks that bridge the other two subsystems.
full power processing, and facilitates reduced device ratings, One advantage of the Multitrack converter is that compo-
reduced magnetics size, improved component utilization, and nents of the subsystems are shared, and their functions are
reduced drive of parasitic transformer capacitances. It also partially merged. The switched-inductor circuit block couples
enables zero-voltage-switching (ZVS or near ZVS) of the into the multiple levels of the switched-capacitor circuit block
transistors used in charge transfer among voltage domains to form a merged regulation stage. Likewise, by using a
without additional elements, which is not available in a single set of switches to perform charge transfer and voltage
traditional switched-capacitor circuit. The proposed approach balancing among different levels of the capacitor stack, and to
embraces trends in the development of semiconductor devices, drive the parallel-track magnetic isolation device, we obtain a
and is suitable for power converter designs operating at high merged isolation stage.
frequencies (close to MHz or higher). This paper is developed Merging the stages in this manner yields a circuit having
from our earlier conference publication [27] and presents improved performance as compared to what could be achieved
extended theoretical analysis and experimental results. with separate stages. In conventional wide input voltage dc-dc
The remainder of this paper is organized as follows: Section converter designs, there is usually a regulation stage (typically
II provides an overview of the MultiTrack power conversion a buck or boost converter) that compresses the variable input
architecture. A basic 2-Track implementation and its oper- voltage to a fixed intermediate bus voltage. This intermediate
ation is introduced in Section III. The 2-Track architecture bus voltage is then processed by a separate isolation stage.
is extended to a generalized MultiTrack architecture in Sec- Since the regulation stage has to be designed for the worst
tion IV. Analysis and discussion about the advantages of the case (peak input voltage and peak input current), the voltage
MultiTrack architecture are provided in Section V. Section VI or current ratings of these components are usually not well
presents several practical design considerations. Experimental utilized: when the voltage is high, the current is usually low;
and benchmark results are provided in Section VII, and when the voltage is low, the current is usually high.
Section VIII concludes the paper. Extended theoretical analysis The proposed MultiTrack architecture improves the compo-
about the MultiTrack architecture is provided in Appendix I. nent utilization through a hybrid switched-capacitor/magnetics
circuit structure. Multiple voltage domains with multiple
ratiometrically-related intermediate bus voltages (V1 , V2 , V3 ,
II. A RCHITECTURE C ONCEPT AND OVERVIEW
etc.) are synthesized using a switched-capacitor circuit struc-
Fig. 1 shows the block diagram of the proposed Multi- ture which also simultaneously acts to drive the isolation stage
Track power conversion architecture. It comprises two merged magnetics. This reduces the number of switches required and
conversion stages that provide the functional benefits of a provides ZVS opportunities for the switches (which is not
switched-inductor circuit (for regulation), a switched-capacitor available in a true switched-capacitor structure). Depending on
circuit (for distributing voltage stress among different levels the input voltage, the switched inductor circuit redistributes the
and providing voltage balancing), and a magnetic isolation regulation stage inductor current into the closest intermediate

0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2526973, IEEE
Transactions on Power Electronics
3

Merged Regulation Stage mechanism that can balance the two stacked bus voltages (VX
Merged Isolation Stage
and 2VX ) formed by the two capacitors (C1 and C2 ). Charge
Switched
Inductor 2VX Switched is transferred through an additional capacitor, C3 , which ties
VX ~ 2VX S1 SA Capacitor Lres1 Magnetic
the two switch nodes together. The capacitive energy transfer
C1 Isolation Vout
LR S2 SB Cres1 Q1 Q2
mechanism ensures VC1 ≈VC2 . It is also possible to envision
Vin
Rload variants in which balancing currents are delivered through the
VX transformer windings. This combination of capacitive energy
SC Q3 Q4 Cout
Lres2
C2 C3
transfer and inverter drive of a multiple-winding transformer
Cres2
SD may be described as a hybrid switched-capacitor/magnetics
circuit structure. This structure performs key functions in the
MultiTrack architecture – the switching of this structure drives
Switched Inductor Hybrid Switched-Capacitor Rectifier Circuit
Circuit Magnetic Circuit Structure the MISO transformer, and at the same time smoothly re-
balances the power processed by different tracks with low loss.
Fig. 2. Schematic of an example 2-to-1 input voltage range 2-Track converter The hybrid structure also enables ZVS of the switches. Res-
comprising a switched-inductor circuit, a switched-capacitor circuit and a
magnetic isolation circuit. The regulation stage and the isolation stage are
onant switched-capacitor and zero-current-switching (ZCS)
merged by a hybrid switched-capacitor-magnetic circuit structure. mechanisms can be included by adding inductive impedances
in the C3 branch and utilize the transformer appropriately.
The merged regulation stage in this 2-Track converter com-
bus voltages, thus effectively reduces the voltage drop across prises inductor LR and switches S1 and S2 . By controlling
the inductor, and reduces the stress on switches (as will be the duty ratio of S1 and S2 , the voltage of C1 is regulated,
discussed in Section V). and the voltage of C2 is effectively regulated through the
A 2-to-1 input voltage range 2-track converter as shown in capacitive energy transfer mechanism. In this embodiment,
Fig. 2 is a simple embodiment of the MultiTrack architec- voltage regulation and dynamic control are achieved by the
ture. This 2-track converter has two related intermediate bus modulation of S1 and S2 . For an input voltage vin between
voltages (VX and 2VX ) and has a 2-to-1 input voltage range VX and 2VX , S1 and S2 are controlled such that the voltages
between VX and 2VX . The relative values of bus voltages VX across C1 and C2 are always VX . If vin is closer to VX , S2 has
and 2VX are synthesized by a 2:1 ladder switched capacitor a higher duty ratio and more charge is delivered to VX ; if vin
circuit structure, whose switches are also used as the inverter is closer to 2VX , S1 has a higher duty ratio and more charge is
switches in the isolation stage. delivered to 2VX . If S1 and S2 are switched in complimentary
We first introduce the merged isolation stage. The merged pulse-width-modulation mode, the duty ratio of S1 that can
isolation stage includes a pair of half bridges (SA /SB and regulate the voltage across C1 and C2 to be VX , d1 , is
SC /SD ) that operate synchronously to drive a pair of iden-
vin − VX
tical resonant tanks (Cres1 -Lres1 and Cres2 -Lres2 ). These are d1 = . (1)
coupled to a multiple-input-single-output (MISO) transformer VX
(whose leakage inductances form Lres1 , Lres2 ), with the out- and the duty ratio of S2 , d2 , is
put tied to a synchronous full-bridge rectifier (Q1 –Q4 ). The vin
isolation stage can be interpreted as two ac power tracks d2 = 1 − d1 = 2 −. (2)
VX
distributed in two stacked voltage domains ([0, VX ] and [VX ,
2VX ]), each processing a half of the total output power. The This is somewhat similar to regulating the output voltage
cross-sectional area of the magnetic core is determined by the of a boost converter, but with VX instead of ground as the
volt-seconds of the secondary winding. The window area of second potential. Other similar control approaches (e.g. DCM
the magnetic core is determined by the output current. Thus, control, constant on-time control, current-mode control) can
the power conversion stress of the merged isolation stage in also be used.
this 2-Track converter is the same as a conventional series-
resonant converter based dc transformer, indicating equivalent III. E XTENDED M ULTI T RACK A RCHITECTURE WITH
magnetics volume and efficiency. This MultiTrack configu- W IDE I NPUT VOLTAGE R ANGE
ration distributes the concentrated device voltage-ratings on The basic 2-Track converter shown in Fig. 2 is suitable
the high-voltage side into multiple devices, which can take for applications in which vin ∈ [VX , 2VX ] with a restricted
advantage of the distributed power processing concept [29]– nominal 2-to-1 input voltage range. Moreover, by adding two
[32]. Moreover, as will be shown shortly, the current driven additional switches (S3 and S4 ) in the regulation stage as
through the common-mode capacitances of the transformer is shown in Fig. 3, the converter can handle any desired input
much smaller than that in a single-primary-winding design. voltage range in the [0, 2VX ] region (i.e. [Vmin , Vmax ] ∈
This effect is beneficial in high frequency or high turns-ratio [0, 2VX ]), so long as the components are sized appropriately.
designs. It is in some respects similar to a series-primary The voltage ratings of C1 and C2 are both VX . The
parallel-secondary configuration [28] with similar advantages, operation of this enhanced design can be split into two regions
whereas only a single magnetic core and a single rectifier is determined by the input voltage vin . When vin ∈ [0, VX ],
needed. S3 and S4 are switching, S1 is kept off, and S2 is kept on.
SA –SD are reused to create a capacitive energy transfer The inductor LR , switches S3 and S4 formulates a ground

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Transactions on Power Electronics
4

Merged Regulation Stage

Merged Isolation Stage Benefiting from the 2-Track architecture, the magnitude of
Switched
the voltage applied across the inductor LR never exceeds VX ,
2VX Switched
Inductor S1 SA Capacitor even if the maximum input voltage is 2VX . The charge coming
Lres1 Magnetic
Isolation from the input source is always delivered to the closest dc
C1 Q1 Q2
S3 S2 SB Cres1
Rload voltages to the input. For example, if vin ∈ [0, VX ], power
Vmin ~ Vmax
VX SC Cout
coming from vin is always delivered to the VX node; if
LR Lres2 Q3 Q4
S4 C3 vin ∈ [VX , 2VX ], power coming from vin is always delivered
Vin
C2 SD Cres2 to the VX node and the 2VX node. As will be analyzed, the
smaller resulting voltage imposed on the inductor, and the
Switched Inductor Circuit Hybrid Switched-Capacitor Rectifier Circuit
largely compressed voltage conversion ratio of the regulation
Magnetic Circuit Structure stage can significantly reduce the inductor size, the current
ripple, and/or the regulation loss.
Fig. 3. An example 2-Track power converter that can handle wide input
voltage range. For this converter, the maximum input voltage, Vmax , must be
One can even use a higher-order capacitor stack to create
smaller than 2VX . more intermediate voltages and power delivery tracks if a
wider input voltage range is desired. Figure 5 shows an
2VX 2VX
example 3-Track converter. Implementations with more tracks
can be created following a similar pattern. By creating n
S1 off, S2 on S1 ɸ1 To Transformer S1 ɸ1 To Transformer
power tracks, the power conversion stress is further distributed,
C1 C1
S3 S2 ɸ2
S3 S2
ɸ2 the voltage across the inductor is further reduced, and the
LR
VX
ɸ1
C3 VX
ɸ1
C3 effective voltage conversion ratio is further compressed, at the
LR S4
S4
Vin
C2
Vin
C2 expense of higher component count and control complexity.
ɸ2 To Transformer S3 on, S4 off ɸ2 To Transformer
As analyzed in Appendix I, these advantages don’t scale up
0 < Vin < VX VX < Vin < 2VX
linearly with the number of tracks, but will gradually saturate
(a) Low Input Voltage Mode (b) High Input Voltage Mode in a manner that may be likened to the gradually saturated
advantages of multi-phase interleaving techniques [29]–[32].
Fig. 4. Two operation modes of the two pairs of half-bridges in the regulation
stage of a 2-Track converter: (a) when 0 < vin < VX , S3 and S4 are Note the voltage ratings S4 and S6 in Fig. 5 are 2VX and
switching, S1 is kept off, and S2 is kept on; (b) when VX < vin < 2VX , S3 3VX , respectively. All other switches on the primary side
is kept on, S4 is kept off, and S1 and S2 are switching. have a voltage rating of VX . The wide input voltage range
is divided into three sections [0–VX ], [VX –2VX ], and [2VX –
3VX ]. The control of the 3-Track converter is an extended
referenced boost converter that feeds current into the VX node. version of the 2-Track converter – the input voltage is tapped
The switched capacitor circuit balances the voltages of C1 and to the switch node of a half-bridge that has the closest voltage
C2 . When vin ∈ [VX , 2VX ], S3 is kept on, S4 is kept off, level to minimize the voltage conversion stress. SA –SF are
and S1 and S2 are switching. The LR , S1 and S2 formulates operated as a 3:1 ladder switched capacitor circuit with 50%
boost-type converter structure that feeds power from the input duty ratio. SA , SC , SE are synchronized as one phase, and
into both the VX and the 2VX node. Fig. 4 illustrates the SB , SD , SF are synchronized as the other phase. Energy is
operation of the switches in these two operation modes. transferred between adjacent voltage domains by C4 and C5 .
Within each subsection of the voltage domain, conventional Detailed operation of 2:1 and 3:1 switched capacitor circuits,
feedback control for boost converters (e.g. a classic PWM and corresponding loss analysis can be found in [10], [11]. The
control) can be directly utilized in the proposed MultiTrack difference between the hybrid switched-capacitor/-magnetics
architecture. When the input voltage fluctuates between two structure and conventional switched-capacitor circuits is that
regions, a hysteresis control can be utilized to stabilize the the switches in the prior circuit are reused as inverters that
mode transition. drive the transformer windings, and can benefit from soft
Figure 4 shows the two different operating modes of the switching owing to the additional magnetic loading.
merged regulation stage. Depending upon the operating mode, If S4 and S6 are implemented as multiple cascaded devices,
the switched capacitor charge transfer is used differently to such as shown in Fig. 6, all switches on the primary side
maintain voltage balance between the two stacked capacitors. can be implemented with a voltage rating of VX . Additional
When the input voltage is low (vin < VX ), S3 and S4 operate protection can be provided by using the intermediate bus
as a boost converter and the input power is injected into the voltage(s) to provide voltage clamping for the devices (e.g.
VX node only (Fig. 4a). When the input voltage is between one can add a few small protection diodes, e.g., D1 –D3 ,
VX and 2VX , S1 and S2 operate as a boost converter and the to ensure voltage sharing of the stacked low-voltage-rating
input power (from the input inductor) is injected into both devices). This modification is beneficial in discrete designs as
the VX and 2VX nodes (Fig. 4b), and the total voltage of the considered here, and would also be desirable in an integrated
two stacked capacitors serve to counter the input voltage (in circuit (IC) implementation [10], [15] if the peak device
providing volt-seconds balance on the inductor). The switched voltage rating is constrained by the fabrication process.
capacitor energy transfer operates to redistribute charge such The MISO transformer in the isolation stage has multiple
that the different windings of the isolation stage magnetics can primary windings and a single secondary winding. One can
be utilized equally. synthesize different tank structures to realize the isolation

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Transactions on Power Electronics
5

3VX Regulation Stage Isolation Stage

S1 SA Switched Vmax
Lres1 Inductor
C1
S1 Vout
SA Magnetic
S2 SB Cres1 Vmin ~ Vmax Cres Lres Isolation Q1 Q2
S3 2VX Rload
LR C1
SC vin S2 Cout
C2 C4 Lres2 SB Q3 Q4
S5 S4
SD Cres2 Q1 Q2
LR VX
Vout
SE Q3 Q4 Cout Fig. 7. Schematic of a conventional boost-type two-stage (BTS) converter
C3 Lres3
S6 C5
Vin having a boost converter as the regulation stage, and a series-resonant
SF Cres3
converter as the isolation stage.

Fig. 5. An example 3-Track power converter that can handle arbitrary input voltage by an isolation stage with a fixed voltage conversion
voltage range. ratio.1 Interestingly, the BTS converter could be thought of as
a 1-Track embodiment of the MultiTrack architecture: there
3VX
is only one power track and one intermediate voltage level.
S1 SA
Lres1 Alternatively, the n-Track circuit could be thought of as related
C1
S2
to a “distribtued” embodiment of a BTS circuit, with n equal-
SB Cres1
S3 2VX voltage levels stacked on top of each other. Each domain has
1 1
D1
C2
SC
C4 Lres2 n of the rated input voltage, and processes n of the full rated
S4a power. The capacitive energy transferring mechanism ensures
S5 S4b SD Cres2 Q1 Q2
LR VX the power balancing of all distributed voltage domains.
S6a
D2
C3
SE Q3 Q4 Cout
Vout
To quantify the advantage of the MultiTrack architecture, we
Lres3
C5
Vin
S6b D3 compare the 2-Track converter to a BTS converter for an input
S6c SF Cres3
voltage range of [Vmin , Vmax ]. The intermediate bus voltage
of the conventional BTS converter is assumed to be Vmax .
The two intermediate bus voltages of the 2-Track converter
Fig. 6. A modified 3-track converter with uniform switch voltage ratings,
which facilitates potential integrated circuit implementation. By replacing S4 are 21 Vmax and Vmax . A generalized comparative analysis
and S6 with low voltage rating cascaded switches (S4a , S4b , S6a , S6b , S6c ), considering n-Track converters is provided in Appendix I to
all primary side devices in this schematic have a voltage rating of VX . One investigate how the advantage scales as the number of tracks
can add a few protection diodes (e.g. D1 -D3 ) with small footprints and low
current rating to help ensure voltage sharing of the cascaded switches. increase.

A. Reduced Regulation Inductor Size.

stage for different purposes, e.g., LLC converters, series- Both the BTS converter and the 2-Track converter have a
resonant converters, dual-active-bridge converters. If planar voltage regulation inductor (LR ) in the regulation stage. The
transformers are utilized, a systematic magnetics modeling size of LR is related to the maximum amount of energy that
technique [33] that can rapidly estimate the impedances and it needs to buffer in each switching cycle, which is related
current distribution can be utilized to advantage, as is done in to the voltage conversion ratio of the regulation stage [39].
the design of Section V. We define ΓE as the ratio between the energy buffered in the
Many known rectifier structures (e.g. center-tapped recti- inductor in each switching cycle, and the total energy that
fier, current-doubler rectifier, full bridge rectifier, switched- the converter delivers in each switching cycle. For a fixed
capacitor step-down rectifier [34], etc.) are compatible with output power, a higher ΓE ratio indicates a higher inductive
the MultiTrack architecture. A full bridge rectifier with high energy buffering requirement, yielding a larger inductor size.
transformer winding usage and high experimental flexibility is As derived in Appendix I, the ΓE of the BTS converter when
selected as the example in this paper. One can also envision an vin ∈ [Vmin , Vmax ] is
implementation with multiple secondary transformer windings,
separate rectifiers and separate outputs, which benefits the vin
ΓE,BTS |vin ∈[Vmin ,Vmax ] = 1 − . (3)
distribution of power processing at the expense of higher Vmax
component count. 1 A buck-type two-stage architecture with a buck converter as the regulation
stage is also widely used, especially in telecom power converters. In a buck-
IV. C OMPARATIVE A NALYSIS type implementation, the wide input voltage range is first regulated to a voltage
that is lower than or equal to the minimum input voltage. The analysis results
The boost-type two-stage (BTS) power conversion architec- for such a converter would be quite similar in terms of device stresses and
ture as shown Fig. 7 is widely used in wide input voltage energy storage requirements. Since the Buck converter is a topological dual
of the Boost converter, many of their theoretical characteristics are similar or
range applications, e.g. grid-interface power factor correction even identical. The MultiTrack design we have implemented is more related
(PFC) circuits [35]–[38]. In the BTS architecture, the input to the boost-type two-stage architecture because its regulation stage is more
voltage is at first boosted to an relatively fixed intermediate similar to a boost converter. As a result, we use the boost-type two-stage
architecture as a benchmark in this paper. We note that Multi-track converters
bus voltage that is equal to or higher than the maximum input utilizing buck or buck/boost combination front-end topologies are likewise
voltage. This voltage is then converted into the desired output possible.

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Percentage of Energy Buffered by the Inductor Normalized Switch Conduction Loss

1 25
BTS
2-Track
0.8 20
!E =0.6

max
n#(Pin/Vmax) 2RV
!E=EL/Etotal

0.6 15

0.4 10
!E =0.2
Normalized Loss = 2.98

0.2 5 Normalized Loss = 1.59

BTS
2-Track
0 0
0 0.2 0.4 0.6 0.8 1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Normalized Input Voltage v in/V max Normalized Input Voltage v in /V max

Fig. 8. Fraction of energy buffered by the regulation inductor in each Fig. 9. Normalized switch conduction loss as a function of the normalized
switching cycle (ΓE = EL /Etotal ). EL is the energy buffered by the input voltage range. The 2-Track converter has a lower conduction loss than
inductor. Etotal is the total energy processed by the full system. the Boost converter (1-Track) converter across the full input voltage range.

ΓE increases monotonically as the input voltage reduces. This where S µn EC 3

is a constant that is related to the material
is because the boost converter in the BTS architecture has a characteristics (“Baliga Figure-of-Merit”).
higher voltage conversion ratio if the input voltage is lower. In a BTS converter, SA and SB must each blocks Vmax .
The inductor needs to be sized for the worst case - when the Assuming that both of them have the same drain-to-source
input voltage equals to Vmin . The ΓE of a 2-Track converter resistance RVmax , and the regulation inductor has small current
is a piecewise function of vin . As derived in Appendix I, the ripple, the total conduction loss in the two switches can be
ΓE when vin ∈ [0, 21 Vmax ] is calculated as a function of the input voltage (vin ) and input
vin power (Pin ):
ΓE,2−Track |vin ∈[0, 12 Vmax ] = 1 − 1 . (4)
2 Vmax Pin 2
LossBTS = ( ) RVmax . (7)
The ΓE when vin ∈ [ 21 Vmax , Vmax ] is vin
In a 2-Track converter, S1 , S2 and S3 need to block Vmax
2 .
(Vmax − vin ) vin − 12 Vmax


ΓE,2−Track |vin ∈[ 12 Vmax ,Vmax ] = . According to (B-1), with the device resistance is a quadratic
1
2 Vmax vin function of the rated voltage, their resistance can be approxi-
(5) R
mated as V4max . S4 needs to block Vmax , and its resistance is
(3)–(5) are plotted and compared in Fig. 8. The ΓE of the RVmax . As derived in Appendix I, when vin ∈ [0, 12 Vmax ], the
2-Track converter is lower than that of the BTS converter total conduction loss in the devices of the switched-inductor
across the full input voltage range. As labeled in Fig. 8, if the circuit can be estimated as
input voltage range is [0.4Vmax , Vmax ], the peak maximum
2
ΓE of the 2-Track converter is one third lower than that of Pin
Loss2−Track = 2 RVmax .
(8)
the BTS converter, indicating significant (approximately 3x) 2vin
reduction in inductor size. This advantage is similar to the
reduced inductor size in three-level or multi-level boost [36] When vin ∈ [ 12 Vmax , Vmax ],
or buck [40] converters. 2
Pin vin
Loss2−Track = 2 RVmax (1 − ). (9)
vin Vmax
B. Reduced Switch Conduction Loss and Switch Stress.
(7)-(9) are plotted and compared in Fig. 9. As labeled in Fig. 9,
The switches in the regulation stage of the BTS converter
if vin ∈ [0.4Vmax , Vmax ], the estimated conduction loss of the
(S1 and S2 ) have to block the peak input voltage (Vmax ). In the
2-Track converter is ideally approximately half of the BTS
2-Track converter shown in Fig. 3, S1 , S2 and S3 only need to
converter.
block 12 Vmax . S4 still needs to block Vmax , but it only conducts
In this idealized estimation, the difference between the die-
for a portion of the input voltage range. This mechanism
area of the Boost/Buck converter and the die area of the n-
reduces the conduction loss of the switches. Consider a simple
track converter is not rigorously controlled. The MultiTrack
model that gives an approximate estimate of the loss reductions
architecture reduces the voltage and current ratings of its
that are ideally available, it is derived in [41] that for an ideal
devices by having higher component counts (with divided
Schottky junction device, the on-resistance (per die area) of
voltage/current ratings). A precise theoretical comparison con-
the drift region is a quadratic function of its rated voltage VB ,
sidering these effects is beyond the scope of this paper. For a
4VB2 specific die area and a specific n-track converter, the optimal
Rdson−1 = 3 , (6) die-area allocation on each device also depends on the input
S µn EC

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voltage range and the rms current carried by each devices in SA SA SA

iSA iSA1 iSA2
the worst condition. All these factors may impact the tradeoff Lres1 Lres1

analysis in a specific design. C1 SB Cres1 C1 SB SB Cres1

SC SC SC
Lres2 Lres2
C. Soft-Switching and Reduced Switching Loss C3 C3
C2 SD Cres2 C2 SD SD Cres2
In the regulation stage, conventionally, the high-side switch
of a boost converter (S1 in Fig. 7) can operate as a diode,
with zero-voltage turn on. Under PWM operation with small Hybrid operation ≈
= Switched capacitor
mechanism
++ Series resonant mechanism

inductor current ripple (continous conduction mode, CCM), iSA iSA1 iSA2
the low side switch (S2 ) is usually hard-switched at both
Combined current waveform Hard switching Soft switching
turn on and turn off. The rated voltage of S2 is Vmax . And current waveform current waveform
S2 always switched with its drain-to-source voltage equals
Vmax regardless of vin . In an 2-Track converter, the low- Fig. 10. The hybrid switched-capacitor/magnetics circuit structure can be
side switches (S2 and S4 ) may also be hard-switched with approximated as the superposition of a hard-switched hard-charged ladder
switched capacitor circuit, and multiple stacked ZVS resonant circuits.
CCM operation. The voltage ratings of these switches are
1
2 Vmax and Vmax , respectively. Although their voltage ratings TABLE I
are different, when they are switching, their off-state drain- B ILL OF M ATERIALS (BOM) OF THE P ROTOTYPE C ONVERTER
to-source voltages are always 12 Vmax , which is half of the
switching voltage of the devices in the BTS converter (Vmax ), Device Symbol Component Description
yielding reduced total switching loss. Moreover, given the
S1 –S4 , SA –SD EPC2016c
reduced ranges over which an individual switch set must be LR Coilcraft EPL6024-522ME: 5.2 µH, 44
operated, it can be easier to realize soft-switching of the boost mohm, height (measured): 2 mm
stage, with consequent performance or size benefits. Cin X5R Ceramic, 100 V, 2 µF, 1206
In the merged isolation stage, the combination of the C1 , C2 X7R Ceramic, 50 V, 10 µF, 1206
C3 X7R Ceramic, 50 V, 15 µF, 1206
switched capacitor circuits and the MISO transformer (the
Cout X5R Ceramic, 10 V, 188 µF, 0805
hybrid switched-capacitor/magnetics circuit structure) creates Cres1 , Cres2 Each consists two paralleled capacitors:
both soft-switching and soft-charging opportunities for the One C0G ceramic, 50 V, 0.1 µF, 1206;
switched-capacitor switches [13], [18], [24]–[26]. In the 2- One X7R ceramic, 50 V, 0.2 µF, 1206;
track converter shown in Fig. 3, the operation of SA -SD can MISO Transformer Ferroxcube EQ13, Core material 3F45,
turns ratio 4:4:1, 8-layer PCB layers
be interpreted as the superposition of a switched-capacitor
and 2 external 2 oz foil layers.
circuit and two series-resonant circuits. As shown in Fig. 4, Q1 –Q4 EPC2023c
the switched-capacitor circuit consists SA –SD , C1 , C2 , and
C3 . Here SA and SB are one pair of half bridge switches.
SC and SD are another pair of half bridge switches. SA and regulated at 40 V and 80 V, respectively. A simplified bill-
SC are synchronously switched as one phase, and SB and of-materials (BOM) of the prototype is listed in Table I.
SD are synchronously switched as the other phase. Energy Fig. 11 shows the gate drive implementation of the eight
is transferred by C3 across the two voltage domains. primary-side switches (S1 –S4 and SA –SD ). Two identical gate
At the same time, SA , SB , Cres1 , and Lres1 formulate one drive modules are utilized. S1 , S2 , SA and SB are driven by
series-resonant circuit, and SC , SD , Cres2 , and Lres2 formu- one gate drive module referred to the 12 Vmax node. S3 , S4 ,
late another series-resonant circuit. The two series-resonant SC and SD are driven by another gate drive module referred
circuit are coupled by the transformer, adding one additional to the ground. Each gate drive module contains one linear
path for energy transfer that can operate together with the regulator, four level-shifters and two half-bridge gate drivers
switched capacitor energy transfer. When the input voltage is (TI LM5113). The ground referenced gate drive module can
low, significant power is processed by the switched-capacitor be powered by VX or by Vin . The 21 Vmax referenced gate
mechanism – the switches consequently see a net capacitive drive module is powered by C1 . This gate drive configuration
load and are hard-switched; when the input voltage is high, is well suited to the MultiTrack architecture - the additional
the power is processed by the series-resonant mechanism (and cost of driving switches in the floating voltage domains is
delivered to the output) is sufficient for switches to have a net minimized. It can be easily integrated and extended to drive
inductive load, enabling zero-voltage-switching (ZVS) of the the switches in an n-track implementation. An auxiliary power
switches, which is beneficial for high frequency designs. source comprising an additional transformer winding (4-turns)
with full-bridge diode arrays and linear regulators is utilized
V. P ROTOTYPE D ESIGN to power the two secondary-side half-bridge gate drivers.
To demonstrate the advantages of the MultiTrack power A Texas Instruments TMS320F28069 micro-controller with
conversion architecture, an 18 V–80 V input, 5 V output, 15 4 PWM channels is utilized to control the prototype. As
A output, 75 W, 800 kHz, 2-Track converter has been built explained in Fig. 4, there are two operating modes for the
and tested. The prototype is designed based on the schematic regulation switches (S1 –S4 ): (1) when the input voltage is
shown in Fig. 3. The two intermediate voltage levels are between 18 V and 40 V, S2 is kept on, S1 is kept off, and

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Module #1
LDO vcc1 Primary
2VX Winding #1 42.8 nH
Half Bridge Half Bridge
Gate Driver Gate Driver 1:1
SA Level Shifters
4.45 nH
Ground SB gS1

To Switch Gates
Referenced 106 nH Secondary
Signals S1 gS2 Winding
S2 gSA Primary 44.8 nH 4:1 366 nH
Winding #2
gSB
VX 1:1

GND
Module #2 Fig. 14. Experimentally extracted cantilever model of the prototype MISO
LDO vcc2 transformer.
VX
Half Bridge Half Bridge
Gate Driver Gate Driver
SC Level Shifters
Ground to 40 V, S1 and S4 are kept off, and S2 and S3 are kept on.

To Switch Gates
Referenced
SD gS3
Signals S3 gS4 S2 and S3 may be switched off for a short time every long
S4 gSC period to reset their level-shifting capacitors. Modulating
gSD the difference between the on-time of S2 and S3 would
GND provides the desired voltage regulation capability when
GND the input voltage fluctuates around 40 V.
3) High Input Voltage Mode: when the input voltage is above
Fig. 11. The gate drive implementation of the primary side switches. Two 40 V, S3 is mostly kept on, and S4 is mostly kept off. S4
identical gate drive module are stacked in two voltage domains. This gate
drive implementation can be easily extended and utilized in an n-track may be switched on for a short period of time every few
implementation. Note the level-shifters for the ground-referenced switches switching cycles to reset the boost-strap capacitor of S3 .
(S3 , S4 , SC , and SD ) are not necessary, and are not implemented in the And S1 and S2 are switched at the PWM frequency.
prototype.
Measured waveforms illustrating these three operating
Vout modes are shown in Fig. 13.
BAT54XY The regulation inductor should be designed such that it
TAR5SB50
5V Q1 5V Q2 can work efficiently across the wide input voltage range and
2 turns LDO
power range. Low profile is also a critical requirement in this
Half-Bridge Half-Bridge
Gate Drive Q3 Gate Drive Q4 prototype as the inductor tends to be the tallest component on
LM5113 LM5113
the board. We choose to size the inductor such that it has 50%
Gate signal from
primary side Digital current ripple when the input voltage is at 30 V, the output
Isolator
SI8420
power is 75 W, with 800 kHz switching frequency. The average
inductor current is 2.5 A, and the calculated inductance value
Fig. 12. Secondary side gate drive circuitry consisting of two auxiliary turns is 3.75 µH. A low profile Coilcraft inductor (EPL6024-522)
on the transformer (generating +/-10V), one full bridge rectifier (BAT54XY),
one LDO (TAR5SB50), one digital isolator (SI8420), and two half-bridge
with 2 mm measured thickness is utilized to implement this
gate drivers (LM5113). This gate drive implementation can be modularized inductor. Its loss across the overall input voltage range is
and utilized in designs with multiple output ports. within the loss budget. It is the tallest component on the
board. It also becomes a major loss component when the
input voltage is close to the minimum of the full voltage
S3 and S4 switch; (2) when the input voltage is between 40 range (e.g. 18 V< vin <25 V). A custom designed inductor
V and 80 V, S3 is kept on, S4 is kept off, and S1 and S2 with larger area and lower thickness could further improve
switch. In actual operation, neither of S2 and S3 can be kept the power density and efficiency of the prototype (for example,
on continuously - an interval is needed to enable the boot-strap reducing the inductor height from 2 mm to 1.5 mm could raise
and level shifter capacitors to be refilled periodically. Also, the overall converter box power density from 453.7 W/in3 to
when the input voltage is very close to 40 V, it is a challenge higher than 500 W/in3 .).
to modulate the duty ratio of S2 and S3 because their duty The multiple ac-tracks in the isolation stage are imple-
ratios are either very close to unity or zero. To address these mented as low Q series resonant converters. The resonant
practical issues, we implemented a “Dual Modulation Mode” inductance of each low Q tank is created using the leakage
operation in the experimental setup, in which both the two inductance of the transformer, together with the PCB trace
half-bridge pairs are modulated: inductances. Since the resonant tank has low Q (when loaded
1) Low Input Voltage Mode: when the input voltage is below with the equivalent rectifier resistance of 0.33 ohm at full
40 V, S1 is mostly kept off, and S2 is mostly kept on. S2 power), close matching between the two primary windings is
may be switched off for a short period of time (minimum not necessary. The ac resistance of the secondary winding of
transistor on-time) every few switching cycles (10–20 the MISO transformer needs to be minimized because it has
cycles) to reset the level-shifter capacitor of S2 . S3 and to carry the full output current (up to 15 A).
S4 are switched at the PWM frequency. A Ferroxcube EQ13 core with 3F45 material was selected
2) Dual Modulation Mode: when the input voltage is close based on core loss and winding loss analysis for the isola-

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V2 Vsw V2 Vsw Vsw

V1 V1 V2

V1
IR IR
IR

(a) Low Input Voltage Mode (b) Dual Modulation Mode (c) High Input Voltage Mode

Fig. 13. Example operation waveforms of the prototype converter working in three different operation modes. Vsw is the voltage of the switch node between
SA and SB . V1 is the voltage of the switch node between S3 and S4 . V2 is the voltage of the switch node between S1 and S2 . IR is the current of the
regulation inductor. (a) Low Input Voltage Mode: vin =20 V, Iout =7 A, with S1 and S2 switched at 80 kHz, and S3 and S4 switched at 800 kHz; (b) Dual
Modulation Mode: vin =40 V, Iout =9.5 A, with two half-bridges both switched at 80 kHz; (c) High Input Voltage Mode: vin =60 V, Iout =10 A, with S1
and S2 switched at 800 kHz, and S3 and S4 switched at 80 kHz. The dual-modulation frequency was selected as 80 kHz in this demonstration. This low
frequency fluctuation only exist in the inductor current, and has negligible impact on the system efficiency.

tion transformer. It was selected also because it has suitable

window-area/core-area/height combinations. The printed cir- 42.8 nH
Cantilever model with
cuit board (PCB) winding was designed based on the planar 1:1 4.45 nH experimentally extracted
magnetics modeling approach presented in [33]. The windings element values
106 nH
were fabricated on a 8-layer PCB with 2 oz copper on each
44.8 nH 4:1 366 nH
layer. The finished pcb board thickness is 52 mil (1.32 mm). 42.8 nH
1:1
Layers 1, 2, 7, 8 each have two series-connected turns. Layers
1. Ignoring the mutual 4.45 nH
1–2 are connected in series through blind vias to implement
inductance between the
a 4-turn primary winding. Layers 7–8 are also connected in two primary windings 44.8 nH 366 nH
series through blind vias to implement another 4-turn primary 42.8 nH
4:4:1
winding. Layers 3–6 are utilized to implement the single-
4.45 nH
turn secondary winding with the four layers connected in 2. Connecting the two
parallel. Two additional 2 oz foil layers were attached on 44.8 nH 366 nH primary windings in series
top and bottom of the PCB board. They are connected as 8:1
42.8 nH

added parallel secondary windings to enable a “symmetric- 142.4 nH

interleaving” configuration [33] to reduce the ac resistance and 3. Reflecting the secondary leakage
inductance to the primary side 44.8 nH 370.5 nH
provide the design flexibility.
142.4 nH
The loop inductance between the two legs of the secondary 185.2 nH 8:1

winding also contributes to the series-resonant tank. Utilizing 4. Splitting the series connection
the method provided in [42], the loop inductance is estimated and merging the inductances
187.2 nH
to be about 3 nH. The trace inductances added by the switches 370.5 nH

are estimated to be about 0.5 nH. Fig. 14 shows the cantilever Simplified estimated model
4:4:1
for resonant tank design
circuit model of the transformer extracted by doing open- and
short-circuit measurements.
We seek to simplify the cantilever model to facilitate Fig. 15. Simplification of the the cantilever model for the transformer to
facilitate the resonant tank design.
convenient design of the series-resonant tank of the Multi-
Track converter. Figure 15 illustrates a suggested four-step
approach. This approach is generally applicable to multi- •Step 3: the secondary side leakage inductance is reflected
winding transformers whose windings are driven by multiple to the primary side and combined with the primary side
identical voltage sources (e.g. by a switched-capacitor circuit): leakage inductances.
• Step 1: the mutual inductance between the two primary • Step 4: the 8-turn primary winding is split into two 4-turn
windings (the 106 nH inductance in Fig. 14) can be primary windings. Each winding has a half of the total
neglected because the two primary windings are driven primary side leakage inductance.
by two identical voltage sources. Based on the estimated primary-side-lumped leakage induc-
• Step 2: the two 4-turn primary windings can be connected tance, the resonant capacitance is tuned to be 300 nF to set
in series to formulate a single primary winding having 8 the L-C resonant frequency to be around 700 kHz–750 kHz.
turns (assuming good current sharing between the two Fig. 16 shows a picture of the prototype 18 V–80 V input,
primary windings). 5 V output, 75 W isolated dc-dc converter and a US quarter.

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Figure 17 shows component placement on the top and bottom

sides of the PCB board. There are four modular switch and
gate drive circuits on the primary side. Each modular switch
and gate drive circuits consists of two switches (EPC2016c)
formulating a half-bridge, one LM5113 half-bridge gate drive,
and the corresponding signal paths. They are placed on the
top side of the PCB board. The full bridge rectifier consists
four switches: two of them are on the top side of the board,
two of them are on the bottom side of the board. The opto-
coupler, linear regulator, capacitors and other auxiliary circuits
and chips are placed on the bottom side of the board. The
regulation inductor (LR ) is placed on the left-bottom corner Fig. 16. The MultiTrack 18 V–80 V input, 5 V output, 75 W, isolated dc-dc
of the PCB board. The microcontroller, Texas Instruments converter, and a US quarter.
TMS320F28069, interfaces with the prototype through a 10-
pin interface. If a custom control IC was implemented, the Level-shifters Ladder SC Rectifier
10-pin interface, and many discrete logic components could
Four Planar
be removed to further reduce the board area. An example Xformer
Modular
MultiTrack IC controller implementation would include a Cells
controller for voltage regulation (e.g., a PI controller which Control Gating
observes the output voltage and adjusts the duty ratio), a mode Interface power
selection circuit which determines the operation mode based Signal
on the input voltage, associated drivers and miscellaneous buffers
logics, and monitoring circuits. Opto-
coupler Planar
Xformer

0.6 inch
VI. E XPERIMENTAL R ESULTS
Regulation
A state-of-the-art commercial 1/16 brick 18 V–75 V in- Inductor
put, 5 V output, 75 W isolated dc-dc converter (PowerOne
UIS48T14050 [43]) was utilized to benchmark this MultiTrack LDOs DC Cap & Resonant Cap Output Cap
prototype. This converter has the highest power density among 1.55 inch
commercial converters with similar input voltage range and
the same output voltage that the authors were able to find. Fig. 17. Component placement on the top and bottom side of the PCB board.
The four modular half-bridge cells contain level shifters, LDOs, gate drivers
It is speculated to be a forward converter and has two major and switches.
magnetic components with similar size - one inductor and one
transformer. The PCB board is relatively thick, suggesting high
current and heat transfer capability. 1.55 inch
1.3 inch

Fig. 18 compares the form factors of the two converters.

Both converters have two magnetic devices - one transformer
0.6 inch

0.9 inch

and one inductor. Benefiting from the MultiTrack architecture

and the higher switching frequency, the inductor of the Mul-
tiTrack converter is about six times smaller than the inductor 0.93 inch2
utilized in the commercial converter (80 mm3 v.s. 480 mm3 ) 1.17 inch2
and is much thinner. The distributed power devices in the 0.42 inch
MultiTrack architecture also facilitate use of a much thinner
0.177 inch
PCB board, because heat generation is naturally distributed
across the board. The box power density of the MultiTrack
prototype is 457.3 W/inch3 , which is 3.2 times higher than 457.3W/inch3 11.5W/g 142.5W/inch3 4.6W/g
the 143.5 W/inch3 of the commercial product (the rated power
MultiTrack Prototype UIS48T14050
is defined under 200 LFM 25 ◦ C air flow and 125 ◦ C peak
device temperature). The prototype weights 6.53 g, which is Fig. 18. Form factors of the prototype MultiTrack converter (left) and
42.7% of the 15.3 g of the commercial product, and has a a comparable commercial converter (PowerOne UIS48T14050, right). The
MultiTrack prototype has similar area but is three times thinner with much
somewhat smaller overall surface area. As will be shown, the smaller inductor. Note that the (oversized) micro-controller (TMS320F28069)
MultiTrack prototype has lower maximum-board-temperature, of the MultiTrack converter is off-board in the experimental prototype.
even though it dissipates a similar amount of heat, and has
higher power density.
Fig. 19 shows the measured efficiency of the MultiTrack with a 2.4 W fan providing the air flow). The prototype
prototype with an ambient temperature of 25 ◦ C at 200 LFM converter achieves a peak efficiency of 91.3% when the
air flow (measured using a Pyle PMA90 digital anemometer input voltage is 58 V and when the output current is 8 A.

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95 Average Board Temperature (Celsius)

80 0. 100
0.9 9

8
0.804.8
Input Voltage (V)

0.8
90
Efficiency (%)

20V

9
30V 60 80

0.
85
0.91

0.9
40V

0.88
0.8 0.84
80 50V 40 60

0.
60V

9
0.8 0.9
75 70V
20 8 0.88 40
80V 0.8
70 300LFM/25C air flow
0 5 10 15 0 5 10 15 20
Output Current (A) Output Current (A) 0 5 10 15 20 25 30 35 40 45 50 55
Time (mins)
(a) (b)
Peak Board Temperature (Celsius)
100
Fig. 19. Measured Efficiency of the MultiTrack converter over the 18 V-80
V input, 0 A-15 A output range (200 LFM, 25◦ C air flow). 80

60
95
80 40 PowerOne
300LFM/25C air flow
Input Voltage (V)

90
0.8

0.88
89 .88
Efficiency (%)

20V
0. 0.87
0 5 MultiTrack

0.
0.9 .88 0.8
0.89

88
85 30V 60 20
40V 9 0 5 10 15 20 25 30 35 40 45 50 55
0. 0.9 Time (mins)
50V
0.99 0 7

80 0.91
0.8 0.85

40
0.8

0.9
0.8

60V 1
0.
0.92
1

92

75 70V
20 Fig. 22. Measured (a) average board temperature and (b) peak board
75V
70 temperature of the MultiTrack converter and the commercial converter. Both
0 5 10 15 0 5 10 15
Output Current (A) Output Current (A)
converters are delivering 7 A with 42 V input voltage.
(a) (b)

Fig. 20. Measured Efficiency of the PowerOne converter over the 18 V–80 mal images of the MultiTrack converter and the commercial
V input, 0 A–15 A output range (200 LFM, 25◦ C air flow). converter when they are operating in the same steady-state
condition (41 V input, 5 V output, 7 A output, 0 LFM 25◦ C
95.2C air flow, measured using a FLIR SC300 thermal camera).
Figure 22 shows the recorded peak and average temperature
curves of the two converters working under this condition,
with and without the 300 LFM air flow. As a result of the
thinner board and the reduced weight, the temperature of the
MultiTrack prototype rises and falls faster than the commercial
27.4C product, but its peak temperature was actually lower than that
(a) Experimental Setup (b) Thermal Image of the commercial product. Applying 300 LFM 25◦ C air flow
significantly reduces the temperature of both converters. It
Fig. 21. Thermal image of the MultiTrack converter and the comparable can be concluded that either with or without air flow, the
commercial converter when they are working with 42 V input voltage and
7 A output current (0 LFM, 25◦ C air flow).
MultiTrack converter enjoys a better thermal profile than the
commercial converter, benefiting from the distributed power
processing concept.
Its efficiency is comparable to the commercial product but In this prototype design, a simple feed-forward control
shows a beneficial profile: when the input voltage is high, based on a look-up table was implemented in the micro-
the MultiTrack converter is more efficient; when the input controller. The duty ratio of the regulation stage is pre-
voltage is low, the commercial converter is more efficient. determined based on the desired input voltage and output
The efficiency of the MultiTrack prototype is relatively fixed power. Fig. 23a shows the startup transient waveforms of the
across the 18 V–80 V input voltage range because operation converter when the input voltage ramps up from 0 V to 30 V.
across wide input voltage range is split into multiple voltage The voltages of the switched capacitors and the output voltage
domains. The converter operates similarly in each voltage follow closely with the startup input voltage. Figure 23b
domain, although the input voltage is different. In contrast, shows the input transient waveforms of the converter when the
the efficiency of the PowerOne UIS48T14050 spans across a input voltage steps from 35 V to 55 V (across the operation
wide range (as shown in Fig. 20). Its efficiency when vin = 18 boundary). Since the operation of the regulation stage jumps
V is about 5% higher than its efficiency when vin = 75 V). directly from one state to another, a transient spike of 200 mV
With similar efficiency performance, the MultiTrack proto- was observed in Vout . Closed-loop control and external filters
type dissipates a similar amount of total heat power through can be utilized to improve the transients.
a roughly similar surface area (but with a thinner circuit Figure 24 shows the transient waveforms of the converter
board), while the overall temperature rise is lower. In the when the load current steps between 4 A and 12 A. Figure 25
MultiTrack converter, heat is generated by multiple distributed shows the transient waveforms of the voltages of the node
devices, across a thinner printed circuit board, providing a VX and 2VX in both ac coupling and dc coupling when the
more uniform thermal distribution. Figure 21 shows the ther- load steps from 4 A to 12 A. Due to the increased voltage

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10 ms/div, Bandwidth 250 MHz 4 ms/div, Bandwidth 250 MHz 40 us/div, Bandwidth: 250 MHz 40 us/div, Bandwidth: 20 MHz
Iout : 2A/div Vin : 50V/div
2VX: 1V/div
Vout : 2V/div Vout : 200mV/div 2VX: 10V/div

VX: 1V/div
Vsw : 20V/div Vsw : 50V/div VX: 10V/div
Vin : 20V/div
V1: 50V/div
(a) Input voltage startup (b) Input voltage step up (a) VX step : dc coupling (b) VX step : ac coupling

Fig. 23. (a) Input voltage startup transient waveforms when the input voltage Fig. 25. Measured VX transient waveforms when the load steps from 4 A
ramps up from 0 V to 30 V with 3.6 A load; (b) Input voltage step up transient to 12 A and the input voltage is 60 V: (a) dc coupling; (b) ac coupling.
waveforms when the input voltage ramps up from 35 V to 55 V with 3.6 A In both ac and dc, the voltage of the VX node follows closely in half with
load. Probe bandwidth: 250 MHz; Iout : output current; Vout : output voltage; the voltage of the 2VX node, indicating rapid and smooth switched-capacitor
Vsw : voltage of the switch node between SA and SB ; V1 : voltage of the voltage balancing.
switch node between S3 and S4 .
0.8
200 mV/div
0.6
200 us/div, Bandwidth: 250 MHz 200 us/div, Bandwidth: 250 MHz Iout = 5 A
Iout: 10A/div 0.4
Iout: 10A/div
Vout: 200mV/div Vout: 200mV/div
0.2
Iout = 10 A
0
Vsw: 50V/div Vsw: 50V/div
-0.2
Iout = 15 A
V1: 50V/div V1: 50V/div -0.4
(a) Load step up (b) Load step down
-0.6

Fig. 24. Transient waveforms when the load current steps between 4 A to 12 A 5 us/div, Bandwidth 20 MHz
-0.8
and the input voltage is 60 V: (a) step up; (b) step down. Feed-forward control; 0 0.5 1 1.5 2 2.5 3 3.5
-5
Probe bandwidth: 250 MHz; Iout : output current; Vout : output voltage; Vsw : Fig. 26. Steady state output voltage ripple when the is 5 A, output xcurrent
10
voltage at the switch node between SA and SB ; V1 : voltage at the switch 10 A, and 15 A, respectively (bandwidth: 20 MHz, input voltage 60 V). A
node between S3 and S4 . low frequency ripple (80 kHz) is observed due to the operation mechanism
introduced in Fig. 13.

200 LFM 25 oC air flow

drop in the isolation stage as a result of the higher load, the 500
125 oC maximum device temperature
duty ratio of S1 needs to be slightly increased to maintain the 450
output voltage, yielding step-up transients in VX and 2VX . In
400
this experimental setup, VX steps from 40 V to 42.5 V, and MultiTrack Prototype
2VX steps from 80 V to 85 V. In both ac and dc coupling 350 Input Voltage Range: 18 V-80 V
Power Density (W/inch3)

measurements, the voltage of the VX node follows closely in 300

Commercial Products
half with the voltage of the 2VX node, indicating rapid and Input Voltage Range: 18 V-75 V
250
smooth voltage balancing of the switched capacitor circuit.
Figure 26 shows the output voltage ripple when the converter 200
delivers 5 A, 10 A, and 15 A, respectively. The peak-to-peak Delta PowerOne UIS
150 DelphiE36
output voltage ripple is maintained within 300 mV. A low Synqor PQ400
100 muRata UWS
frequency ripple (about 80 kHz) with a period of ten switching Ericsson PKU
cycles is observed, due to the low frequency operation of the 50
GE Hammerhead
switched-inductor circuit described in Fig. 13. Delta DelphiV36
0
88.5% 89.0% 89.5% 90.0% 90.5% 91.0% 91.5%
Fig. 27 plots the efficiency and power density of the
Peak Efficiency with 48V Input Voltage (%)
MultiTrack prototype and many state-of-the-art commercial
products (with the power density defined under 200 LFM
Fig. 27. Comparison of MultiTrack converter with many state-of-art com-
25 ◦ C air flow with 125 ◦ C allowable device temperature). All mercial products. The MultiTrack converter achieves 3x higher power density
of these commercial products have 18 V–75 V input ranges while maintaining comparable efficiency performance. Note that the prototype
and 5 V output. They utilizes Silicon devices and switch at MultiTrack converter does not include the micro controller on board, though
area is provided for a 10-pin connector to the micro controller (and is included
frequencies in the range of 200 kHz–300 kHz. By employ- in the density calculation).
ing the proposed MultiTrack power conversion architecture
with reduced inductor size and PCB thickness, switching at
higher frequency, and taking advantage of miniaturized GaN VII. C ONCLUSIONS
switches, the MultiTrack converter achieves 3x higher power A MultiTrack power conversion architecture that is suitable
density while maintaining comparable efficiency. for designing isolated dc-dc converters with wide input volt-

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13

age range is presented in this paper. This power conversion 𝒌 iR

𝑽𝑿 = 𝑽
𝒏 𝒎𝒂𝒙
architecture represents a new way of combining switched- Ipk=2Iavg
SX Ipk
capacitor circuits and magnetics. It leverages the complemen- LR
tary strengths of switched-inductor, switched-capacitor, and 𝒗in Iavg T
magnetic isolation circuits, and gains mutual benefits from iR SY
the way they are merged together. As demonstrated in the t
𝑽𝑿 − 𝒗𝒊𝒏 𝒗𝒊𝒏 − 𝑽𝒀
prototype, by processing power in multiple voltage domains 𝒌−𝟏 𝒅𝒀 = 𝒅𝑿 =
𝑽𝒀 = 𝑽𝒎𝒂𝒙 𝑽𝑿 − 𝑽𝒀 𝑽𝑿 − 𝑽𝒀
𝒏
and current channels, multiple advantages can be achieved (a) (b)
with the MultiTrack architecture to miniaturize wide-input-
voltage-range isolated dc-dc converters. Fig. 28. The regulation circuit can be treated as a direct converter having
Vin , VX and VY as the three node voltages.

ACKNOWLEDGEMENTS
Percentage of Energy Buffered by the Inductor
1
The authors would like to thank Texas Instruments and the 1-Track
2-Track
MIT Center for Integrated Circuits and Systems (CICS) for 3-Track
supporting this work. 0.8 4-Track
5-Track
6-Track

!E=EL/E total
0.6
A PPENDIX I: E XTENDED T OPOLOGY A NALYSIS

In this appendix, we investigate how the advantages of 0.4

the MultiTrack architecture scale with the number of tracks
increases.
0.2

A. Generalized Inductor Energy Storage Analysis

0
0 0.2 0.4 0.6 0.8 1
In the MultiTrack architecture, the full input voltage range Normalized Input Voltage v in /V max
is split by the n intermediate bus voltages (VXk = nk Vmax ,
k=1, ..., n) into n voltage domains. The inductor energy buffer- Fig. 29. Fraction of energy buffered by the regulation inductor in each
ing ratio ΓE is a piecewise function of the input voltage switching cycle (ΓE = EL /Etotal ). EL is the energy buffered by the
vin . When vin is located in the k-th voltage sub-section inductor. Etotal is the energy processed by the full system.
( k−1 k
n Vmax <vin < n Vmax ), the regulation circuit can be mod-
eled as a direct converter having vin as the input voltage
level, and k−1 k
n Vmax and n Vmax as the two output voltage
levels, as illustrated in Fig. 28a. Figure 28b shows the inductor ELR
current iR assuming the converter works in critical continuous- ΓE,n−track | k−1 Vmax <vin < k Vmax ] =
n n Etotal
conduction-mode (CCM). In critical CCM mode, the inductor (VX − vin )(vin − VY )
is fully charged and discharged, yield the highest inductor = (A-4)
(VX − VY )
utilization ratio. The average current of iR is Iavg , and the k

k−1


peak current of iR is Ipk = 2Iavg . The switching period is n Vmax − vin vin − n Vmax
= 1 ,
Tsw . The total energy that is processed by this circuit in each n max vin
V
switching cycle is ΓE is plotted in Fig. 29 as a function of the normalized input
voltage ( Vvmax
in
). The ΓE of an 1-Track converter is identical to
1 the ΓE of a boost converter, while the ΓE gradually reduces
Etotal = vin × Iavg × Tsw =Vin Ipk Tsw . (A-1)
2 as the number of tracks increases. Figure 30 compares the
The inductance value that allows critical CCM operation is maximum ΓE of multiple n-track converters as a function
of the input voltage range (Vmax /Vmin ratio). For a specified
input voltage range (Vmax /Vmin ratio), increasing the number
(VX − vin )dX Tsw (VX − vin )(vin − VY )Tsw
LR = = . of tracks can reduce the maximum ΓE , yield smaller regulation
Ipk Ipk (VX − VY ) inductor size. As the number of tracks increases, the marginal
(A-2)
advantage of adding more tracks gradually saturates. By taking
The peak energy that is buffered in the inductor LR is
the derivative of ΓE relative to vin , it can be calculated that
in each voltage sub-section, ΓE reaches the local maximum
1 2 1 (VX − vin )(vin − VY )Tsw Ipk when vin equals the geometrical mean of the two adjacent
ELR = LR Ipk = . (A-3)
2 2 (VX − VY ) intermediate voltages
The percentage of energy that is buffered in the inductor when p p Vmax
vin belongs to k−1 k
n Vmax ↔ n Vmax region, ΓE , is
vin = VX VY = k(k − 1) . (A-5)
n

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Transactions on Power Electronics
14

Percentage of Energy Buffered by the Inductor 2

Normalized Switch Conduction Loss
1 10
1-Track
2-Track
3-Track
0.8 4-Track
5-Track

max
6-Track
101

n#(P in /Vmax )2R V

0.6
max(!E)

0.4
0
10 1-Track
2-Track
3-Track
0.2
4-Track
5-Track
6-Track
-1
0 10
0 2 4 6 8 10 10-1 100
Input Voltage Range V max/V min Normalized Input Voltage v in /V max

Fig. 30. Maximum fraction of energy buffered by the regulation inductor in Fig. 31. Normalized total switch conduction loss as a function of the nor-
each switching cycle (ΓE = EL /Etotal ). For a fixed overall power, ΓE is malized input voltage vin /Vmax . The reference value (Pin /Vmax )2 RVmax
proportional to the inductor size. is the conduction loss of a 1-Track converter when vin = Vmax .

When k > 1, the maximum ΓE when vin is located in the

k-th voltage domain is Normalized Switch Conduction Loss
102

max(ΓE,n−track | k−1 Vmax <vin < k Vmax ] )

qn n

√ √
q
k k−1
n Vmax − n Vmax
max

k− k−1 (A-6) 101

=√
n#(P in /Vmax )2R V

=q q √ .
k
Vmax + k−1 Vmax k+ k−1
n n

For a 1-Track converter, the ΓE as a function of the

normalized input voltage Vvmax
in
is 100 1-Track
2-Track
vin 3-Track
ΓE,BTS |vin ∈[Vmin ,Vmax ] = 1 − , (A-7) 4-Track
Vmax 5-Track
6-Track
which is equal to the ΓE of a BTS converter. 10-1
100 101
Input Voltage Range V max/V min
B. Generalized Switch Conduction Loss Analysis
The conduction loss of a circuit is related to the voltage and Fig. 32. Normalized total switch conduction loss as a function of the input
voltage range Vmax /Vmin . As the input voltage range spans, the total switch
current rating of its devices. It is derived in [41] that for an conduction loss increases
ideal Schottky junction device, the on-resistance (per die area)
is a quadratic function of its rated voltage VB ,

4VB2 The total conduction loss is a piecewise function of the

Rdson−1 = 3 , (B-1)
S µn EC input voltage vin . Using our idealized scaling rules, we
where S µn EC 3
is a constant that is related to the material can approximate the impact of the MultiTrack system on
characteristics (“Baliga Figure-of-Merit”). the device conduction loss. When vin is between k−1 n Vmax
In an n-Track converter, all high-side switches in the and nk Vmax , a total of (k − 1) switches (S2n−1 , S2n−3 , ...,
R
modular half-bridge pairs (S1 , S3 , S5 , ..., S2n−1 ) need to S2n−2k+3 ) with their resistances equal to Vnmax 2 are kept on
RVmax
block Vmax and are conducting. One n2 switch (S2n−2k+1 ) and one
n . According to (B-1), since the device resistance
(n−k)2
is a quadratic function of the rated voltage, their resistance n2 RVmax switch (S2n−2k ) are conducting with a duty ratio
R (n−k+1)2
can be approximated as Vnmax 2 . RVmax is the on-resistance per vin n
of ( Vmax − k + 1); and one RVmax switch (S2n−2k+2 )
n2
die area of a switch that need to block a voltage of Vmax . is conducting with a duty ratio of (k− Vvmax
in n
). The input current,
The low side switches in the modular half-bridge pairs (S2 , iin , is also a function of vin , iin = Pin /vin . Assume the
S4 , S6 , ..., S2n ) need to block ( n1 Vmax , n2 Vmax , n3 Vmax , ..., inductor current equals the input current and has no ripple. The
n
n Vmax ), respectively. And their resistances would ideally scale total conduction loss in the devices of the switched-inductor
RVmax 22 RVmax 32 RVmax n2 RVmax
as ( n2 , n2 , n2 , ..., n2 ). circuit can be estimated as

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[13] D. M. Giuliano, M. E. D’Asaro, J. Zwart and D. J. Perreault, “Minia-

turized Low-Voltage Power Converters With Fast Dynamic Response,”
P2 1 IEEE Journal of Emerging and Selected Topics in Power Eletron., vol.2,
Lossn−Track = (k − 1) 2in 2 RVmax
vin n no.3, pp. 395–405, Sept. 2014.
2 [14] S. M. Ahsanuzzaman, J. Blackman, T. McRae and A. Prodic, “A Low-
(n − k)2
 
Pin 1 vin n Volume Power Management Module for Portable Applications based on
+ 2 2
RVmax + 2
RVmax ( − k + 1)
vin n n Vmax a Multi-output Switched-Capacitor Circuit,” Proc. of the IEEE Applied
Power Electronics Conference and Exposition (APEC), pp. 1473–1479,
P 2 (n − k + 1)2
 
vin n 17-21 March 2013.
+ 2in RVmax (k − )
vin n2 Vmax [15] C. Le, M. Kline, D. L. Gerber, S. R. Sanders and P. R. Kinget, “A
(B-2) Stackable Switched-Capacitor DC/DC Converter IC for LED Drivers
with 90% Efficiency,” Proc. of the IEEE Custom Integrated Circuits
For a 1-track (or boost) converter, k=1 and n=1, the total Conference (CICC), pp. 1–4, Sept. 2013.
conduction loss is [16] M. Kasper, D. Bortis and J. W. Kolar, “Novel High Voltage Conversion
Ratio ‘Rainstick’ DC/DC Converters,” Proc. of the IEEE Energy Conver-
Pin 2 sion Congress and Exposition (ECCE), pp.789–796, 15-19 Sept. 2013.
Loss1−Track = ( ) RVmax . (B-3) [17] S. R. Sanders and M. Kline, “Switched-Capacitor Isolated Led Driver,”,
vin US Patent 14/293,107.
Fig. 31 plots the estimated worst-case conduction loss of [18] R. C. N. Pilawa-Podgurski and D. J. Perreault, “Merged Two-Stage
Power Converter With Soft Charging Switched-Capacitor Stage in 180
a few n-Track converters as a function of the normalized nm CMOS,” IEEE Journal of Solid-State Circuits, vol.47, no.7, pp. 1557–
input voltage range (vin /Vmax ), assuming the device voltage 1567, July 2012.
scaling rule described previously in (B-2). Figure 32 plots [19] R. C. N. Pilawa-Podgurski, D. M. Giuliano and D. J. Perreault, “Merged
the same information as a function of the input voltage range Two-Stage Power Converter architecture with Soft Charging Switched-
Capacitor Energy Transfer,” Proc. of the IEEE Power Electronics Spe-
Vmax /Vmin . The conduction loss scales quadratically with the cialists Conference (PESC) pp. 4008–4015, 15-19 June 2008.
input voltage range (because the conduction loss is a quadratic [20] M. Araghchini, J. Chen, V. Doan-Nguyen, D. V. Harburg, D. Jin, J. Kim,
function of the input current). For an n-Track converter, when M. S. Kim, S. Lim, B. Lu, D. Piedra, J. Qiu, J. Ranson, M. Sun, X. Yu,
H. Yun, M. G. Allen, J. A. del Alamo, G. DesGroseilliers, F. Herrault,
1 < VVmax
min
< n−1n
, the conduction loss is linearly reduced J. H. Lang, C. G. Levey, C. B. Murray, D. Otten, T. Palacios, D. J.
by a factor of 1/n. For wider input voltage range, e.g. if Perreault and C. R. Sullivan, “A Technology Overview of the PowerChip
Vmax n Development Program,” IEEE Trans. Power Electron., vol.28, no.9, pp.
Vmin > n−1 , the conduction loss gradually approach the 4182–4201, Sept. 2013.
conduction loss of the 1-Track converter. [21] S. Lim, D. M. Otten and D. J. Perreault, “Power Conversion Architecture
for Grid Interface at High Switching Frequency, Proc. of the IEEE Applied
Power Electron. Conference and Exposition (APEC), pp. 1838–1845,
R EFERENCES March 2014.
[1] J.G. Kassakian and T.M. Jahns, “Evolving and Emerging Applications of [22] S. Lim, J. Ranson, D. M. Otten and D. J. Perreault, “Two-Stage Power
Power Electronics in Systems,” IEEE Journal of Emerging and Selected Conversion Architecture Suitable for Wide Range Input Voltage,” IEEE
Topics in Power Electronics, vol.1, no.2, pp.47–58, June 2013. Trans. on Power Electron., Vol. 30, No. 2, pp. 805–816, Feb. 2015.
[2] M. Chen, “Merged Multi-Stage Power Conversion: A Hybrid Switched- [23] M. Chen, K.K. Afridi, D.J. Perreault, “A Multilevel Energy Buffer and
Capacitor/Magnetics Approach,” Ph.D. dissertation, Elect. Eng. and Voltage Modulator for Grid-Interfaced Microinverters,” IEEE Trans. on
Comp. Sci. Dept., Massachusetts Inst. of Technol., Cambridge, 2015. Power Electron., vol.30, no.3, pp.1203-1219, March 2015.
[3] T. A. Meynard and H. Foch, “Multi-Level Conversion: High Voltage [24] C. Schaef, K. Kesarwani and J. T. Stauth, “A Variable-Conversion-Ratio
Choppers and Voltage-Source Inverters,” Proc. of the IEEE Power Elec- 3-phase Resonant Switched Capacitor Converter with 85% Efficiency at
tron. Special. Conf. (PESC), pp. 397-403, vol. 1, 29 Jun-3 1992. 0.91 W/mm2 using 1.1nH PCB-trace Inductors,” IEEE International
[4] F. Hamma, T. A. Meynard, F. Tourkhani, and P. Viarouge, “Characteristics Solid- State Circuits Conference - (ISSCC), pp. 1–3, 22-26, Feb. 2015.
and Design of Multilevel Choppers,” Proc. of the IEEE Power Electron. [25] K. Kesarwani, R. Sangwan and J. T. Stauth, “Resonant Switched-
Special. Conf. (PESC), pp.1208-1214, vol.2, 18-22 Jun 1995. Capacitor Converters for Chip-Scale Power Delivery: Design and Im-
[5] T. A. Meynard, H. Foch, P. Thomas, J. Courault, R. Jakob, and M. plementation,” IEEE Trans. on Power Electron., early access.
Nahrstaedt, “Multicell Converters: Basic Concepts and Industry Applica- [26] Y. Lei, R. May and R. C. N. Pilawa-Podgurski, “Split-Phase Control:
tions,” IEEE Transactions on Industrial Electronics, vol.49, no.5, pp.955- Achieving Complete Soft-Charging Operation of a Dickson Switched-
964, Oct 2002. Capacitor Converter,” IEEE Trans. on Power Electron., vol.31, no.1, pp.
[6] J. S. Lai and F. Z. Peng, “Multilevel Converters-A New Breed of Power 770-782, Jan. 2016.
Converters,” IEEE Transactions on Industry Applications, vol.32, no.3, [27] M. Chen, K. K. Afridi, S. Chakraborty and D. J. Perreault, “A High-
pp.509-517, May/Jun 1996. Power-Density Wide-Input-Voltage-Range Dc-Dc Converter having a
[7] L. M. Tolbert, F. Z. Peng, and T.G. Habetler, “Multilevel Converters MultiTrack Architecture,” Proc. of the IEEE Energy Conversion Congress
for Large Electric Drives,” IEEE Transactions on Industry Applications, and Exposition Conference (ECCE), Montreal, Canada, September, 2015.
vol.35, no.1, pp.36-44, Jan/Feb 1999. [28] D. Meneses, O. Garcia, P. Alou, J. A. Oliver and J. A. Cobos, “Grid-
[8] S. R. Sanders, E. Alon, H. -P. Le, M. D. Seeman, M. John and V. W. connected Forward Micro-inverter with Primary-Parallel Secondary-
Ng, “The Road to Fully Integrated DC-DC Conversion via the Switched- Series Transformer,” IEEE Transactions on Power Electronics (early
Capacitor Approach,” IEEE Trans. Power Electron., vol.28, no.9, pp. access).
4146–4155, Sept. 2013. [29] B. A. Miwa, “Interleaved Conversion Techniques for High Density
[9] H. Kim, H. Chen, D. Maksimovic, and R. Erickson, “Design of a High Power Supplies,” Ph.D. dissertation, Elect. Eng. and Comp. Sci. Dept.,
Efficiency 30 kW Boost Composite Converter,” Proc. of the IEEE Energy Massachusetts Inst. of Technol., Cambridge, 1992.
Conversion Congress and Exposition (ECCE), pp. 4243-4250, 20-24 Sept. [30] D. J. Perreault, “Design and Evaluation of Cellular Power Converter
2015. Architectures,” Ph.D. dissertation, Elect. Eng. and Comp. Sci. Dept.,
[10] M. Seeman and S. Sanders, “Analysis and Optimization of Switched- Massachusetts Inst. of Technol., Cambridge, 1997.
Capacitor DC-DC Converters,” IEEE Transactions on Power Electronics, [31] C. Chang and M. A. Knights, “Interleaving Technique in Distributed
vol. 23, no. 2, March 2008. Power Conversion Systems,” IEEE Transactions on Circuits and Systems
[11] J. M. Henry and J. W. Kimball, “Practical Performance Analysis of I: Fundamental Theory and Applications, vol.42, no.5, pp. 245–251, May
Complex Switched-Capacitor Converters,” IEEE Transactions on Power 1995.
Electronics, vol.26, no.1, pp. 127–136, Jan. 2011. [32] D. J. Perreault and J. G. Kassakian, “Distributed Interleaving of Paral-
[12] J. Sun, M. Xu, Y. Ying and F. Lee, “High Power Density, High Efficiency leled Power Converters,” IEEE Transactions on Circuits and Systems I:
System Two-Stage Power Architecture for Laptop Computers,” Proc. of Fundamental Theory and Applications, vol.44, no.8, pp. 728–734, Aug
the IEEE Power Electron. Special. Conf. (PESC), pp. 1–7, Jun. 2006. 1997.

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[33] M. Chen, M. Araghchini, K. K. Afridi, J. H. Lang, C. R. Sullivan and Khurram K. Afridi (S’93−M’98) received the B.S.
D. J. Perreault, “A Systematic Approach to Modeling Impedances and degree in electrical engineering from the California
Current Distribution in Planar Magnetics,” IEEE Transactions on Power Institute of Technology (Caltech) in 1989 and the
Electronics, vol.31, no.1, pp. 560–580, Jan. 2016. S.M. and Ph.D. degrees in electrical engineering and
[34] W. Li and D. J. Perreault, “Switched-Capacitor Step-Down Rectifier computer science from the Massachusetts Institute of
for Low-Voltage Power Conversion,” Proc. of the IEEE Applied Power Technology (MIT) in 1992 and 1998, respectively.
Electron. Conference, pp. 1884–1891, March 2013. During summers and between degrees he worked
[35] M. F. Schlecht, B. A. Miwa, “Active Power Factor Correction for for JPL, Lutron, Philips, and Schlumberger. In 1997,
Switching Power Supplies,” IEEE Transactions on Power Electronics, he joined the founding team of Techlogix as Chief
vol.PE-2, no.4, pp. 273–281, Oct. 1987. Technology Officer and became Chief Operating
[36] M. T. Zhang, Y. Jiang, F. C. Lee and M. M. Jovanovic, “Single-Phase Officer in 2000. From 2004 to 2008 he also led the
Three-Level Boost Power Factor Correction Converter,” Proc. of the IEEE development of LUMS School of Science and Engineering (SSE) as Project
Applied Power Electron. Conference and Exposition (APEC), pp. 434– Director, and was appointed Associate Professor and the Werner-von-Siemens
439, vol. 1, 5-9 Mar 1995. Chair for Power Electronics in 2008. From 2009 to 2014 he was a Visiting
[37] B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad, A. Pandey and D. Associate Professor in the Department of Electrical Engineering and Computer
P. Kothari, “A Review of Single-phase Improved Power Quality AC-DC Science at MIT. Since January 2014 he is an Assistant Professor in the
converters,” IEEE Trans. on Industrial Electronics, vol.50, no.5, pp. 962– Department of Electrical, Computer and Energy Engineering at the University
981, Oct. 2003. of Colorado (CU) Boulder. His research interests are in power electronics
[38] B. Mahdavikhah and A. Prodic, “Low-Volume PFC Rectifier Based and energy systems incorporating power electronic controls. Dr. Afridi is
on Nonsymmetric Multilevel Boost Converter,” IEEE Trans. on Power a recipient of Caltech’s Carnation Merit Award, CU Boulder’s College of
Electron., vol.30, no.3, pp. 1356–1372, March 2015. Engineering and Applied Science Dean’s Professional Progress Award, the
[39] J. G. Kassakian, M. F. Schlecht and G. C. Verghese, “Section 6.5.3: BMW Scientific Award, and the NSF CAREER Award.
Minimum L and C for the Direct Converter,” in Principles of Power
Electronics, Addison-Wesley, 1991.
[40] V. Yousefzadeh, E. Alarcon, and D. Maksimovic, “Three-level Buck
Converter for Envelope Tracking Applications,” IEEE Transactions on
Power Electronics, vol. 21, pp. 549–552, March 2006.
[41] B. J. Baliga, “Section 1.6: Ideal Drift Region for Unipolar Power Sombuddha Chakraborty (S’02−M’16) received
Devices”, in Fundamentals of Power Semiconductor Devices, New York: the B.E. degree in Electrical Engineering from In-
Springer, 2008. dian Institute of Engineering Science and Tech-
[42] F. E. Terman, “Section 2: Circuit Elements,” in Radio Engineers’ nology, Shibpur in 2001, and the M.S, and Ph.D.
Handbook, First Edition, New York, NY: McGraw-Hill Book Company, degrees in Electrical Engineering from University of
1943. Minnesota, Minneapolis, in 2003, and 2005, respec-
[43] Bel Power Solutions, “UIS48T14050 Datasheets”, [online]. tively.
Available: http://belpowersolutions.com/power/documents/downloads/ From 2006 to 2007, he was Design Engineer at
uis48t14050-datasheet. General Electric Lighting Institute, Cleveland, OH.
From 2008 to 2013, he was System Design Engineer
and Manager at Volterra Semiconductors, Fremont,
CA. Since 2014, he is at Power Electronics Research Group, Kilby Labs,
Texas Instruments at Santa Clara, CA.
His primary research interest includes design of high density offline and
dc-dc power management system for computing, automotive and industrial
applications.

David J. Perreault (S’91−M’97−SM’06−F’13)

received the B.S. degree from Boston University,
Boston, MA, and the S.M. and Ph.D. degrees from
the Massachusetts Institute of Technology, Cam-
bridge, MA. In 1997 he joined the MIT Labora-
tory for Electromagnetic and Electronic Systems as
a Postdoctoral Associate, and became a Research
Scientist in the laboratory in 1999. In 2001, he joined
the MIT Department of Electrical Engineering and
Computer Science, where he is presently Profes-
sor and Associate Department Head. His research
interests include design, manufacturing, and control techniques for power
electronic systems and components, and in their use in a wide range of
applications. He also consults in industry, and is co-founder of Eta Devices,
a startup company focusing on high-efficiency RF power amplifiers. Dr.
Perreault received the Richard M. Bass Outstanding Young Power Electronics
Engineer Award, the R. David Middlebrook Achievement Award, the ONR
Young Investigator Award, and the SAE Ralph R. Teetor Educational Award,
Minjie Chen (S’10−M’15) received the B.S. degree and is co-author of seven IEEE prize papers.
from Tsinghua University in 2009, and the S.M.,
E.E., and Ph.D. degrees from MIT in 2012, 2014
and 2015, respectively. He is currently a postdoctoral
research associate in the MIT Research Laboratory
of Electronics. His research interests are in the
design of high performance power electronics for
emerging and important applications.
M. Chen received the national outstanding student
scholarship from Tsinghua University, the MIT E.E.
Landsman Fellowship, and an IEEE ECCE best
student demonstration award.

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