Voltage Oriented Control of Three Phase Boost PWM Converters

Voltage Oriented Control of Three‐Phase

Boost PWM Converters
Design, simulation and implementation of a 3‐phase boost battery
charger

Master of Science Thesis in Electric Power Engineering

Sylvain LECHAT SANJUAN

Department of Energy and Environment
Division of Electric Power Engineering
CHALMERS UNIVERSITY OF TECHNOLOGY
Göteborg, Sweden, 2010

Voltage Oriented Control of Three‐Phase
Boost PWM Converters
Design, simulation and implementation of a 3‐phase boost battery
charger

By


Supervisor
Saeid Haghbin, PhD Student

Examiner
Ola Carlson, Associate Professor

Göteborg, Sweden, 2010

VOLTAGE ORIENTED CONTROL OF THREE‐PHASE BOOST PWM CONVERTERS
DESIGN, SIMULATION AND IMPLEMENTATION OF A 3‐PHASE BOOST BATTERY CHARGER
SYLVAIN LECHAT SANJUAN

© SYLVAIN LECHAT SANJUAN, 2010

SE‐412 96 Göteborg
Sweden
Telephone : + 46 (0)31‐772 1000

Göteborg, 2010

ABSTRACT

Voltage Oriented Control of Three‐Phase Boost PWM Converters
Design, simulation and implementation of a 3‐phase boost battery charger

Chalmers University of Technology

In a plug‐in hybrid electric vehicle, the utility grid will charge the vehicle battery through the
battery charger. For a three‐phase grid supply voltage, three‐phase boost rectifiers are a commonly
used scheme for chargers. Bi‐directional power transfer capability and unit power factor operation
are interesting features that can be achieved by the method proposed in this thesis. Different
control strategies have been proposed to control the converter. The Voltage Oriented Control is one
of these methods based on high performance dq‐coordinate controllers.
The Voltage Oriented Control method for a three‐phase boost rectifier have been designed
and simulated. Moreover, an implementation of the system has been started. The system simulation
has been done using Matlab/Simulink software. Feedforward decoupled current controller has been
designed along with Pulse Width Modulation scheme to control the battery charging. The controller,
that is, a current controller and a DC‐link voltage controller, have been designed using a method
called Internal Model Control. The simulation results have been presented and the control system
performance evaluated in response to the load and dc‐bus voltage step changes.
dSpace system have been used for practical implementation. The system is directly running a
Simulink model as a controller. The Simulink files have been developed for this purpose. A brief
explanation of the system configuration has been provided for the experimental system.

Key words : battery charger, decoupled controller, dSpace, Internal Model Control (IMC), Pulse
Width Modulation (PWM), three‐phase boost PWM rectifier, Voltage Oriented Control (VOC).

iv

ACKNOWLEDGEMENTS

First of all, I would like to express my sincere gratitude to Saeid Haghbin, my supervisor, for
his total availability during the thesis, for his understanding, technical guidance and friendliness.

My gratitude also goes to Ola Carlson, for giving me the opportunity to do this Master’s Thesis work
in the Electric Power division of Chalmers University of Technology.

A very special thanks to Stefan Lundberg and Massimo Bongiorno, for all help, their availability,
technical guidance and nice discussions.

Thanks to all the employees and staff in the division who made my thesis work such a pleasant stay.
Furthermore, I would like to thank Magnus Ellsen for his availability and help for laboratory set‐up.

Finally, many thanks to my fellow Master’s Thesis students with Saman Babaei, Thinley Gyeltshen,
Francisco Montes Venero, Peng Hou, Sergio Garcia Collino and Johan Andersson. Thanks for their
support, guidance and nice discussions. They also made my stay in Sweden an unforgettable
experience.

Sylvain Lechat Sanjuan
Göteborg, Sweden
Wednesday, June 16, 2010

v

LIST OF SYMBOLS, SUPERSCRIPTS, SUBSCRIPTS AND ABBREVIATIONS

ABBREVIATIONS
DPC Direct Power Control
IC Initial Condition
IGBT Insulated Gate Bipolar Transistor
IM Induction Machine
IMC Internal Model Control
PWM Pulse Width Modulation
PLL Phase Locked Loop
PMSM Permanent Magnet Synchronous Machine
SVM Space Vector Modulation
VF‐DPC Virtual Flux Direct Power Control
VFOC Virtual Flux Oriented Control
VOC Voltage Oriented Control

SYMBOL
U Line voltage
E Line voltage
Grid phase‐to‐ground voltage amplitude
and dq‐coordinates of line or grid voltage (amplitude invariant transformation)
Vpcc Voltage at the point of common connection
Us Converter voltage
V Converter voltage
V* Converter voltage reference from current controller
Line‐to‐Line voltage
Line‐to‐Neutral voltage
Amplitude of Line‐to‐Neutral voltage
Amplitude of Line‐to‐Neutral voltage
, DC‐link voltage
Voltage across AC‐side capacitor
iL Line current
i Line current
iCONV Line current, current flowing into the converter
iDC DC‐link current
iLOAD Load current
Line resistance
Line inductance
DC‐link capacitor
Grid resistance
Grid inductance
Breaker SW1 resistance
AC capacitor
DC capacitor
Load resistance
_ Temporary load resistance
Voltage angle
Sampling frequency
Sampling time
vi

Switching frequency
Triangular wave frequency (PWM)
Triangular wave frequency (PWM)
Current controller bandwidth (rad/s)
Voltage controller bandwidth (rad/s)
Active damping conductance
Voltage controller integrator coefficient
Voltage controller proportional coefficient
Current controller integrator coefficient
Current controller proportional coefficient
PLL Integrator coefficient
PLL proportional coefficient
PLL bandwidth
Controller transfer function (PI)
Process transfer function
Open‐loop transfer function
Closed‐loop transfer function

Grid power
Load power

SUPERSCRIPT, ACCENTS
, , , Estimated values
Space vector
dq‐coordinate system
Reference value of

SUBSCRIPT, UNDERLINE
dq‐coordinate system
dq‐coordinate system, complex value

vii

TABLE OF CONTENTS

ABSTRACT IV
ACKNOWLEDGEMENTS V
LIST OF SYMBOLS, SUPERSCRIPTS, SUBSCRIPTS AND ABBREVIATIONS VI
1 INTRODUCTION AND SCOPE 1
2 THREE PHASE CONTROLLED RECTIFIERS 3
2.1 Introduction 3
2.2 Universal bridge topology 5
2.2.1 Steady state operation 5
2.2.2 Mathematical model 5
2.2.3 Limitations 9
2.3 Control strategies 11
2.3.1 Introduction 11
2.3.2 Direct Power Control and Virtual Flux Direct Power Control 12
2.3.3 Voltage and Virtual Flux Oriented Control 13
2.3.4 Comparison and discussion 14
2.4 Pulse Width Modulation 15
2.4.1 Sinusoidal PWM 15
2.4.2 Digital implementation 16
2.4.3 Dead time effect 16
3 VOLTAGE ORIENTED CONTROL – SIMULATION 18
3.1 Introduction – References chosen 18

3.2 System block diagram 19
3.3 PWM Simulation 20
3.3.1 Simulink implementation of PWM 20
3.4 Current controller 22
3.4.1 Internal Model Control 22
3.4.2 Synchronous PI control 22
3.4.3 Design of the synchronous PI controller 23
3.4.4 Active damping, voltage saturation, anti‐windup 25
3.4.5 Current controller simulation 27
3.5 DC‐link voltage controller 30
3.5.1 DC‐link model and linearization 30
3.5.2 Design of voltage controller 30
3.5.3 Voltage saturation, anti‐windup, active damping 31
3.5.4 Voltage controller simulation 33
3.5.5 Simulation with current controller 36
3.5.6 Controller improvements 39
3.6 Stability analysis 41
viii

3.6.1 Current controller 41

3.6.2 Voltage controller 41
3.6.3 Complete controller 42
3.6.4 Nyquist and Bode diagram 43
3.6.5 Conclusion 46
3.7 Phase Locked Loop (PLL) 48
3.7.1 Design 48
3.7.2 Simulations 48
3.7.3 Improvements and conclusion 52
3.8 Grid modeling 53
3.9 Grid connected converter simulation 55
3.9.1 Simulation steps, Simulink block diagram 55
3.9.2 Verification 56
3.9.3 Simulation results 58
4 VOLTAGE ORIENTED CONTROL – IMPLEMENTATION 63
4.1 Block diagram 63

4.2 Principle 63
4.3 Simulink model modification 64
4.4 Running an experiment 67
5 CONCLUSIONS AND FUTURE WORK 70
REFERENCES 71
APPENDICES 74
A. Three‐phase system – Coordinate transformations 74
A.1 Voltage and current definition 74
A.2 Equivalent two‐phase system, ‐transformation (Clarke) 74
A.3 Synchronous coordinate, dq‐transformation (Park) 75
A.4 Simulation 76
A.5 Impedance in synchronous coordinates 77
B. Voltage and current control, continuous simulation 79
B.1 Simulink current control tests – Block diagram 79
B.2 Continuous voltage controller, simulation with saturation, anti‐windup, active
damping 80
C. Digital simulation 81
D. Voltage and current control, discrete time simulation 82
E. Stability analysis cont. 83
E.1 Simulations 83
F. Grid connected converter simulation cont. 91
F.1 Data and simulations 91
F.2 Matlab Script (Vdc Step) 102
G. Implementation 104

ix
INTRODUCTION AND SCOPE

1 INTRODUCTION AND SCOPE
PHD PROJECT
The master thesis is part of a PHD project titled “Integrated charger for plug‐in Hybrid
Electric Vehicles”.
The PHD project is funded by the Swedish Hybrid Vehicle Centre (SHC1) and is doing by the PHD
student Saeid Haghbin under supervision of Associate Professor Ola Carlson. Moreover, Assistant
Professor Sonja Lundmark is the project co‐supervisor.

The scope of the PhD project is :
Investigating and evaluating existing plug‐in HEV’s in general and especially the charging
systems. This collection of available information also includes listing all as well as the most
interesting parameters of the charger, i.e. speed of charging, power rating, cost, volume and
weight, number of phases, voltage levels, ease of charging and availability of charging places,
limitations on power electronic components, power factor, harmonic distortion, monitoring
equipment, standards, and persons safety. The study should involve battery knowledge, so
that the charger could be fully adapted to the battery, giving a long battery life length.
Suggest and evaluate possible integrated chargers, meaning integration of the charger and
the available drive system used for propulsion of the vehicle.
Prototype building in cooperation with the whole group (including industry). One prototype
coordinator from industry administrates the task. The task also incorporates preparations for
lab testing.

MASTER THESIS SCOPE
The thesis is part on the sub project “On Board Integrated Charging”. The main goal is to
design, simulate and implement a 3‐phase boost battery charger with power factor correction.

Figure 1.1 : Rectifier schematic with AC machine

The Figure 1.1 represent our system. The first idea was to use an AC motor on the AC‐side. Some
data are given is Table 1.1.

1
SHC is composed with three different partners : three universities with Lund Institute of Technology (LTH),
Royal Institute of Technology (KTH) and Chalmers University of Technology (CTH), The Swedish Energy Agency
(Energimyndigheten) and automotive industry with AB Volvo, Volvo Car Corporation, Saab Automobile AB, GM
Powertrain Sweden AB, Scania CV AB, BAE Systems Hägglunds AB.

1

INTRODUCTION AND SCOPE

‐ 3‐phase
POWER SOURCE ‐ 50Hz
‐ PMSM 115V±20% phase voltage
POWER LEVEL ‐ 15kW
BATTERY VOLTAGE ‐ 320‐400VDC (nominal value 350VDC)
‐ Motor (KTH development)
‐ IGBT Rectifier
‐ Battery
MATERIAL ‐ dSpace system
‐ Hardware (in development)
‐ Piece of software to develop for implementation (probably C)
‐ Sensors (full access I/V/Speed)
Table 1.1 : Scope data

At the beginning of thesis, a first plan had been established.
1) Literature review (how the system work/find literature resources)
2) Topology selection (VFOC is preferred method regarding to this specific application)
3) System design (inductance value, switching frequency, control design)
4) Simulation with Matlab/Simulink
5) Addition of PMSM to the model and using the leakage inductance of the machine as energy
storage device (Re‐design/Re‐simulation)
6) Implementation
a. dSpace system
b. Software development
c. Hardware test (in development)
7) Testing and debugging / Report

Nevertheless, after a couple of weeks we decided to simplify the system to keep a grid connected
rectifier and try to implement it in the laboratory to test the controller.

The main goal of the thesis is to develop and test the control algorithm of the converter.

* *
*

We will start this thesis with an overview of three‐phase controlled rectifiers (chapter 2), with
steady state operation, modeling, limitations. Then, the overview will focus on control strategies, and
finally, a Pulse Width Modulation (PWM) will be describe.
Chapter 3 will be the main part of the report with Voltage Oriented Control design and simulation.
We will see the current and voltage controller, stability analysis, Phase Locked Loop (PLL), and finally
a simulation of grid connected converter.
The last part chapter 4 will give the main guidelines for implementation of the controller using
dSpace system.

2

THREE PHASE CONTROLLED RECTIFIERS
2 THREE PHASE CONTROLLED RECTIFIERS
2.1 Introduction
In the following part, we will see some topologies for 3‐phase rectifiers. But we can start to
explain why those topologies appeared. The high harmonic content and a low power factor cause
some problems in power distribution system. New standards have been introduced by governments
or organizations to limit the harmonic content of the current drawn from the power line by
rectifiers. Consequently, new topologies have been deployed for rectification applications [9] .

We can introduced five topologies (Figure 2.1).
The figure a) present a simple solution of Boost converter. The main drawback of this solution is
stress on the components and low frequency distortion of the input current.
The topologies b) and c) use PWM rectifier modules with a very low current rating (20‐25% level of
RMS current comparable with e) topology). Hence they have a low cost potential and provide only
the possibility of regenerative braking mode b) or active filtering c).
Figure d) presents a converter called a Vienna rectifier. The main advantage is low switch voltage,
but non‐typical switches are required.
Figure e) presents the most popular topology. This universal topology has the advantage of using a
low‐cost three‐phase module with a bidirectional energy flow capability, and it can also provide a
unity power factor (UPF). However, its disadvantages are a high per‐unit current rating, poor
immunity to shoot‐through faults, and high switching losses [9] .
Topologies are compared in a table (see Table 2.1). A diode rectifier is also included to the table for
comparison.

3

Figure 2.1 : Three‐phase rectifier topologies [9] [13]

REGULATION OF LOW HARMONIC NEAR SINUSOIDAL
FEATURE POWER FACTOR BIDIRECTIONAL
DC OUTPUT DISTORSION OF CURRENT REMARKS
TOPOLOGY CORRECTION POWER FLOW
VOLTAGE LINE CURRENT WAVEFORMS
Diode rec.
Rec. (a)
Rec. (b)
Rec. (c) UPF
Rec. (d) UPF
Rec. (e) UPF
Table 2.1 : Three‐phase rectifier topologies, performance comparison [9] [13]

4

2.2 Universal bridge topology
2.2.1 Steady state operation
Figure 2.2 : Rectifier schematics [9]

Figure 2.2 shows basic diagram of the three‐phase boost converter. uL is the line voltage and uS is the
bridge converter voltage controllable from de the dc‐side. We can draw a general phasor diagram
and diagrams for both rectification and regeneration operation at unity power factor (UPF).

a) General phasor diagram b) Rectification (at UPF) c) Regeneration (at UPF)

Figure 2.3 : Phasor diagrams [9]

The line current iL is controlled by the voltage drop across the inductance L interconnecting the two
voltage sources (line and converter).
When we control the phase angle ε and the amplitude of converter voltage uS , we control indirectly
the phase and amplitude of the line current. In this way, the average value and sign of the dc current
is subject to control that is proportional to the active power conducted through the converter. The
reactive power can be controlled independently with a shift of the fundamental harmonic current IL
with respect to voltage UL [9] .

Remark : Inductors connected between the line and the rectifier input bring a current source
character of the input circuit and provide the boost feature of the converter [9] .

2.2.2 Mathematical model
DESCRIPTION OF INPUT VOLTAGE AND CURRENT
The three‐phase line voltage and current are

5

2
(2.1)
3
4

3

2
(2.2)
3
4

3

and since there is no neutral connection, we obtain

0. (2.3)

A three‐phase system can be described with only two components α and β (real and
imaginary respectively). Furthermore, we call a space vector the quantity ([4] [12] )

2
. (2.4)
3

where K is a scaling constant (amplitude invariant 1, RMS‐invariant 1/√2 , power invariant
√ 3/2 – Refer to APPENDIX A for details).

RECTIFIER ABC‐MODEL [9]
(2.5)

1 upper switch ON
with the switching function defined by : Si with phase , , .
0 bottom switch ON

.
. (2.6)
.

1 2

3 3
2
(2.7)
3
2

3
( are 0, ±1/3 or ±2/3).

The rectifier in defined by four equations, one for each phase (voltage) and one for the currents (dc‐
link).
(2.8)

6

(2.9)

The combination of the previous equations can be represented as a block diagram.
iLOAD
Figure 2.4 : Rectifier model [9]

RECTIFIER ‐EQUATIONS
We define the amplitude invariant Clarke transformation (see APPENDIX A) with ([4] [12] )

(2.10)
0
√ √
1 0
1 √3
2 2 (2.11)
1 √3
2 2

Then, applying this transformation we can find the voltage equations in αβ‐coordinates

(2.12)
3
. (2.13)
2

7

RECTIFIER ‐EQUATIONS
Now, we need to apply the Park transformation (see APPENDIX A and [4] [12] ) which is

(2.14)

where is a space vector ( ). We get

(2.15)
(2.16)

And finally, with separation of Real and Imaginary part we obtain

(2.17)
(2.18)
3
(2.19)
2

INSTANTANEOUS POWER [4]
From the well known relation for single phase rms‐value‐scaled phasors and
(“*” indicates complex conjugate), we know that instantaneous power for three‐phase system will
be proportional to
(2.20)

Note that the formula is independent of the coordinate system.

From the space vector definition we get (the time argument “(t)” is removed for simplicity)

2

3
2 1

3 √3

And finally, the Real part gives us the active power

3 3
. (2.21)
2 2

And with Imaginary part we obtain the reactive power

3 3

2 2 (2.22)
1
.
√3

8

For ideal, positive sequence space vectors (voltage is reference)

and

where and are amplitude, the active power is given by

3 3 3
3 (2.23)
2 2 2

Where and are rms‐values. This previous relation will be use in the DC‐link voltage controller
design.

2.2.3 Limitations
MINIMUM DC‐LINK VOLTAGE
For proper operation of the rectifier, a minimum dc‐link voltage is needed to obtain
undistorted current waveforms. To have a full control of the rectifier, its six diodes must be polarized
negatively at all value of ac‐voltage supply. To keep the diodes blocked, we need to ensure a dc‐link
voltage higher than the peak dc‐voltage generated by the diodes alone.
Theoretically for diode rectifier, the maximum dc output voltage is the peak value of line‐to‐line RMS
voltage [9] .

√2 √2. √3. (2.24)

VDC‐LINK
√ 15‐20%
VDIODE RECTIFIER
Figure 2.5 : DC‐link voltage condition

It will be better to select a DC‐link voltage about 15‐20% more than √2 .

IMPORTANT : The previous voltage correspond to the converter voltage (Us). There is no
line impedance taking in account here.
Nevertheless, if there is no line impedance (R = 0Ω , L=0H) we can continue to write the equation
(2.24) according to the amplitude of supply voltage Em :
√2. √3. √3 . (2.25)

ATTENTION : This is a true definition but doesn’t apply in all situation [9] . The DC‐link voltage
depends on the PWM method. In our case, we will use a sinusoidal PWM. In this case the maximum
reference voltage is Vdc/2 (Figure 2.6 [23] ).

9

Figure 2.6 : Maximum sinusoidal reference voltage (converter voltage Us) for sinusoidal PWM [23]

Finally, our minimum DC‐link voltage will be
(2.26)
2
√2
√3 2

2√2
2 1.663 (2.27)
√3

MINIMUM DC‐LINK VOLTAGE AND INDUCTANCE
The book [9] (chapter11 p434) defines a minimum DC‐link voltage taking in account the line
inductance value. The demonstration seems to be valid in our case for amplitude invariant (they
assume a maximum converter voltage equal to (i.e. radius of switching hexagon). It will be
for power invariant). They define a DC‐link voltage as
3 . (2.28)

We can observe that R is neglected and if L = 0 (if there is no inductance voltage), we find again the
equation (2.25) where √3 .

From this equation we can get the maximum inductance value as

3 (2.29)
.

A low inductance will give a high current ripple and will make the design more dependent on the line
impedance (refer to “3.8 Grid modeling” and “3.9.3 Simulation results”). According to [9] , a high
value of inductance will give a low current ripple, but simultaneously reduce the operation range of
the rectifier. The voltage drop across the inductance controls the current. This voltage drop is
controlled by the voltage of the rectifier but its maximal value is limited by the dc‐link voltage.
Consequently, a high current (high power) through the inductance requires either a high dc‐link
voltage or a low inductance (low impedance).

10

2.3 Control strategies
2.3.1 Introduction
The control of PWM converter can be considered as a dual problem with vector control of an
induction motor IM (see figure and table below).

Control of PWM rectifier IM control
DPC DTC
Direct Power Control Direct Torque Control
VOC FOC
Voltage Oriented Control Field Oriented Control
Figure 2.7 : PWM rectifier and IM control duality

Control of PWM rectifier IM control
Speed control loop of vector drive dc‐link voltage
Reference angle between stator current and rotor flux Reference angle of line voltage
Table 2.2 : PWM rectifier and IM control duality [9]

We can classify the PWM rectifier method in two categories : voltage based and virtual flux
based control (See following Figure 2.8).
Figure 2.8 : Control strategies [9]

All these control strategies can achieve the same main goals, such as high power factor and near
sinusoidal input current waveforms.
The Voltage Oriented Control (VOC) guarantees high dynamic and static performance via an internal
current control loop. But the quality depends mainly on the current control strategy.
The Direct Power Control (DPC) is based on the instantaneous active and reactive power control
loop. There are no internal current control loop and no PWM modulator block. The switching state
are determined with a switching table based on the instantaneous errors between the commanded
and estimated values of active and reactive power.
The Virtual Flux Based Control (VF‐) correspond to a direct analogy of IM control.

11

2.3.2 Direct Power Control and Virtual Flux Direct Power Control
The DPC method is similar to Direct Torque Control (DTC) for induction motor. Instead of
torque and stator flux the instantaneous active and reactive powers are controlled.
The following figure shows the scheme of the DPC method.
Figure 2.9 : Block scheme (DPC, VF‐DPC)[9]

The power estimation of DPC is based on the line voltage. An important disadvantages of the
method id the need of current differentiation to estimate this power. Other relevant points can be
found ([9] ) :
Need high sample frequency because the estimated value are changing all the time.
Need high inductance value because the switching frequency is not constant.
A non‐constant switching frequency means trouble to design an input filter.
Calculation of power and voltage should be avoid during switching (errors).

The virtual flux method is an improvement of Voltage Oriented Control (VOC). The virtual flux is an
integration of line voltage uL.
For the VF‐DPC, we can summaries the following characteristics.
No line voltage sensors required. Furthermore, a voltage sensor‐less line power estimation is
much less noisy due to natural low‐pass behavior of the integrator.
Simple and noise robust power estimation algorithm, easy to implement in a DSP.
Lower sampling frequency (as conventional DPC).
Sinusoidal line currents (low THD).
No separate PWM voltage modulation block.
No current regulation loops.
Coordinate transformation and PI controllers not required.
High dynamic, decoupled active and reactive power control.
Power and voltage estimation gives the possibility to obtain instantaneous variables with all
harmonic components, which has an influence for improvement of total power factor and
efficiency.
Easier calculations for p and q than voltage based method, no differentiation of line current.

The typical disadvantages of VF‐DPC are :
Variable switching frequency.

12

Solution requires a fast microprocessor and A/D converters.

2.3.3 Voltage and Virtual Flux Oriented Control
Figure 2.10 : VOC block scheme [9]

The Voltage Oriented Control (VOC) and Virtual Flux Oriented Control (VFOC) are close to Field
Oriented Control for induction motor. The method is based on the transformation between
stationary coordinates and synchronous rotating coordinates dq. This strategy guarantees :
Fast transient response
High static performance via internal current control loop.
Consequently, the performance depends on the quality of the current control loop.

We can find several strategies that can be applied for current control. A widely used scheme for high
performance current control is the dq synchronous controller, where the regulated current are DC
quantities. This eliminates steady‐state errors.

VOC and VFOC provide some advantages compared to DPC.
Low sampling frequency for good performance (cheaper A/D converters and
microcontroller)
Fixed switching frequency (easier design of input filter)

Furthermore, VFOC provides improved rectifier control under non‐ideal line voltage condition
(because ac voltage sensorless operation is much less noisy thanks to the natural low‐pass behavior
of the integrator used in the flux estimator).

Both methods also have some disadvantages :
Coupling occurs between active and reactive components and some decoupling solution is
required.
Coordinate transformation and PI controllers are required.

13

2.3.4 Comparison and discussion
The following table summarizes the main characteristics of the different control strategies.

TECHNIQUE ADVANTAGES DISADVANTAGES
Fixed switching Freq. (easier design input filter) Coordinate transformation and decoupling between

Advanced PWM strategies can be used active and reactive components is required
VOC
Cheap A/D converters Complex algorithm
Input power factor lower than for DPC
No separate PWM block High inductance and sample frequency needed
No current regulation loop Power and voltage estimation should be avoid at the
No coordinate transformation moment of switching
Good dynamics Variable switching frequency
DPC Simple algorithm Fast microprocessor and A/D converters required
Decoupled active and reactive power control
Instantaneous variables with all harmonics
components estimated (improve power factor
and efficiency)
Fixed switching Freq. (easier design input filter) Coordinate transformation and decoupling between
Advanced PWM strategies can be used active and reactive components is required
VFOC
Cheap A/D converters Complex algorithm
Input power factor lower than for VF‐DPC
Simple and noise resistant power estimation Variable switching frequency
algorithm, easy to implement in a DSP Fast microprocessor and A/D converters required
Lower sampling frequency than for DPC
Low THD of line currents with distorted or
unbalanced supply
VF‐DPC No separate PWM block
No current regulation loop
No coordinate transformation
Good dynamics
Simple algorithm
Decoupled active and reactive power control
Table 2.3 : Control strategies comparison [9]

VOC vs. VFOC
One of the only advantages of VFOC against VOC is that VFOC provides improved rectifier control
under non‐ideal line voltage condition (because ac voltage sensorless operation is much less noisy
thanks to the natural low‐pass behavior of the integrator used in the flux estimator).

Switching Frequency
A FIXED switching frequency is required in our project mainly because it means : easier design (input
filter for eg.) and the sample frequency can be lower. Only VOC or VFOC can provide this feature.

Power factor
DPC has better power factor than VOC but has variable switching frequency. DPC also means
complicated calculations for p and q (need differentiation of line current, risk of instability).
A good power factor can be achieved with VF‐DPC and the method has lots of advantages but as we
want a fixed switching frequency, VOC or VFOC should be chosen.
If the switching frequency can be variable, the VF‐DPC strategy is obviously the best solution (but the
cost can become a problem. The method need fast microprocessors and A/D converters).

14

2.4 Pulse Width Modulation
The Pulse Width Modulation used in our system, a sinusoidal PWM will be used.

2.4.1 Sinusoidal PWM
Sinusoidal modulation is
based on a triangular carrier signal.
The idea is to compare three
sinusoidal reference voltages Ua*,
Ub* and Uc* to this triangular wave.
By comparison, the logical signals Sa,
Sb and Sc, which define switching
instants of power transistor, are

generated. Operation with constant
carrier signal concentrate voltage
harmonics around switching
Figure 2.11 : Sinusoidal PWM
frequency and multiple of switching
frequency.

Vdc/2
‐Vdc/2
Figure 2.12 : Sinusoidal PWM basic waveforms

Â Maximum sinusoidal reference voltage
Using a sinusoidal PWM, the maximum reference value is Vdc/2.
Figure 2.13 : Maximum sinusoidal reference voltage (sinusoidal PWM) [23]

Â Maximum slope
The slope of the triangular wave should be higher than the slope of the reference voltage. We can
write

15


(2.30)

2.4.2 Digital implementation
Â Synchronous sampling [4]
In a digital current control system, the current is sample with interval Ts. To avoid
electromagnetic interference (EMI) due to ON/OFF switchings of the valves, it is useful to
synchronize the sampling with converter switching. Current sampling are taken in between
switchings. This coincide with the positive and negative peak values of the triangular waveform.
Using synchronous sampling, approximately the mean value of the current is obtained. Thus,
not only EMI is avoided, but also the current ripple is reduced. This method can be effective enough
to avoid low‐pass filtering before sampling.

We will select the sample frequency as :

(2.31)
( is the switching frequency, )

Sampling time
Figure 2.14 : Asymmetric PWM – Synchronous sampling illustration [23]

Two samples can be acquired over each switching period. According to [4] a fast sampling enables
higher bandwidth of the current controller, then it’s possible to reduce the sampling rate for
example to the switching rate : (or less).

2.4.3 Dead time effect
When we speak about implementation of converter, we need to inject deadtime (delay) in
PWM signals to avoid short circuit in DC‐link (i.e. both transistor of one leg are conducting). The
system becomes safer but, the performance are affected.
This is temporary a loss of control. For example in an inverter, the output voltage waveform deviates
from that for which it is originally intended. Since this is repeated over and over for every switching
operation, its detrimental effect may become significant in PWM inverters that operate in high
switching frequency. This is known as the deadtime effect. During the delay time, both transistors of
the leg cease to conduct. Another consequence of the deadtime effect is the appearance of
undesirable harmonics ([31] [32] ).
We can find several strategies for deadtime injection. An example is given below.

16

Figure 2.15 : One leg with transistors B1 and B2 – On/Off states, deadtime Td [32]

17

VOLTAGE ORIENTED CONTROL – SIMULATION
3 VOLTAGE ORIENTED CONTROL – SIMULATION
3.1 Introduction – References chosen
As we explain in the previous section, Voltage Oriented Control (VOC) or Virtual Flux
Oriented Control (VFOC) should be chosen. We decided to start with a VOC.
Before going further in the design and simulation of the controller, we need to precise some
important references chosen in this report.

3‐PHASE SYSTEM DEFINITION

2

3
4

3

COORDINATE TRANSFORMATION
1 0
√
and (2.10)(2.11)
0 √
√ √

and . (3.1) (3.2)

You can refer to APPENDIX A for details. We only use AMPLITUDE INVARIANT in this thesis.
Indeed, after transformation from ABC‐to‐dq coordinates, the d‐components is equal to , and the
q‐component equal to zero.

POWER, CURRENT DIRECTION
We chose a reference as shown in the following schematic, the current is flowing from the
grid to the rectifier.
Figure 3.1 Reference for I, P, Q

18

3.2 System block diagram
The voltage oriented control scheme is shown Figure 3.2.
Figure 3.2 : System block diagram

First of all, the line voltage Uabc need to feed the PLL (Phase Locked Loop, see “3.7 Phase
Locked Loop (PLL)”) and the voltage angle calculated is used for three‐phase to dq‐coordinate
transformation of line current and voltage.
Secondly, the dq‐coordinate values and the DC‐link voltage value are used in a decoupled controller
which will be described in the section “3.4 Current controller” and “3.5 DC‐link voltage controller”.
Finally, the reference voltages created by the controller are sent to the PWM block (Pulse Width
Modulation) to create the switching patterns Sabc (S = 1 means upper switch ON, lower switch OFF ;
S=0 means upper switch OFF, lower switch ON).

Remark : The reference voltage from the controller correspond to the converter voltage Us (see
design of the current controller in section “3.4 Current controller”).

The system will be simulated in Matlab/Simulink. According to the previous figure, we will have
four main parts in the model : the PLL, a decoupled controller composed by a current and voltage
controller, a PWM block, and a rectifier model (with grid impedance R and L included).

19

3.3 PWM Simulation
A description of the sinusoidal PWM implemented here is available in section “2.4 Pulse
Width Modulation”.

3.3.1 Simulink implementation of PWM
Â PWM block using switch
The amplitude of triangular wave should be Vdc/2. But Vdc is not constant in our case. We
should first normalized the reference value by Vdc/2 and compare this value with a triangular wave
with an amplitude of 1. The following figure show the Simulink block diagram.

Figure 3.3 : Simulink PWM block

Â PWM block without switch
We can also use a PWM block without switching to create the switching pattern. The
reference voltage is normalized by Vdc/2 to obtain a signal within a range [‐1 ; +1], then divide by 2
and translate to get signal in the range [0 ; +1] like the switching function Sabc. This simple model
can be useful in Simulink to reduce the simulation time if needed. In a complete simulation with
controller, the behavior of the system is similar using Figure 3.3 or Figure 3.4.

Figure 3.4 : Simulink PWM block without triangular wave

20

Â Synchronization verification
We have to check which carrier wave we should have (at t=0, triangle amplitude is 1 or 0?).
We need to be sure that we sample every triangular wave peak (we need to check if at t=0, Matlab
take a sample or not).
We can verify it by sampling the triangular wave, using a “sample and hold” block. The signals before
and after sampling are plotted below. As we can see, we sample on each triangle peak (blue point).

2
/2
Figure 3.5 : Synchronization verification

21

3.4 Current controller
This section is mainly based on the reference [4] and [14] . We are giving a summary for
controller design based on Internal Model Control (IMC) with synchronous PI control (decoupled
controller).
To make the following more understandable, a first schematic for decoupled controller is given
Figure 3.6 with the current controller and the dc‐link voltage controller (describe in section “3.5 DC‐
link voltage controller”).

Figure 3.6 : Decoupled controller (current and dc‐link voltage controller)

3.4.1 Internal Model Control
Internal Model Control (IMC) is a method for controller design, for which the resulting
controller becomes directly parameterized in terms of the plant model parameters and the desired
closed‐loop bandwidth.
For example, the controller transfer function will be

(3.3)

that is, a low pass filter with bandwidth α, is an estimation of the plant (process), and n the order
or G.

A brief tutorial is available in [14] , Chapter 6, page 83. This method is used for the following
controller design.

3.4.2 Synchronous PI control
PI controllers are inherently incapable of giving zero steady state control error for a
sinusoidal reference. The integral action removes the error only if the reference value is constant in
steady state.
Using Clarke and Park transformations, the current measurements are transformed to DC‐
quantities, then, a simple PI controller can give good results (but not always optimal performances).

Main qualities for dq‐frame current controller are then :
fast dynamic response,

22

good accuracy current tracking,
less sensitive to parameter variations.
(Sources :[4] [9] ).

3.4.3 Design of the synchronous PI controller
Figure 3.7 : Synchronous coordinates schematic (see APPENDIX A‐A.5)

Â Synchronous coordinates equation (notation, )
(3.4)

And the system transfer function is
1
. (3.5)

Figure 3.8 : Current control with inner decoupling loop

Â Cross coupling cancellation
The first step in the controller design is to cancel the cross coupling initiated by the term
(since multiplication by maps the axis on axis and vice versa). This easily possible if we
have an accurate estimation of which is .
According to [9] , a PI current controller has no satisfactory tracing performance for the coupled
system described by equations (2.17)(2.18). For high performance and accuracy current tracking we
need to cancel this cross‐coupling. We select as

(3.6)

with the estimated value of . Then, if and we get

23


1
(3.7)

with the decoupled system transfer function from to .

Â Controller transfer function
As the complex transfer function is a first order (representing two non‐interacting first order
system in the and directions), a PI controller is enough :

(3.8)

Based on IMC method of [14] , we can write

(3.9)

with (rad/s) the current controller bandwidth where the pole of is placed, and the
estimation of . Finally, we obtain the PI coefficients :
and . (3.10) (3.11)

For this inner current control loop, the bandwidth should be selected smaller than a decade
below the sampling frequency (Fs [Hz]) [14] ).

2 (3.12)
10

Â Decoupled current control design
In order to establish the decoupled current control diagram, we have to continue with
equation (3.6). We define , complex integrator state variable as :
(3.13)

Then, we can write the real and imaginary part to get our reference voltage and draw our current
controller block diagram :

24

(3.14)
(3.15)
Reference voltages
Figure 3.9 : Current controller block diagram

Comments : In our system, the line current is split into a q‐component and a d‐component .
determines the active power flow whereas the reactive power. The unit power factor (UPF)
condition is met when the line current vector is aligned with line voltage . In this case, we have
to set to zero in our controller ( 0).
Figure 3.10 : Vector diagram of VOC – Line current and voltage [9]

Furthermore, we can write down the equation for power and see that the reactive power is set to
zero. From the power equations established in section “2.2.2 Mathematical model” we can write

3 3 3
(3.16)
2 2 2
3 3 3
(3.17)
2 2 2

Now if we set the reference to zero and we know that the line voltage vector is aligned with the d‐
axis, so 0 . Finally, we get
3
(3.18)
2
0

3.4.4 Active damping, voltage saturation, anti‐windup
ACTIVE DAMPING
As it’s fully explained in [4] (section 1.4–p24), the current control error could be decrease
be increasing R. Therefore, we can add a inner feedback loop which add Ra (just using signal, there is
no energy transfer or more losses). This method improve disturbance rejection capability because

25

the dynamics are speeded up from L/R to L/(R+Ra). Active damping is also used when R and L value
are not estimated precisely.
This active damping is not implemented in this thesis.

REFERENCE VOLTAGE SATURATION
We have treated the current control loop as an ideal and linear system. In practice, this is
not correct because the reference voltage is limited to an upper and lower value. For large step of
the d‐current, the controller might demand a large voltage vector (outside the switching hexagon
that defines the switching possibilities). This exceeds the realizable voltage modulus of a PWM
converter ([4] [14] ).
The saturation is applied on the modulus of the complex value of the reference voltage
, that is, .
The saturation value depends on the DC‐link voltage. The maximum value of reference voltage is
Vmax = Vdc/2.
The simplest method to create the saturation [Vdc/2 ; ‐Vdc/2] in Simulink is to normalized the
modulus of reference voltage by Vdc/2 before the saturation block. Then, the saturation block is the
set to [1 ; ‐1] (it means a saturation between Vdc/2 and –Vdc/2). Finally, we multiply back the output
of the saturation block by Vdc/2.
Figure 3.11 : Reference voltage saturation – Simulink implementation

INTEGRATOR ANTI‐WINDUP
Principle
As we said in the previous section, for large step of the d‐current, the controller might
demand a too large voltage vector (outside the switching hexagon). This exceeds the realizable
voltage modulus of a PWM converter ([14] ).
We call the reference voltage. The PI controller is :

Once become limited ( ), the integrator part of the PI controller can introduce a phenomenon
called integrator windup. An integrator windup generally manifest itself by an overshoot (to the step
response). In order to avoid windup, the integrator part should not be updated with too large error
. We should feed the integrator with another error , so that .

26

Then, writing the difference we can obtain
.
The following controller results :

(source : [4] [14] )

In our case…
For the decoupled controller, the following equation have been found :

Ê .

Now we call the value of after saturation, we can write :

Ê

By writing the difference , we can find :
(3.19)
The PI current controller will be created as follow.
Figure 3.12 : PI controller with anti‐windup

3.4.5 Current controller simulation
BLOCK DIAGRAM
The simulation have been done following the following equations (equation (2.8) of section
“2.2.2 Mathematical model”) :

For each phase we know that the current is equal to

Also, we can draw the following diagram block (Figure 3.13).
Id* will be chosen ;

27

Ua Ub Uc are line voltage ;
Ed Eq are the dq‐transformation of Ua Ub Uc.

Figure 3.13 : Block diagram for current control tests

Remark : The tests can also be simulated in dq but we’ve decided to stay in ABC‐frame to model the
rectifier and the grid impedance to be as close as possible to the real system.

SIMULATION
The system have been simulated in continuous and discrete (only the continuous simulation
is shown here). No saturation or anti‐windup are present in this simulation. They will be added later.

Parameters Value
R (Ω) 0.1
L (H) 5e‐3
ω (rad/s) 2π50
Em (V), ph‐to‐gnd amplitude (=Ed) 115√2
Id* (A) 3
Id*step (A) at 0.025s 3
Iq* (A) 0
Fsw (kHz), switching frequency 20
/ (rad/s) 1.26e4
PI controller, Kpi 62.8
PI controller, Kii 1.26e3
Table 3.1 : Current controller simulation parameters
The bandwidth of the current controller have been selected at : 2 (we chose to
take a decade smaller than the switching frequency).
is selected equal to .
The Simulink block diagram is available in APPENDIX B‐B.1, Figure 0.7. We also advice to read
the simulation of coordinate transformation in APPENDIX A‐A.4 before.

28

Figure 3.14 : Current control simulation

Remark : The value of iq is zero when a zoom is done (even if a q‐current is visible in the previous
figure).

29

3.5 DC‐link voltage controller
3.5.1 DC‐link model and linearization
DC‐LINK MODEL
The DC‐link voltage is modeled as a pure capacitor. This capacitor is an energy storage where
the stored electrical energy in Joule is
1
. . (3.20)
2

The time derivative of this stored energy should be equal to the sum of instantaneous grid power
and load power [14] .

1
(3.21)
2

As we can see, the previous equation is not linear with Figure 3.15 : Energy transfer
respect to Vdc.

LINEARIZATION
The design of the voltage controller is facilitated thanks a feedback linearization. The
feedback linearization transforms the nonlinear dc‐voltage dynamics to a equivalent linear system,
on which traditional linear controller design can be applied.

We now choose a new state variable .
(3.22)
Then, equation (3.21) becomes
1
. (3.23)
2

which is linear with respect to . The physical interpretation is that the energy is chosen to
represent the dc‐link voltage dynamics instead of the voltage itself. Other type of linearization can
be found [14] .

3.5.2 Design of voltage controller
Â System transfer function
Following [14] and the Internal Model Control method, we can write

1

2
3
(3.18)
2
(3.24)

where is the d‐current, and the grid voltage . The coefficient comes from the amplitude
invariant transformation (see section “2.2.2 Mathematical model” about power calculation).

1 3
(3.25)
2 2

30

1 3

2 2
3 2
3 2

Then, the system transfer function is
3
(3.26)
Figure 3.16 : Voltage control loop

(3.27)
3
where is the estimation of and (rad/s) is the bandwidth of the voltage controller. Then,
give us a proportional coefficient :

(3.28)
3 3

with (Em is the amplitude of the three‐phase input voltage in the model section
“2.2.2 Mathematical model”)

We will choose at least a decade smaller than the current control bandwidth.

(3.29)
10

As we can see there is no integrator part in the controller. In our controller, we will add a small
integrator part with gain (for example 0.01).

3.5.3 Voltage saturation, anti‐windup, active damping
SATURATION, ANTI‐WINDUP
Exactly as the current controller, we have to add a saturation (on current id*) and an anti‐
windup is highly recommended (useful is the saturation limit is reached).

In this case we can write :

31

with . If we do the same calculation than the current controller case, we can find :

(3.30)

Then, the PI voltage controller scheme will be as below.

Figure 3.17 : PI controller with anti‐windup

ACTIVE DAMPING
Previously, we found a system transfer function (equation (3.26)) as

3

which has a pole at the origin. [14] advice to add an active damping in this case, to place the pole at
, with the bandwidth of the voltage controller.

Â System transfer function
Based on [14] , we can find the following equations and block diagram (Figure 3.18). We can
start again with equation (3.25):
1 3
(3.25)
2 2

We chose to define with
(3.31)

where is the active conductance that provides active damping. Then, by substituting equation
(3.31) into (3.25), the system model becomes

1 3 3
(3.32)
2 2 2

The system transfer function becomes
3
(3.33)
3

As we can see, we still have a first order system but the pole can be chosen with . Placing the pole
at we can find as
3 0 3 0
(3.34)
3

32

Following the previous IMC method, we obtain
(3.35)
3

3 3 3
(3.28) (3.36)

with .

Figure 3.18 : Voltage control loop with active damping

3.5.4 Voltage controller simulation
The system represented in Figure 3.19 is first simulated without saturation, then with
saturation, and finally, an anti‐windup is added. The simulation parameters and Simulink scheme are
presented below.

Parameters Value
C (μF) 2200
ω (rad/s) 2π50
/ (rad/s) 1.26e3
PI controller, Kpv 0.0057
PI controller, Kiv 0.01
Vdc reference (V) 400
Rload (Ω) 500
Table 3.2 : Voltage controller simulation

33

Figure 3.19 : Voltage controller – Simulink block scheme

Figure 3.20 : Voltage control – Without saturation

34

Figure 3.21 : Voltage control – With saturation15A

Figure 3.22 : Voltage control – With saturation15A and anti‐windup

Â Without saturation (Figure 3.20)
We can see a fast response, a small error close to zero (0.0001V at 3second). But, we observe a very
high current about 800A. We need to add the saturation here.

Â With saturation (Figure 3.21)
The error has been increased lightly (Error 0.06V with Rload = 500Ω, Error 0.1V with Rload = 50Ω).
We observe that the error depends on the saturation upper and lower value and depends also on
the load.
As the current is now limited the response is much slower. Finally, we also observe the so called
integrator windup due to the saturation.

35


Â With saturation and anti‐windup (Figure 3.22)
We now include the back calculation anti‐windup and as we can see, the overshoot disappeared. The
error is also reduce.

Â With saturation, anti‐windup and active damping (APPENDIX B‐B.2, Figure 0.8, Table 0.1)
In this simulation, the active damping doesn’t influence the system.

3.5.5 Simulation with current controller
The whole system can now be simulated. The rectifier is modeled according to the following
Simulink scheme (Figure 3.23 and Figure 3.24) and data (Table 3.3)

PARAMETERS VALUE
R (Ω) 0.1
L (H) 5e‐3
C (μF) 2200
ω (rad/s) 2π50
Rload (Ω) 500
Vdc reference (V) 400
/ (rad/s) 1.26e4
/ (rad/s) 1.26e3
V controller, Kpv 0.0057
V controller, Kiv 0.01
I controller, Kpi 62.8
I controller, Kii 1.26e3
I saturation (A) ±15
Vdc step at 0.03 (V) 50
Table 3.3 : Current and voltage controller simulation parameters

36

Figure 3.23 : Simulink block scheme – Grid impedance and dc‐link model

In the previous figure, the signals uabc_ref come from the controller (after dq‐to‐abc
transformation).

Figure 3.24 : Simulink block scheme – Controller

37

Figure 3.25 : Controller simulation results

In the Figure 3.25, we observe a very high current when the system start (id reaches 70A),
and we can see also a small overshoot on Vdc. This is due to the capacitor charging.
Now we apply a small step on Vdc reference (50V), and we can see that the d‐current reaches the
saturation limit (15A) when Vdc is increasing towards the reference value (450V). Finally, when Vdc
reaches the reference value (without overshoot), the current is stabilize around 1.3A (steady state
value).

DISCRETE SIMULATION
All the previous design and simulation have also been implemented in discrete time since
the controller will be discrete in reality. You can find a discrete simulation of the controller (same
scheme as Figure 3.24) in APPENDIX D.

38

3.5.6 Controller improvements
FILTERS
Figure 3.26 : Decoupled controller with filter

Êdq represent the line voltage (grid, or ) and Vdq the converter voltage. We received a
piece of advice regarding the feed‐forward term Êdq in the controller Figure 3.26. This feed‐forward
could turn the system unstable if some high frequency oscillations appear on Êdq.
To remove any high frequency oscillations, we decided to add a filter for each feed‐forward. We
chose a first order discrete filter with a bandwidth a decade lower than the current control
bandwidth :
(3.37)
10

If the grid is stiff enough, the bandwidth of the filter can be equal to the current controller
bandwidth.

INTEGRATORS
We can see in the previous scheme that two integrator are in cascade, an integrator in the
voltage controller and one in the current controller. The current controller integrator can probably
be removed (then, the anti‐windup also).

LOAD COMPENSATION
In the papers [11] , a load compensation has been proposed to minimized the influence of
rapid changes of the converter load. The feed‐forward information (see schematic on Figure 3.27)
about the actual converter load has also contributed to improve the transient response of the DC‐
link voltage. This compensation is not implemented in this report.

39

Figure 3.27 : Improvement proposed in [11]

40

3.6 Stability analysis
We decided to do a small stability analysis with the current controller only, voltage
controller, then both voltage and current controller together. Furthermore, the analysis is done for
three different voltage controller. First, only a proportional controller is taking in account ( ). In a
second time, the integration part is added ( 0.01). And finally, the active damping coefficient
is added.

3.6.1 Current controller
If the cross coupling cancellation is ideal, that is, , we saw in section “3.4.3 Design of
the synchronous PI controller” (and see Figure 3.8) that the system transfer function becomes
1
(3.7)

If we see as a disturbance that we neglect, we obtain the following diagram
Figure 3.28 : stability analysis of current control

Now, following the IMC, we saw that the controller is calculated with

The open‐ and closed‐loop transfer function are noted respectively and

(3.38)
(3.39)
1

Furthermore, if and , we can obtain the open‐ and closed‐loop transfer function

(3.40)
(3.41)

is a first order system, low pass filter, with a cut‐off frequency rad/s.
There is only one pole for and it’s located at (negative Real part of the Imaginary domain
means stability).

3.6.2 Voltage controller
PROPORTIONAL CONTROL ONLY
We consider again the Figure 3.16 without load disturbance and we obtain the
following diagram. The system transfer function is (equation (3.26))

41

3

Figure 3.29 : stability analysis of voltage controller

The open‐ and closed‐loop transfer function are noted respectively and .
(3.42)
(3.43)

As the previous case, if and , is a first order system, low pass filter, with a cut‐
off frequency rad/s.
There is only one pole for and it’s located at (negative Real part of the Imaginary domain
means stability).

PROPORTIONAL AND INTEGRAL CONTROL
As we explain during the voltage controller design, we decided to add a small integration
constant.
The open‐ and closed‐loop transfer function are noted respectively and .

3 3 3
(3.44)
3
3
(3.45)
1 3

WITH ACTIVE DAMPING GA
In this case, we consider the following diagram.
Figure 3.30 : stability analysis of voltage controller with active damping

3
(3.46)
3 3
(3.47)
1 3

3.6.3 Complete controller
To study the complete controller, we consider the following diagram.

42

Figure 3.31 : stability analysis of controller

We can now write the open‐ and closed‐loop transfer function and :

(3.48)
(3.49)
1

The following table sum‐up the different transfer functions of the controller.

P CONTROL PI CONTROL PI AND ACTIVE DAMPING GA

3

3
3

3 3
3

3 3
3

3 3 3
Table 3.4 : Transfer functions

3.6.4 Nyquist and Bode diagram
We can now plot the Nyquist and bode diagram for the complete controller. The Nyquist
diagram should be plot for the open‐loop transfer function . Bode plot are given for the
closed‐loop transfer function .
The following table shows the data used for Matlab script.

PARAMETERS VALUE
R (Ω) 0.05
L (H) 3e‐3
C (μF) 2200
ω (rad/s) 2π50
Rload (Ω) 500
/ (rad/s) 6.283e+003

43

/ (rad/s) 628.3
V controller, Kpv 0.0028
V controller, Kiv Given later
I controller, Kpi 18.8496
I controller, Kii 314.1593
Ga Given later
Table 3.5 : Calculation data
PARAM. VALUE
Kpv 0.0028
Kiv 0
Kpi 18.8496
Kii 314.1593
Ga 0
Pole1 ‐5575.1
Pole2 ‐708.1

Figure 3.32 : P control – Nyquist plot of open‐loop

Figure 3.33 : P control – Bode plot of closed‐loop

44


PARAM. VALUE
Kpv 0.0028
Kiv 0.01
Kpi 18.8496
Kii 314.1593
Ga 0
Pole1 ‐5575.6
Pole2 ‐704.1
Pole3 ‐3.5
Figure 3.34 : PI control – Nyquist plot of open‐loop

Figure 3.35 : PI control – Bode plot of closed‐loop

45

PARAM. VALUE
Kpv 0.0028
Kiv 1.7801
Kpi 18.8496
Kii 314.1593
Ga 0.0028
Pole1 ‐5575.1
Pole2 ‐708.1
Pole3 ‐628.3
Figure 3.36 : PI Ga control – Nyquist plot of open‐loop

Figure 3.37 : PI Ga control – Bode plot of closed‐loop

3.6.5 Conclusion
All the previous Nyquist plot show stability, the blue curve is far enough from the point “‐1”.
The phase margins are about 84deg (a good phase margin is higher than 60deg). The Gain margin

46

are also good in our cases (infinite). Nevertheless, we feel that the delay margin is really too small
compared to the system time constant.
ATTENTION, this analysis is probably too simplistic. We assumed that the converter and grid
parameters are perfectly known and it’s not correct in reality. The cross coupling cannot be perfectly
cancelled and the estimated values are not exactly equal to the real values, that is : ,
, , .
Another important point is that the analysis have been done in continuous time and should
be also done in discrete time in order to be close to the real system (discrete controller).

More Nyquist and Bode graph are plotted in APPENDIX E.

47

3.7 Phase Locked Loop (PLL)
The PLL is an important and critical part of the system. Its aim is to give the voltage angle of
the three‐phase system (Ua Ub Uc Figure 2.4). This angle is then used for all the dq‐transformations
in the model.

3.7.1 Design
The PLL was design according ([4] [14] ).

(3.50)
(3.51)

where and are gain parameters and the error signal ( is the Ki, and is the Kp of a PI
controller). The main difference is that in our case, with d‐oriented control, the error signal is
selected as:
instead of (chosen for flux oriented control).

Following the analysis of the thesis (or compendium), we can find the following PI parameters and
the following scheme.
2
, , (3.52) (3.53) (3.54)

where can be seen as the bandwidth of the PLL (rad/s), and is the estimated “grid” voltage
modulus.
Figure 3.38 : PLL scheme

Comments :
The PI coefficients can be fixed or calculated in Simulink according to the estimated value (or
measured value) .
The reference value ( 2. . 50 / ) can be also included as a initial condition in the
PI controller integrator.
The first selection of the PLL bandwidth is about 20Hz. It will be adjust later.

3.7.2 Simulations
The model was implemented in continuous first, then in discrete using the following scheme
for a discrete integrator :

48

Figure 3.39 : Discrete integrator (APPENDIX C. Digital simulation)

The sample frequency is chosen as : 2. 2. (Fsw is the switching
frequency, 20kHz).

Simulation1 : Balanced 3‐phase system
Figure 3.40 : Simulation‐Block Scheme

The results show that the original angle and the angle from the pll are equal (angular frequency is
also the same, 314.1593rad/s).

49

Figure 3.41 : Simulation‐Balanced 3‐phase system

50

Simulation2 : Unbalanced 3‐phase system
Now we create a voltage dip on phase C at 0.025s (30% dip, 70% of the voltage left).

Figure 3.42 : Simulation‐Unbalanced 3‐phase system

Now an oscillation is produced and we can see a small oscillation on theta_pll too.

Simulation3 : Balanced 3‐phase system, noise
We comeback to a balanced grid and we add noise to the 3‐phase voltages (random noise
for A, square wave for B, sawtooth wave for C, at different frequencies). We can see on the
simulation below that the angles are similar (a small error about 0.03deg can be seen with a zoom).

Noise phase A Noise phase B Noise phase C
Random wave form square wave sawtooth wave
At different frequencies : 100, 150, 200, 250, 1000, 5000, 10000Hz
Table 3.6 : Noise parameters

51

Figure 3.43 : Simulation‐Balanced 3‐phase system, noise

Remark and conclusion
We saw that the coefficients and can be calculated in Simulink according to .
Nevertheless, this can create a simulation issue at beginning of the simulation. We assume that for a
first implementation and a stiff grid, fixed coefficients can be easily used. Another solution could be
to start with fixed coefficients then switch to variable values.
To remove the oscillations on theta, we advice to reduce the PLL bandwidth to 5Hz.

3.7.3 Improvements and conclusion
As indicated in some papers (for example, see [30] in the case of amplitude distortion,
frequency distortion, phase distortion, harmonics, phase loss, random noise, the conventional PLL
presented here is not enough. For example, they use a controlled moving average algorithm to
extract and a phase locker.
Figure 3.44 : PLL proposed by [30]

52

3.8 Grid modeling
Figure 3.45 : Grid connected converter

The aim of this part is to modify the model introduced in section “2.2.2 Mathematical
model” (Figure 2.4) to simulate a grid connected converter. We are going to add the grid voltage and
impedance Eg, Rg and Lg. A switch will be modeled with a resistor Rb (high value for an open switch,
very small value for a switch closed). We can write four equations as below.

First equation : ig

1
(3.55)

Second equation : i

1
(3.56)

Third equation : Vc

1
(3.57)

Fourth equation :
(3.58)

With these four equations, we can establish the scheme Figure 3.47 to replace the simple grid model
of Figure 3.46 (establish in section “2.2.2 Mathematical model” Figure 2.4).

Figure 3.46 : Simple grid model (phase A)

53

Figure 3.47 : Simulink – New grid model (phase A)

We can also write more simple equations for a model without Cac.

(3.59)

Then if we inject di/dt of the first equation in the second :
1
(3.60) (3.61)

We can remark that if is too big compare to , the voltage Vppc will be highly dependent on
the current I and will vary. In the other hand, if is very small compare to , the last term of
the equation can be removed and is more stable.

54

3.9 Grid connected converter simulation
This section shows the simulations results of the complete system built with (Figure 3.49) :
A DISCRETE block
‐ Sampling system (sample and hold block)
‐ PLL
‐ Decoupled controller
PWM block (sinusoidal PWM)
An asymmetric PWM is used here, as we saw in the section “2.4.1 Sinusoidal PWM”, we have
2 2 .
Grid and rectifier model
We are now using the model presented in the previous part “3.8 Grid modeling” with small
unknown grid impedance and a switch (beaker) . We also add a second switch in
the output as we can see in Figure 3.48.

Figure 3.48 : Single phase schematic

3.9.1 Simulation steps, Simulink block diagram
SIMULATION STEPS
The simulation is composed by three steps. In the step I : SW1 and SW2 are open, step II :
SW1 closed and SW2 open, step III : SW1 and SW2 closed.

¬ Step : Synchronization
SW1 and SW2 are open.
The voltage is sent to the PLL and the voltage angle is calculated.
All IGBTs are OFF (the rectifier becomes a simple three‐phase diode rectifier). No current is
flowing into the rectifier.
The controller is in standby mode. All discrete integrators are disabled. All integrators should
be disabled when all IGBTs are OFF. Otherwise, the integrator part of the controller will try
to set the error to zero but since there are no switches activated, the error cannot be set to
zero. The integrator value will increase.
DC‐link link capacitor is charged to the reference value (in the simulation, this action
is done by setting the Initial Condition to into the integrator of the DC‐link model).
ATTENTION, the value should respect the condition explain in “2.2.3 Limitations” :
2 , where , is the Line‐to‐Neutral amplitude of .

55

The load is now _ . This resistor is set to a high value to avoid the discharge of .

¬ Step : Closing SW1
The AC‐side capacitor (filter) is charged (small transient).
All IGBTs are OFF and the controller is in standby mode (no integration).
As 2 , , there is no current flowing into the rectifier.

¬ Step : Closing SW2 and START
SW2 is closed. _ can now be neglected since _ .
The controller is fully activated and the IGBTs can be turned ON.

SIMULINK BLOCK DIAGRAM
Figure 3.49 : Top level Simulink model

The Figure 3.49 shows the top level block diagram of Simulink. You can find the details of
different block in APPENDIX F.
Before presenting the simulation results, we have to precise two important points, that are, how the
IGBT OFF‐state and how the disabled integrators are modeled in Simulink.

¬ IGBT OFF‐state
When the IGBTs are OFF in our simulation, no current is flowing into the rectifier (DC‐link voltage is
high enough and the body diode of the IGBTs are blocked). Consequently, we decided to force the
current to zero with the Figure 0.39 in APPENDIX F.

¬ Disabled integrators
The integrators are disabled by forcing the value to zero (another solution could be to set Ki to zero).
You can see the Simulink block in APPENDIX F, Figure 0.35.

3.9.2 Verification
In this sub‐section, we verify that the equation presented in the second Chapter (“2.2.3
Limitations”).

56

¬ Grid voltage
400 (Line‐to‐Line)
230.9 (Phase‐to‐Ground)
√
√2 230.9 326.6 (Phase‐to‐Ground amplitude)

¬ Minimum DC‐link voltage
The minimum DC‐link voltage is found with the equation (2.27) of section “2.2.3
Limitations”.
2 2
2 326.6
653.2 .

This minimum value have been verify in our simulation. In the Simulink simulation, we found
a minimum DC‐link voltage around 660V.
Finally, for our simulation we will select
700 .
This value is probably a bit low for an experiment. In reality, it will be better to select 15%
or 20% more (about 750V or 790V. Refer to “2.2.3 Limitations”).

¬ Inductance value
The equation (2.29) of section “2.2.3 Limitations” applied in our system becomes :
3
.

As we saw during the voltage controller design, section “3.5.2 Design of voltage controller”
equation (3.18), the d‐current is calculated by
2

3
Then, in steady‐state we can write the equality of power
(3.62)
Finally, the current becomes
2
(3.63)
3
2 700
6.668 6.7
3 326.6 150

This value is totally verified in the following simulation. We can now calculate the
inductance.
3

700
326.6
3

2 50 6.7
0.1131

We think that this value too high according to results read in some papers. We decided to
select the inductance around 3mH (it could be 5mH or 10mH).

57

3.9.3 Simulation results
SIMULATION 1 AND 2
The following Table 3.7 present a summary of the simulation parameters. All the parameters
for this “Simulation1” are presented in APPENDIX F, Table 0.3.

The simulation is performed with approximation :
¬ We assume that the voltage is equal to the grid voltage (Figure 3.48). That is only
true if the grid impedance is small enough compared to impedance RL.
¬ We assume that we know exactly the converter parameters, that is :
; ;

GRID AND CONVERTER VALUE TIME VALUE
Grid (V), line‐to‐line RMS 400 STEP II: SW1 closing at … (s) 0.005
(Ω), grid resistance 1e‐3 STEP III: IGBTs ON at … (s) 0.01
(H), grid inductance 1e‐5 step at … (s) 0.025
(Ω) 0.05
(H) 3e‐3
(F) 2200e‐6 CONTROLLER VALUE
(V) 700 , current controller 37.6991
STEP (V) 30 , current controller 628.3185
(Ω) 150 , voltage controller 0.0028
, voltage controller 0.01
Sample freq. 2 (kHz) 20
PWM VALUE
Triangular freq. (kHz) 10
Mode Asymmetric

Table 3.7 : Summary of simulation1 parameters
The basic waveforms are plotted in Figure 3.50. All voltages are phase‐to‐ground voltages.

For this simulation1, we selected a small grid impedance and we observe a voltage without
distortions, and we can say that and the grid voltage are equal (stiff grid). We will see the
influence of the grid impedance in the simulation3.

On the current plot (iabc), when the breaker SW1 is closing at time 0.005s, no current is
flowing into the rectifier. Then, at time 0.01s, we activate the IGBTs, we close SW2 and the system is
starting. We observe a small ripple on the current due to the switching. This ripple increases if the
switching frequency decreases or if the line inductance decreases.
Finally, at time 0.025s, the step on is starting. The current is reaching the saturation limit of
±15A and the DC‐link voltage is increasing linearly from 700V (initial condition) to 730V. Another
Simulation have been done with a bigger step of 100V on with saturation limit in the current
controller about ±50A (see APPENDIX F, Figure 0.27).

Furthermore, we observe a small overshoot on the DC‐link voltage . This overshoot may
increase if the switching frequency decrease. On Simulation2 Figure 3.51a., we plot the DC‐link
voltage for a switching frequency selected at 3kHz. We observe oscillations. These oscillations can be
remove by adjusting the PI controller coefficients. The calculation for the PI coefficients depends on
the bandwidth and selected as follwow :
2 /10 and 2 /100.

58

Nevertheless, when we select a switching frequency 3kHz, we modify the bandwidth ( 2 )
and we modify the PI controllers. For example, if we select the bandwidth with 3 2 /10
and 3 2 /100, the oscillations are highly reduced (Figure 3.51b.).

Figure 3.50 : Simulation1 results

a. b.
Figure 3.51 : Simulation2 with switching frequency 3kHz
a. voltage
b. with bandwidth /

59

SIMULATION3 – INFLUENCE OF THE GRID IMPEDANCE
The simulation3 have been done to show the influence of the grid impedance on the system.
We multiplied by 10 both and .

GRID MODIFICATION VALUE
(Ω), grid resistance 1e‐2
(H), grid inductance 1e‐4
Table 3.8 : Simulation3 – New grid impedance parameters
As we explain in section “3.8 Grid modeling”, if is too big compare to the total inductance value
, the voltage will be highly dependent on the current and will vary. The Figure 3.52a. shows
the effect of the grid impedance, the voltage is distorted. Despite that, the system is still working
well even if this voltage is used by the PLL to calculate the voltage angle. Figure 3.52b. shows the
voltage angle under simulation3 condition, there is no visible distortion.

a. b.
Figure 3.52 : Simulation3 with new grid parameters
a. voltage
b. Voltage angle Theta

SIMULATION4 – TEST WITH ACTIVE DAMPING GA
The results of simulation4 is plotted in APPENDIX F, Figure 0.28. The simulation parameters
are the same as simulation1 with the following modification on controller parameter. We also re‐
write the equation to find them (equation XXX section “3.5.3 Voltage saturation, anti‐windup, active
damping”).
PARAMETER MODIFICATION VALUE
3
active conductance 0.0028
3

Table 3.9 : Simulation4

We can see on Figure 0.28 that the controller doesn’t work properly anymore, some oscillation
appear on DC‐link voltage and the current is completely distorted.

We observed that the simulation becomes stable again by reducing the controller parameters
values. The Figure 0.29 shows a simulation with the following modified parameters :

60

PARAMETER MODIFICATION VALUE
3
active conductance 2.8216e‐005
, voltage controller 0.0355 3
Table 3.10 : Simulation4 – modified parameters

The Simulink diagram is given in APPENDIX F, Figure 0.41.

SIMULATION5 – ESTIMATED PARAMETERS , ,
For simulation5, we now assume that ; ; . One by one, we modify
(increase and decrease) the estimated value and verify the effect on the waveforms.

Â Resistance influence
A couple of tests have been done and we didn’t see any problem due to a bad estimation of
the line resistance.

Tests with equal to… Comments
No visible influence
0 , instability
. No visible influence
Table 3.11 : Resistance influence
Â Inductance influence

See Figure 0.30 in APPENDIX F.
‐ Distorted reference voltage
‐ Vdc oscillations
‐ Distorted reference voltage
.
‐ Vdc oscillations
‐ Distorted line current
Table 3.12 : Inductance influence
Â Capacitor influence

. ‐ Line current oscillation
‐ Vdc oscillation
No visible influence
Table 3.13 : Capacitor influence
Â Conclusion
As we can see in the previous tables, inductance and capacitor estimation are more critical
than resistance estimation. Nevertheless, we saw in simulation that a bad estimation with an
error about 20‐40% is not problematic. The waveforms are pretty similar.

61

SIMULATION 6 – LOAD STEP
Simulation 6 is done by modifying the load resistance from 150Ω to 30Ω, that corresponds,
to a load asking suddenly for 16kW (30Ω) instead of 3kW (150Ω).

Figure 3.53 : Simulation6 results

The input power (blue) is calculated with the following equation (3.18) :
3

2
The output power (black) as below (equation (3.62)) :

As we can see in the previous figure (Figure 3.53), an overshoot appears in the d‐components of the
current (6A overshoot). Nevertheless, this overshoot is not so visible on the 3‐phase current.

Regarding the DC‐link voltage, we observe a small drop (5.5V, 0.7%). The controller is acting and
after a couple of millisecond, the error is set to zero again. The controller performance seems to
good for disturbance rejection.

62

VOLTAGE ORIENTED CONTROL – IMPLEMENTATION
4 VOLTAGE ORIENTED CONTROL – IMPLEMENTATION
4.1 Block diagram
The set‐up present in the lab can represented with the following block diagram. It shows one
power stage, electronic stage, and software stage.
Figure 4.1 : Laboratory set‐up

MATERIAL COMMENTS
dSpace system DS1103
Computer PC
Matlab / Simulink Real Time Workshop
library and dSpace library
Control Desk software Used for real time control
Measurement box Voltage and current
Emitter card Optical emitters
Receiver card and IGBT drivers Optical receivers
Table 4.1 : Lab material
This set‐up is not running yet. No experiments have been done in this thesis.

4.2 Principle
From your Simulink model (see next section), Matlab generates a C‐code and send it to the
hardware (dSpace DS1103) connected to the PC.

63

Then, using Control Desk software, you can build an interface with control panel : knobs, control
buttons. You can also add visualizations : led, gauge, graph and so on.

To be able to run our system, some modification need to be done on our Simulink model.

4.3 Simulink model modification
The top level Simulink model for implementation is show in Figure 4.2.

Figure 4.2 : Top level Simulink model for dSpace implementation

ADC
Figure 4.3 : ADC example (see APPENDIX G. Figure 0.42)

The important information using ADC and DAC is shown in the following table. You need to multiply
by 10 a value from ADC, and divide by 10 before sending to DAC.

ADC DAC
Input voltage Correspondance Simulink Output voltage
range in Simulink value range
‐10V…+10V ‐1…+1 ‐1…+1 ‐10V…+10V
Table 4.2 : ADC/DAC value range

64

PWM
The PWM block have been replaced by the dSpace PWM block “DS1103SL_DSP_PWM3”. This is a
sinusoidal symmetric PWM (Ftriangle = Fswitching = Fsampling). You can modify the carrier wave
(triangle) and the deadtime duration.
“PWM stop” allows to enable(PWM stop = 0) or disable(PWM stop = 1) the PWM block. This signal
needs double type and not Boolean (but following “Simulink help” it should be Boolean). The
Termination and Initialization values of the block should be set (see next section for explanation
about Termination and Initialization).

The input range for “duty cycle abc” is [0;+1]. Finally, we have to send our three‐phase reference
voltage to this block but a scaling block is needed. This block is included to the control block and
shown in Figure 4.4.

Figure 4.4 : Scaling block

CONTROL SYSTEM AND PLL
You can find the detail of this block in APPENDIX G. Figure 0.43. You can see that the scaling block
presented above is included to this block. The control is totally similar to the one presented in
Chapter 3 except that :
All the sample & hold block have been removed but the system is still discrete.
The sample time "Ts" is replaced by "‐1" (inherited).

The enable signal is maybe not useful. It could be removed. It depends how will be run the system.
But if it’s used, the output port “Uabc_ref range [0;1]” should be set to the following characteristics :
Reset when disabled
Initial output = 0.
In this configuration, when the block is disabled, the output will be zero and the PWM block will see
zero duty cycle and will open the switches.

TRIGGER SIGNAL, SYNCHRONIZATION
The sample & Hold have been removed. Now, we need to specify when acquire a sample. We know
that we need to sample on the peak of the triangular wave of the PWM, ideally, on every peak that
is the asymmetric PWM.
We guess that more than one solution is possible to run the system. But for simplicity, as we said
above, we decided to use the PWM block “DS1103SL_DSP_PWM3” using a symmetric PWM.

Furthermore, this block is link to an interruption “DS1103SLAVE_PWMINT”. The interruption is
generated every POSITIVE PEAK of the triangular wave of block PWM3 as shown in Figure 4.5.
Consequently we have : Finteruption = Fsampling = Ftriangle = Fswitching.

65

Figure 4.5 : Matlab Help from dSpace, PWM interruption [33]

The interrupt is generated that can be shifted nearly over the whole PWM period by specifying the
interrupt alignment (Source : dSpace Help in Matlab [33] ).

In Simulink, a block “DS1103SLAVE_PWMINT” is available. To trigger the whole Simulink model, we
have to link this block to another block called “Timer Task Assignment” as shown in the top‐level
model Figure 4.2. Finally, every interruption signal, ONE sample will be acquired.

Nevertheless, the “overrun” condition should be checked. We need to be sure that the calculation
(in the controller) is finished before a new sample is acquired.

CONTROL SIGNAL “GO”
The “GO” signal (Figure 4.2) is used to activate the integrator part of the controller (see section
“3.9.1 Simulation steps, Simulink block diagram” for explanation). It is also used to enable or disable
PWM block.

HOW TO FORCE IGBTS OFF
It’s possible to force IGBTs OFF disabling the block “Control system and PLL” since the output will be
zero when disable (if set correctly…). A zero value will be sent to the PWM block and the switches
will be open.
Another solution in presented in Figure 4.6 and is present in the main block diagram in APPENDIX G.
Figure 0.43.

66

Figure 4.6 : How to force IGBTs OFF (complete diagram : APPENDIX G. Figure 0.43)

The switches are activated by the “GO” signal in our model.
If GO = 0 Output = 0 IGBT = OFF
If GO = 1 Output = Ubac range [0;1] IGBT = ON

4.4 Running an experiment
To run an experiment we need to introduce some important points that are :
STOP/PAUSE/RUN mechanism, simState variable, Initialization and Termination value, how to build a
model and which parameters should we used, and how to use Control Desk software.
A tutorial is also available in [37] , and we also advice to use the dSpace Help in Simulink (more
useful than the dSpace books).

SIMSTATE VARIABLE
The simState variable is an internal variable that allows to read or set the simulation state of the
application [33] . This variable is created when the system is built (see how to build a model in the
following).

It can take the following value (Table XXX).

Simulation State simState variable
STOP 0
PAUSE 1
RUN 2
Table 4.3 : simState values

STOP/PAUSE/RUN MECHANISM
The STOP/PAUSE/RUN mechanism depends on the simState variable. By controlling it, you can stop,
pause or run your experiment.
In our case, we chose to control it via Control Desk. When your system is built and your variable
description file (“.sdf”) is opened in Control Desk (see next paragraph), you can find this variable in
the main group of variable.

The following figure shows a part of control panel in Control Desk, the simState is linked to “Push
Buttons”.

67

simState variable
Enable
GO signal
Figure 4.7 : Control Panel in Control Desk

In each Simulink block, you can specify an Initialization and Termination value. The following table
shows the links with the simState variable.

STATE SIMSTATE RESULT
STOP 0 Termination code executed. Termination value are used.
PAUSE 1 If the previous state was in RUN, no Termination values are used, the
current outputs are kept.
If the system was in STOP mode, the Initialization values are used.
RUN 2 If the simulation was previously in the PAUSE mode, the execution of
the application is re‐enabled.
If the previous state was STOP, the states of the model are reset to
their initial values and the execution of the application is restarted.
Table 4.4 : Relation between application state and Initialization and Termination values

SIMULATION PARAMETERS AND “BUILD MODEL”
When your Simulink model is modified, you can BUILD the model from Simulink using :
//Tools/Real Time Workshop/Build Model (or CTRL+B)

But before that, you may need to modify the Configuration Parameters as follow :

PARAMETERS VALUE
Solver/Step Fixed
Solver/Stop Time INF
Optimization/block reduction Disable
Real Time Workshop/System Target File rti1103.tlc
Table 4.5 : Configuration Parameters before BUILD
Before pressing “CTRL+B” (build), we advice to open Control Desk software. In this case, Control
Desk will automatically detect that a new file have been built (variable description file with extension
“.sdf”).

Then, a “new experiment” should be created, and the “.sdf” file should be “added to experiment”.
You can now create a new “layout”. Since you have the layout open, you can add buttons, knobs,
display, gauge, numeric input (to write a value) and so on. After that, you can link your Simulink
variables (or labels) to graphical instruments, for example, a button to control this variable or a

68

graph for visualization. The variables are visible in the “Tool Window” in the bottom part of the
Control Desk interface.

ATTENTION !
When you build the model, the C‐code generated is automatically sent to your hardware and the
application START TO RUN (simState = 2). So, as you can see in the Figure 4.2, the signal GO and the
Enable are set to zero. Consequently, when our system is built and start running, the PWM is OFF
and the controller is disabled.

69

CONCLUSIONS AND FUTURE WORK
5 CONCLUSIONS AND FUTURE WORK
Controller lab‐tests
In the Chapter 3, some simulations were presented. The controller seems to be correct and
stable. We suppose that some lab‐tests can now be achieved with a grid‐connected converter with
simple resistive load.
The Simulink file prepared for implementation may need to be slightly modified but the idea was
presented in Chaper4 with some key point to run an experiment with dSpace. A tutorial is available
at the reference [37] .

Stability analysis
In this report, a simple stability analysis have been done. Nevertheless, this analysis is quite
simplistic (with approximations) and have been realized in continuous time only. It should be also
complete in discrete time because the controller is implemented in discrete time.

Deadtime
As we explain in the first part (2.4.3 Dead time effect), the performances of the converter
are affected by injection of deadtime in the PWM signals to avoid short circuit of the DC‐link. We
suppose that some simulations of this deadtime and some compensation should be done before
testing the controller in the laboratory.

Modulation method
The modulation method could be improved. In our system, we decided to implement a
sinusoidal Pulse Width Modulation mainly for its simplicity and acceptable performances. We advice
to test it in the lab. Nevertheless, a simulation with Space Vector Modulation (SVM) should be also
simulated and a deep comparison to sinusoidal PWM could be done. The SVM is known for its
effectiveness, simplicity for implementation, harmonics reduction.

Control method
A last possible improvement could be done by implementing a Virtual Flux Oriented Control
(VFOC). It could improve the performance under non‐ideal line voltage conditions. Furthermore, this
method could be useful if a machine is added to the model (AC side) because machine models are
generally done with flux‐oriented reference.
We also advice to implement a load current controller. Reading some papers, we saw some
battery charger configuration with another stage after the rectifier (on more leg with two IGBTs for
DC‐DC conversion). A load current controller was responsible of the switches for this stage ([3] ).

70

REFERENCES
REFERENCES
Control and Modeling of PWM rectifiers
[1] BLASKO V., KAURA V. “A New Mathematical Model and Control of a Three‐Phase AC–DC Voltage
Source Converter”. IEEE Transactions on Power Electronics, 1997. Vol.12 , issue: 1. Pages: 116 –
123.

[2] BO YIN, ORUGANTI R., PANDA S.K., BHAT A.K.S. “A Simple Single‐Input‐Single‐Output (SISO) Model for
a Three‐Phase PWM Rectifier”. IEEE Transactions on Power Electronics, 2009. Vol.24, issue: 3.
Pages: 620 – 631.

[3] BOJRUP MARTIN. “Advanced Control of Active Filters in a Battery Charger Application”. Phd Thesis,
Department of Industrial Electrical Engineering and Automation (IEA), Lund Institute of
Technology (LTH), Lund, Sweden. 1999. 124p. ISBN 91‐88934‐13‐6.

[4] HARNEFORS LENNART. “Control of Variable‐Speed Drives”. Applied Signal Processing and Control,
Department of Electronics, Mälardalen University, Västerås, Sweden, 2002. 194p.

[5] HENGCHUN MAO, BOROYEVICH D., LEE F.C.Y. “Novel Reduced‐Order Small‐Signal Model of a Three‐
Phase PWM Rectifier and Its Application in Control Design and System Analysis”. IEEE
Transactions on Power Electronics, 1998. Vol.13 , issue: 3. Pages: 511 – 521.

[6] HITI S., BOROYEVICH D., CUADROS, C. “Small‐signal modeling and control of three‐phase PWM
converters”. Industry Applications Society Annual Meeting, IEEE 1994. Vol.2, pages: 1143 –
1150.

[7] H.S. KIM, H.S. MOK, G.H. CHOE, D.S. HYUN, S.Y. CHOE. “Design of Current Controller for 3‐Phase
PWM Converter with Unbalanced Input Voltage”. Power Electronics Specialists Conference, IEEE
1998. Vol.1. Pages: 503 – 509.

[8] JASINSKI M., ANTONIEWICZ P., KAZMIERKOWSKI M.P. “Vector control of PWM rectifier ‐ inverter fed
induction machine ‐ a comparison”. Compatibility in Power Electronics, IEEE 2005. Pages: 91 –
95.

[9] KASMIERKOWSKI MARIAN P., BLAABJERG F., KRISHNAN R.‐ “Control in power electronics, selected
problem”. Elsevier Science, USA. 2002. 518p. ISBN : 0‐12‐402772‐5.

[10] KASMIERKOWSKI MARIAN P. “Current Control Techniques for Three‐Phase Voltage‐Source PWM
Converters: A Survey”. IEEE Transactions on Industrial Electronics. Vol.45 , issue: 5. 1998. Pages:
691 – 703.

[11] KNAPCZYK MICHAŁ, PIENKOWSKI KRZYSZTOF. “High Performance decoupled control of PWM rectifier
with load compensation”. Politechnika Wrocławska, Instytut Maszyn, Napedów i Pomiarów
Elektrycznych. 2007. 11p. Available at :
http://www.imne.pwr.wroc.pl/Wydawnictwa/PNIMNIPEnr60/Napedy/pdf/4%20Michal%20KNA
PCZYK%20Krzysztof%20PIENKOWSKI%202.pdf

[12] LUNDBERG STEFAN. Lecture slides : ENM075 Electric Drives II. Department of Energy and
Environment, Chalmers University of Technology, Göteborg, Sweden. 2009.

[13] MALINOWSKI MARIUSZ. “Sensorless Control Strategies for Three‐Phase PWM Rectifiers”. PhD
Thesis, Warsaw University of Technology, Faculty of Electrical Engineering, Institute of Control
and Industrial Electronics. Warsaw, Poland. 2001. 128p.

71

REFERENCES

[14] OTTERSTEN ROLF. “On Control of Back‐to‐Back converters and Sensorless Induction Machine
Drives”. PhD Thesis, Department of Electric Power Engineering, Chalmers University of
Technology, Göteborg, Sweden. 2003. 165p. ISBN : 91‐7291‐296‐0.

[15] RODRIGUEZ J.R., DIXON J.W., ESPINOZA J.R., PONTT J., LEZANA, P. “PWM Regenerative Rectifiers: State
of the Art”. IEEE Transactions on Industrial Electronics, 2005. Vol.52, issue: 1. Pages: 5 – 22.

[16] RUNXIN WANG, JINJUN LIU. “Redefining a New‐Formed Average Model for Three‐Phase Boost
Rectifiers/Voltage Source Inverters”. Applied Power Electronics Conference and Exposition,
2009. Pages: 1680 – 1686.

[17] WANG XU, HUANG KAIZHENG, YAN SHIJIE, XU BIN. “Simulation of Three‐phase Voltage Source PWM
rectifier Based on Space Vector Modulation”. Control and Decision Conference, Chinese, IEEE
2008. Pages: 1881 – 1884.

[18] WEI KE‐XIN, WANG SHUI‐MING. “Modeling and Simulation of Three‐Phase Voltage Source PWM
Rectifier”. International Conference on Advanced Computer Theory and Engineering, IEEE 2008,
Pages: 982 – 986.

[19] YU FANG, YONG XIE, YAN XING. “Study on control strategy of three phase high power factor PWM
rectifier”. International Conference on Electrical Machines and Systems, IEEE 2008. Pages: 1832
– 1837.

Power Electronics
[20] ERIKSON ROBERT W., MAKSINMOVIĆ D. “Fundamentals of Power Electronics”. Second Edition.
Springer Science, USA. 2001. 883p. ISBN : 978‐0‐7923‐7270‐7.

[21] MOHAN N., UNDELAND T., ROBBINS W. “Power Electronics, Converters, Applications and Design”.
Second Edition. John Wiley & Sons, Inc. USA. 1995. 802p. ISBN : 0‐471‐30576‐6.

[22] MUHAMMAD H. RASHID. “Power Electronic Handbook, Devices, Circuits, and Applications”. Second
Edition. Burlington, MA : Academic. 2006. 1172p. ISBN: 978‐0‐12‐088479‐7.
Available at : http://www.sciencedirect.com/science/book/9780120884797 (Chalmers library).

PWM
[23] BONGIORNO MASSIMO, SANINO A. Lecture slides : ENM100 Power Electronic Solutions for Power
Systems. Department of Energy and Environment, Chalmers University of Technology,
Göteborg, Sweden. 2009.

Carrier‐based PWM
[24] HAVA AHMET M., KERKMAN RUSSEL J., LIPO THOMAS A. “Carrier‐Based PWM‐VSI Overmodulation
Strategies : Analysis, Comparison, and Design”. IEEE Transactions on Power Electronics, 1998,
Vol.13, issue: 4, pages: 674 – 689.

SVM
[25] ANALOG DEVICES APPLICATION NOTE AN31‐17. “Implementing Space Vector Modulation with the
ADMC331”. Analog Devices Inc., January 2000.

[26] DORIN O. NEACSU. “Space Vector Modulation‐An Introduction”. Tutorial at IECON2001, the 27th
Annual Conference of the IEEE Industrial Electronics Society. 2001.
Available at : http://www.et.upt.ro/admin/tmpfile/fileM1224954797file490353adde0d4.pdf

72

REFERENCES
[27] JIN‐WOO JUNG. “Project #2 Space Vector PWM inverter”. Project performed at Mechatronic
Systems Laboratory, Department of Electrical and Computer Engineering, The Ohio State
University, USA. 2005. Available at :
http://www2.ece.ohio‐state.edu/ems/PowerConverter/SpaceVector_PWM_Inverter.pdf

PLL
[28] AMUDA L.N., CARDOSO FILHO B.J., SILVA S.M., SILVA S.R., DINIZ A.S.A.C. “Wide bandwidth single and
three‐phase PLL structures for grid‐tied PV systems”. Photovoltaic Specialists Conference, IEEE
2000. Pages: 1660 – 1663.

[29] CHUNG S.K. “Phase‐locked loop for grid‐connected three‐phase power conversion systems”.
Electric Power Applications, IEE Proceedings. 2000. Vol.147 , issue: 3. Pages: 213 – 219.

[30] SALAMAH A.M. “Three‐phase phase‐lock loop for distorted utilities”. IET Electric Power
Applications, 2007. Vol.1, issue : 6, pages: 937–945.

Deadtime
[31] JONG WOO CHOI, SUNG IL YONG, SEUNG KI SUL. “Inverter output voltage synthesis using novel dead
time compensation”. IEEE Applied Power Electronics Conference and Exposition, 1994. Vol.1,
Pages: 100 – 106.

[32] SEUNG‐GI JEONG, MIN‐HO PARK. “The analysis and compensation of dead‐time effects in PWM
inverters”. IEEE Transactions on Industrial Electronics, vol.38, no.2, 1991. Pages: 108 – 114.

dSpace
[33] dSpace Help in Simulink.

[34] JUSTIN D. LANGDON. “Design and Adaptive Control of a Lab‐based, Tire‐coupled, Quarter‐car,
Suspension Test Rig for the Accurate Re‐creation of Vehicle Response”. MSc Thesis, Virginia
Polytechnic Institute and State University, USA. January 31, 2007. Available at:
http://scholar.lib.vt.edu/theses/available/etd‐02132007‐
112050/unrestricted/Langdon_Thesis_Rev_Final_ETD_2007.pdf

[35] KIRAN KUMAR GUNDA. “Adjustable Speed Drives Laboratory Based on dSpace Controller”. MSc
Thesis, Department of Electrical & Computer Engineering, Louisiana State University and
Agricultural and Mechanical College, USA. 2008.

[36] Laboratory Tutorial, Massachusetts Institute of Technology, Department of Mechanical
Engineering, 2.737 Mechatronics–Spring 2006, February 14, 2006. Available at:
http://web.mit.edu/2.737/www/labs/General/tutorial.pdf

[37] NICANOR QUIJANO, KEVIN PASSINO. “A Tutorial Introduction to Control Systems Development and
Implementation with dSPACE”. Dept. of Electrical Engineering, The Ohio State University, USA.
2002. Available at : http://www2.ece.ohio‐state.edu/~passino/dSPACEtutorial.doc.pdf

73

APPENDICES
APPENDICES
A. Three‐phase system – Coordinate transformations
A.1 Voltage and current definition
First of all, we can define the voltage and current of a three‐phase system :

2

3
4

3
(positive sequence here)

2

3
4

3

For any three‐phase system composed of positive and negative sequence we have

0

If the system present an asymmetry, a zero sequence appears and is define as the mean value

.
3

A good thing is that there will never be any zero sequence in the currents, provided that there is no
neutral connection.

A.2 Equivalent two‐phase system, ‐transformation (Clarke)
A three‐phase system can be described with only two components α and β (real and
imaginary respectively). Furthermore, we call a space vector the quantity

2
.
3

where is a scaling constant. The transformation from ABC‐to‐αβ (Clarke transformation)
depending on the scaling constant is :

74

APPENDICES

0
√ √ Amplitude invariant 1
1
RMS‐value invariant
and √2

3
1 0 Power invariant
√ 2
.
√

A.3 Synchronous coordinate, dq‐transformation (Park)
We can now define a transformation of the previous space vector (we now
drop the time argument “(t)” for simplicity) with

where . This transformation makes similar to fixed complex phasor. This transformation
is called dq‐transformation and can be regarded as observing the space vector from a coordinate
system rotating with the frequency (synchronous coordinate or dq‐coordinate). We denote the
space vector in synchronous coordinates as
.

Figure 0.1 : Relation between ‐frame and dq‐frame (rotating) [23]

Giving dc‐steady state quantity, the synchronous coordinates are very useful for analysis,
implementation of control algorithm (controller design is easier on dc‐quantities).

We can write

and .
Source : [4]

75

APPENDICES
A.4 Simulation
These transformations and the theta angle (voltage angle) are very critical for all the
simulations in the project. To be sure that we have the correct angle, we created this angle first,
then, a three‐phase voltage system is created according to this angle as we can see in the following
block diagram.

Em will be the amplitude
of the 3‐phase voltages
(amplitude invariant
transformation).

2 50 /
Figure 0.2 : Three‐phase system simulation

The transformations are implemented as below.
Figure 0.3 : ‐transformation

Figure 0.4 : dq‐transformation

The simulation results are plotted on the following figure.

76

APPENDICES
Figure 0.5 : Simulation of coordinates transformations

Simulation comments :
Theta is positive.
Voltage is placed on the d‐axis.
Beta signal is delay (lag).
We verify a direct three‐phase system (A first[0 rad], B in second[‐2π/3 rad], C third[‐4π/3
rad]).

A.5 Impedance in synchronous coordinates
We assume in the report (current controller design) that the impedance is :
. We can prove this relation with the following.
is a general space vector, its transformation in synchronous coordinates is

and its time derivative is transformed as

.

Then, using the derivative operation / we get

In the Laplace domain, the following substitution is made : . This implies that the
complex impedance of an inductor in synchronous coordinates is

77

APPENDICES
Figure 0.6 : Illustration ‐ and dq‐impedance

Source : [4]

78

APPENDICES
B. Voltage and current control, continuous simulation
B.1 Simulink current control tests – Block diagram
Figure 0.7 : Simulink current control tests – Block diagram

79

APPENDICES
B.2 Continuous voltage controller, simulation with saturation, anti‐

windup, active damping

Figure 0.8 : Voltage controller – Simulation with saturation, anti‐windup, active damping

NEW PARAMETERS VALUE
Ga 0.0057
Kiv 7.1205
Table 0.1 : New parameters for voltage controller with active damping

80

APPENDICES
C. Digital simulation
DISCRETE INTEGRATOR
As the controller will be digital, we decided to simulate the control system in discrete time.
The integrator have been implemented as below.
U: input / Y : output

1 1

1

1 1

We can also draw the block scheme with the
following equation :

Figure 0.9 : Discrete integrator

REMARK FOR SIMULINK SIMULATION
In a simulation where discrete and continuous blocks are used at the same time, in order to
come back from discrete to continuous, we should add a zero to the discrete signal with sampling
time “INF” as below. Then, the output signal is treated as continuous by Simulink.
Discrete Continuous
Figure 0.10 : Simulink discrete‐to‐continous

81

APPENDICES
D. Voltage and current control, discrete time simulation
Figure 0.11 : Controller simulation results (discrete)

Table 0.2 : Voltage and current control, discrete time simulation
Parameters Value / (rad/s) 1.26e3

R (Ω) 0.1 V controller, Kpv 0.0057
L (H) 5e‐3 V controller, Kiv 0.01
C (μF) 2200 I controller, Kpi 62.8
ω (rad/s) 2π50 I controller, Kii 1.26e3
Em (V), ph‐to‐gnd amplitude (=Ed) 115√2 I saturation (A) ±15
Fsw (kHz), switching frequency 20 Vdc step at 0.03 (V) 50
Rload (Ω) 500 Triangular wave Frequ. (kHz) 20
Vdc reference (V) 400 Sampling frequency (kHz), FS=2 Ftri 40
/ (rad/s) 1.26e4

82

APPENDICES
E. Stability analysis cont.
E.1 Simulations
Figure 0.12 : Nyquist of Li

Figure 0.13 : Bode of Li

83

APPENDICES
Figure 0.14 : Bode of Si

Figure 0.15 : Nyquist of Lv (P only)

84

APPENDICES
Figure 0.16 : Bode of Lv(P only)

Figure 0.17 : Bode of Sv(P only)

85

APPENDICES
Figure 0.18 : Bode of Lvi(P only)

Figure 0.19 : Nyquist of Lv (PI)

86

APPENDICES
Figure 0.20 : Bode of Lv (PI)

Figure 0.21 : Bode of Sv (PI)

87

APPENDICES
Figure 0.22 : Bode of Lvi (PI)

Figure 0.23 : Bode of Lv (PI Ga)

88

APPENDICES
Figure 0.24 : Bode of Lv (PI Ga)

Figure 0.25 : Bode of Sv (PI Ga)

89

APPENDICES
Figure 0.26 : Bode of Lvi (PI Ga)

90

APPENDICES
F. Grid connected converter simulation cont.
F.1 Data and simulations
GRID VALUE PWM VALUE
Frequency (Hz) 50 Triangular freq. (kHz) 10
(V), line‐to‐line RMS 400 Mode Asymmetric
(V), line‐to‐neutral RMS 230
(V), line‐to‐neutral amplitude 327 CONVERTER VALUE
(Ω), grid resistance 1e‐3 (Ω) 0.05
(H), grid inductance 1e‐5 (H) 3e‐3
(F) 2200e‐6
BREAKER SW1 VALUE (kHz), switching freq.=Fc 10
Rb_open (Ω) 1e5 (Ω) 150
Rb_close (Ω) 0.01 _ (Ω) 1e5
Cac (nF) 1 (V) 700
Closing at time… (s) 0.005 STEP (V) 30
Step at… (s) 0.025
IGBTs ON/OFF SIGNAL VALUE Power / (W) 3267
IGBTs ON at time… (s) 0.01
ON‐state 1 CONTROLLER VALUE
OFF‐state 0 (Ω) R
(H) L
PLL VALUE (F) C
Bandwidth (Hz) 20 2 /10 (rad/s) 1.2566e+004
Bandwidth (rad/s) 125.6637 2 /100 (rad/s) 1.2566e+003
48.3510 , current controller 37.6991
0.7695 , current controller 628.3185
DISCRETE SYSTEM VALUE , voltage controller 0.01
Sample freq. 2 (kHz) 20 Saturation current control (A) ±15
Sample time (s) 5e‐005 Filter /10 (rad/s) 1.2566e+003

SIMULATION VALUE
Solver Step Variable
Step max 1/ 10
Faster solver Ode23tb
Tolerance 1e‐3
Table 0.3 : Parameters of simulation1

91

APPENDICES
Figure 0.27 : Simulation1 – 100V Step on , saturation limit±50A (current controller)

92

APPENDICES
Figure 0.28 : Simulation4 with active damping

93

APPENDICES
Figure 0.29 : Simulation4 with active damping, modified controller parameters

94

APPENDICES

Figure 0.30 : Inductance influence – Test :

Figure 0.31 : Inductance influence – Test : 0.9

Figure 0.32 : Capacitor influence – Test : 0.9

95

APPENDICES
Figure 0.33 : Simulink – DISCRETE BLOC

96

APPENDICES
Figure 0.34 : Simulink – DISCRETE BLOCK / PLL

Figure 0.35 : Simulink – DISCRETE BLOCK / DECOUPLED CONTROLLER / Discrete PI V Controller

Figure 0.36 : Simulink – GRID AND RECTIFIER MODEL / eg_abc

97

APPENDICES
Figure 0.37 : Simulink – DISCRETE BLOCK / Decoupled Controller

98

APPENDICES
Figure 0.38 : Simulink – PWM block

Figure 0.39 : Simulink – GRID AND RECTIFIER MODEL / GridPhaseB

99

APPENDICES
Figure 0.40 : Simulink – GRID AND RECTIFIER MODEL

100

APPENDICES
Figure 0.41 : Simulink – DISCRETE BLOCK / Decoupled Controller with active damping

101

APPENDICES
F.2 Matlab Script (Vdc Step)
close all; clear all; clc
%***********************************************************************
% GRID / BREAKER / COMMAND
%***********************************************************************
grid_f = 50;
w = 2*pi*grid_f; % Line frequency
Urms = 400; % Line-to-line RMS voltage
Vrms = 400/sqrt(3); % Line-to-ground RMS voltage
Eg = Vrms*sqrt(2) % Phase-to-ground voltage amplitude
Rg = 1e-3; % 1e-2
Lg = 1e-5; % 1e-4
%BREAKER
Rb_open = 1e5; %ATTENTION VALUE
Rb_close = 0.01;
Cb = 1e-9 ; %Cac - ATTENTION VALUE (NEED DESIGN FILTER, avoid resonnance
frequency)
%STEP breaker SW1 command : 0/1

breaker_step_time = 0.005; %Close switch at...
breaker_initial_value = 0;
breaker_final_value = 1; %Or more than 0
%IGBTs ON/OFF SIGNAL (To activate switching)

IGBTONOFF_step_time = 0.01;
IGBTONOFF_initial_value = 0;
IGBTONOFF_final_value = 1;
%***********************************************************************
% CARRIER BASED PWM PARAMETERS
%***********************************************************************
Carrier_amp = 1; % Triangular wave Amplitude
Carrier_f = 10e3; % Triangular wave frequency = Fsw
Tc = 1/Carrier_f; % Triangular wave period
%***********************************************************************
% CONVERTER PARAMETERS
%***********************************************************************
R = 0.05; % Line Resistance
L = 3e-3; % Line inductance
C = 2200e-6; % DC bus capacitor
Fsw = Carrier_f; % Converter switching frequency = Triangular wave f
Rload = 150; % Output load, Pout about 800W
Rload_temp = 1e5; % Temporary output load to avoid discharge of C
Vdc_ref = 700; % Output voltage reference
initial_condition_integrator = Vdc_ref; % IC model integrator

102

APPENDICES
%***********************************************************************
% CONTROLLER PARAMETERS
%***********************************************************************
Ts = 0.5*Tc; % Sample time, half of triangular wave period, Fs = 2*Fc
Fs = 1/Ts;
%ESTIMATED PARAMETERS
R_hat = R;
L_hat = L;
C_hat = C; % probably, C_hat = C OK
Vpcc_hat = Eg ; % Ph-to-gnd - Possible for stiff grid, otherwise, Vpcc <
Eg
%CURRENT PI Regulator (thesis, state-variable W=Vdc^2)

alphaI = Fs/10*2*pi; % Bandwidth in rad/s
Kpi = alphaI*L_hat
Kii = alphaI*R_hat
%VOLTAGE PI Regulator (thesis, state-variable W=Vdc^2)

alphaV = Fs/100*2*pi; % Bandwidth in rad/s
Kpv = alphaV*C_hat/(3*Vpcc_hat)
Kiv = 0.01
%SATURATION (TO MODIFY, depends on rectifier limit)

Isaturation_upper_limit = 50; %saturation on Iref, V PI controller
Isaturation_lower_limit = -50;
%FEEDFOWARD Ed_hat/Eq_hat FILTER

alphaf_ff = alphaI/10;

%***********************************************************************
% PLL PARAMETERS
%***********************************************************************
%Gain gamma1&2 : calculated in simulink (we assume Ed_hat and Eq_hat can
change)
Fbandwidth_pll = 20; %bandwidth in Hz
rho_pll = 2*pi*Fbandwidth_pll; %bandwidth in rad/s
gam1 = (rho_pll^2)/Vpcc_hat
gam2 = 2*rho_pll/Vpcc_hat
%***********************************************************************
% TESTS
%***********************************************************************
%INPUT STEP
input_step_time = 0.025;
input_step_value = 100;

103

APPENDICES
G. Implementation
Figure 0.42 : ADC block

104

APPENDICES
Figure 0.43 : Control block

105

Voltage Oriented Control of Three Phase Boost PWM Converters

Uploaded by

Copyright:

Available Formats

Voltage Oriented Control of Three Phase Boost PWM Converters

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Voltage Oriented Control of Three Phase Boost PWM Converters

Uploaded by

Copyright:

Available Formats

Voltage Oriented Control of Three‐Phase

3.1 Introduction – References chosen 18

3.6.1 Current controller 41

4.1 Block diagram 63

a) General phasor diagram b) Rectification (at UPF) c) Regeneration (at UPF)

 Fixed switching Freq. (easier design input filter)  Coordinate transformation and decoupling between

Figure 2.15 : One leg with transistors B1 and B2 – On/Off states, deadtime Td [32]

 The load is now _ . This resistor is set to a high value to avoid the discharge of .

The basic waveforms are plotted in Figure 3.50. All voltages are phase‐to‐ground voltages.

B.2 Continuous voltage controller, simulation with saturation, anti‐

Parameters Value / (rad/s) 1.26e3

Figure 0.31 : Inductance influence – Test : 0.9

Figure 0.32 : Capacitor influence – Test : 0.9

%STEP breaker SW1 command : 0/1

%IGBTs ON/OFF SIGNAL (To activate switching)

%CURRENT PI Regulator (thesis, state-variable W=Vdc^2)

%VOLTAGE PI Regulator (thesis, state-variable W=Vdc^2)

%SATURATION (TO MODIFY, depends on rectifier limit)

%FEEDFOWARD Ed_hat/Eq_hat FILTER

You might also like

Fixed switching Freq. (easier design input filter) Coordinate transformation and decoupling between

The load is now _ . This resistor is set to a high value to avoid the discharge of .