Addressing modes

Instructions-0,1,2,3 address
 Instruction Set Design
Very complex because it affects so many aspects of the computer system

Defines many of the functions performed by the processor

Fundamental design issues:

Operation repertoire Data types Instruction format Registers Addressing

How many and which The various types of data Instruction length in bits, Number of processor The mode or modes by
operations to provide and upon which operations number of addresses, size registers that can be which the address of an
how complex operations are performed of various fields, etc. referenced by operand is specified
should be instructions and their use
 Design Decisions (1)
Operation repertoire
How many ops?
What can they do?
How complex are they?
Data types
Instruction formats
Length of op code field
Number of addresses
 Design Decisions (2)
Registers
Number of CPU registers available
Which operations can be performed on which
registers?

RISC v CISC
RISC and CISC
 Overview
History of CISC and RISC
CISC and RISC
Philosophy
Attributes and disadvantages
Summation
 History of RISC/CISC
1950s IBM instituted a research program
1964 Release of System/360
Mid-1970s improved measurement tools demonstrated on CISC

1979 32-bit RISC microprocessor (801) developed led by Joel Birnbaum

1984 MIPS developed at Stanford, as well as projects done at Berkeley
1988 RISC processors had taken over high-end of the workstation market
Performance Optimization With Enhanced RISC)
architecture introduced w/ the RISC System/6k
AIM (Apple, IBM, Motorola) alliance formed, resulting in PowerPC
 Table 15.1
Characteristics of Some CISCs, RISCs, and Superscalar Processors

Complex Instruction Set Reduced Instruction

(CISC)Computer Set (RISC) Computer
Characteristic IBM VAX Intel SPARC MIPS
370/168 11/780 80486 R4000
Year developed 1973 1978 1989 1987 1991
Number of 208 303 235 69 94
instructions
Instruction size (bytes) 2 6 2 57 1 11 4 4
Addressing modes 4 22 11 1 1
Number of general- 16 16 8 40 - 520 32
purpose registers
Control memory size 420 480 246
(kbits)
Cache size (kB) 64 64 8 32 128
 Instruction High-level languages (HLLs)
Allow the programmer to express algorithms more
concisely
Execution Allow the compiler to take care of details that are not

algorithms

Characteristics Often support naturally the use of structured

programming and/or object-oriented design

Execution sequencing
Semantic gap
Determines the control and
pipeline organization The difference between the
operations provided in HLLs
and those provided in computer
architecture

Operands used
The types of operands and the
Operations performed
frequency of their use determine Determine the functions to be
the memory organization for performed by the processor and its
storing them and the addressing interaction with memory
modes for accessing them
 What is CISC?
CISC is an acronym for Complex Instruction Set Computer and are chips
that are easy to program and which make efficient use of memory. Since
the earliest machines were programmed in assembly language and memory
was slow and expensive, the CISC philosophy made sense, and was
commonly implemented in such large computers as the PDP-11 and the
DECsystem 10 and 20 machines.
Most common microprocessor designs such as the Intel 80x86 and
Motorola 68K series followed the CISC philosophy.
But recent changes in software and hardware technology have forced a re-
examination of CISC and many modern CISC processors are hybrids,
implementing many RISC principles.
CISC was developed to make compiler development simpler. It shifts most
of the burden of generating machine instructions to the processor. For
example, instead of having to make a compiler write long machine
instructions to calculate a square-root, a CISC processor would have a
built-in ability to do this.
 CISC Attributes
The design constraints that led to the development of CISC (small amounts
of slow memory and fact that most early machines were programmed in
assembly language) give CISC instructions sets some common
characteristics:
A 2-operand format, where instructions have a source and a destination.
Register to register, register to memory, and memory to register commands.
Multiple addressing modes for memory, including specialized modes for
indexing through arrays
Variable length instructions where the length often varies according to the
addressing mode
Instructions which require multiple clock cycles to execute.

E.g. Pentium is considered a modern CISC processor

Most CISC hardware architectures have several characteristics in
common:
Complex instruction-decoding logic, driven by the need for a
single instruction to support multiple addressing modes.
A small number of general purpose registers. This is the direct
result of having instructions which can operate directly on
memory and the limited amount of chip space not dedicated to
instruction decoding, execution, and microcode storage.
Several special purpose registers. Many CTSC designs set
aside special registers for the stack pointer, interrupt handling,
and so on. This can simplify the hardware design somewhat, at
the expense of making the instruction set more complex.
A 'Condition code" register which is set as a side-effect of
most instructions. This register reflects whether the result of
the last operation is less than, equal to, or greater than zero and
records if certain error conditions occur.
At the time of their initial development, CISC machines used
available technologies to optimize computer performance.
Microprograming is as easy as assembly language to
implement, and much less expensive than hardwiring a control
unit.
The ease of microcoding new instructions allowed designers to
make CISC machines upwardly compatible: a new computer
could run the same programs as earlier computers because the
new computer would contain a superset of the instructions of
the earlier computers.
As each instruction became more capable, fewer instructions
could be used to implement a given task. This made more
efficient use of the relatively slow main memory.
Because microprogram instruction sets can be written to match
the constructs of high-level languages, the compiler does not
have to be as complicated.
 CISC Disadvantages
Designers soon realized that the CISC philosophy had its own problems,
including:
Earlier generations of a processor family generally were contained as a
subset in every new version - so instruction set & chip hardware become
more complex with each generation of computers.
So that as many instructions as possible could be stored in memory with the
least possible wasted space, individual instructions could be of almost any
length - this means that different instructions will take different amounts of
clock time to execute, slowing down the overall performance of the
machine.
Many specialized instructions aren't used frequently enough to justify their
existence -approximately 20% of the available instructions are used in a
typical program.
CISC instructions typically set the condition codes as a side effect of the
instruction. Not only does setting the condition codes take time, but
programmers have to remember to examine the condition code bits before a
subsequent instruction changes them.
 What is RISC?
RISC?
RISC, or Reduced Instruction Set Computer. is a type of microprocessor
architecture that utilizes a small, highly-optimized set of instructions, rather than a
more specialized set of instructions often found in other types of architectures.
History
The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s
and early 80s. The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all
designed with a similar philosophy which has become known as RISC. Certain
design features have been characteristic of most RISC processors:
one cycle execution time: RISC processors have a CPI (clock per instruction) of one
cycle. This is due to the optimization of each instruction on the CPU and a technique
called PIPELINING
pipelining: a techique that allows for simultaneous execution of parts, or stages, of
instructions to more efficiently process instructions;
large number of registers: the RISC design philosophy generally incorporates a larger
number of registers to prevent in large amounts of interactions with memory
 Characteristics of Reduced
Instruction Set Architectures
One machine instruction Machine cycle --- the time it takes to fetch two operands
from registers, perform an ALU operation, and store the
per machine cycle result in a register

Only simple LOAD and STORE operations accessing

Register-to-register memory
operations This simplifies the instruction set and therefore the
control unit

Simple addressing Simplifies the instruction set and the control unit
modes

Generally only one or a few formats are used

Simple instruction Instruction length is fixed and aligned on word boundaries
formats Opcode decoding and register operand accessing can occur
simultaneously
 Implications
HLLs can best be supported by optimizing performance
of the most time-consuming features of typical HLL
programs
Three elements characterize RISC architectures:
Use a large number of registers or use a compiler to
optimize register usage
Careful attention needs to be paid to the design of
instruction pipelines
Instructions should have predictable costs and be
consistent with a high-performance implementation
 The Use of a Large Register
File
Software Solution Hardware Solution

Requires compiler to allocate More registers

registers
Thus more variables will be in
Allocates based on most used registers
variables in a given time

Requires sophisticated program

analysis
Parameter Local Temporary
Level J
Registers Registers Registers

Call/Return

Parameter Local Temporary

Level J + 1
Registers Registers Registers

Figure 15.1 Overlapping Register Windows

 8 16 16 16 8 4 16
Add B C A Load RB B
Memory to memory Load RC B
I = 56, D= 96, M = 152 Add R RB RC
A
Store R A
A
Register to memory
I = 104, D = 96, M = 200

(a) A B+C

8 16 16 16 8 4 4 4
Add B C A Add RA RB RC
Add A C B Add RB RA RC
Sub B D D Sub RD RD RB
Memory to memory Register to register
I = 168, D= 288, M = 456 I = 60, D = 0, M = 60

(b) A B + C; B A + C; D D B

I = number of bytes occupied by executed instructions

D = number of bytes occupied by data
M = total memory traffic = I + D

Figure 15.5 Two Comparisons of Register-to-Register and Memory-to-Memory Approaches

 RISC Attributes
The main characteristics of CISC microprocessors are:
Extensive instructions.
Complex and efficient machine instructions.
Microencoding of the machine instructions.
Extensive addressing capabilities for memory operations.
Relatively few registers.
In comparison, RISC processors are more or less the opposite of the above:
Reduced instruction set.
Less complex, simple instructions.
Hardwired control unit and machine instructions.
Few addressing schemes for memory operands with only two basic
instructions, LOAD and STORE
Many symmetric registers which are organized into a register file.
 Pipelining
RISC Pipelines
A RISC processor pipeline operates in much the same way, although the
stages in the pipeline are different. While different processors have
different numbers of steps, they are basically variations of these five,
used in the MIPS R3000 processor:
- fetch instructions from memory
- read registers and decode the instruction
- execute the instruction or calculate an address
- access an operand in data memory
- write the result into a register
 Pipelining Strategy

To apply this concept

to instruction
execution we must
Similar to the use of recognize that an
an assembly line in a instruction has a
manufacturing plant number of stages

New inputs are

accepted at one end
before previously
accepted inputs
appear as outputs at
the other end
Instruction Instruction Result
Fetch Execute

(a) Simplified view

Wait New address Wait

Instruction Instruction Result

Fetch Execute

Discard
(b) Expanded view

Figure 14.9 Two-Stage Instruction Pipeline

 Additional Stages
Fetch instruction (FI) Fetch operands (FO)
Read the next expected Fetch each operand from
instruction into a buffer memory
Decode instruction (DI) Operands in registers need not
Determine the opcode and
be fetched
the operand specifiers
Execute instruction (EI)
Calculate operands (CO)
Perform the indicated operation
Calculate the effective
address of each source and store the result, if any, in
operand the specified destination
This may involve operand location
displacement, register Write operand (WO)
indirect, indirect, or other Store the result in memory
forms of address calculation
 Time

1 2 3 4 5 6 7 8 9 10 11 12 13 14
Instruction 1 FI DI CO FO EI WO

Instruction 2 FI DI CO FO EI WO

Instruction 3 FI DI CO FO EI WO

Instruction 4 FI DI CO FO EI WO

Instruction 5 FI DI CO FO EI WO

Instruction 6 FI DI CO FO EI WO

Instruction 7 FI DI CO FO EI WO

Instruction 8 FI DI CO FO EI WO

Instruction 9 FI DI CO FO EI WO

Figure 14.10 Timing Diagram for Instruction Pipeline Operation

 RISC Disadvantages
There is still considerable controversy among experts about
the ultimate value of RISC architectures. Its proponents argue
that RISC machines are both cheaper and faster, and are
therefore the machines of the future.

However, by making the hardware simpler, RISC architectures

put a greater burden on the software. Is this worth the trouble
because conventional microprocessors are becoming
increasingly fast and cheap anyway?

Pipeline delays
 CISC versus RISC
CISC RISC

Emphasis on hardware Emphasis on software

Includes multi-clock Single-clock,
complex instructions reduced instruction only
Memory-to-memory: Register to register:
"LOAD" and "STORE" "LOAD" and "STORE"
incorporated in instructions are independent instructions
Small code sizes, Low cycles per second,
high cycles per second large code sizes
Transistors used for storing Spends more transistors
complex instructions on memory registers
 Summation
As memory speed increased, and high-level languages displaced assembly
language, the major reasons for CISC began to disappear, and computer
designers began to look at ways computer performance could be optimized
beyond just making faster hardware.
One of their key realizations was that a sequence of simple instructions
produces the same results as a sequence of complex instructions, but can be
implemented with a simpler (and faster) hardware design. (Assuming that
memory can keep up.) RISC (Reduced Instruction Set Computers)
processors were the result.
CISC and RISC implementations are becoming more and more alike. Many
chips. And today's CISC chips use many techniques formerly associated
with RISC chips.
To some extent, the argument is becoming moot because CISC and RISC
implementations are becoming more and more alike. Many of today's RISC
chips support as many instructions as yesterday's CISC chips. And today's
CISC chips use many techniques formerly associated with RISC chips.
 Modern Day Advancement
CISC and RISC Convergence

State of the art processor technology has changed significantly since RISC
chips were first introduced in the early '80s.

Because a number of advancements are used by both RISC and CISC

processors, the lines between the two architectures have begun to blur.

In fact, the two architectures almost seem to have adopted the strategies of
the other. Because processor speeds have increased, CISC chips are now
able to execute more than one instruction within a single clock.

This also allows CISC chips to make use of pipelining. With other
technological improvements, it is now possible to fit many more transistors
on a single chip.
This gives RISC processors enough space to incorporate more
complicated, CISC-like commands.

RISC chips also make use of more complicated hardware,

making use of extra function units for superscalar execution.

All of these factors have led some groups to argue that we are
now in a "post-RISC" era, in which the two styles have
become so similar that distinguishing between them is no
longer relevant.

However, it should be noted that RISC chips still retain some

important traits. RISC chips strictly utilize uniform, single-
cycle instructions. They also retain the register-to-register,
load/store architecture. And despite their extended instruction
sets, RISC chips still have a large number of general purpose
registers.
 Table 15.7
Characteristics of Some Processors

Number Number of
of Max Load/store Max bits for Number of
instruc- instruc- Number of combined number of Unaligned Max integer bits for FP
tion tion size addressing Indirect with memory addressing Number of register register
Processor sizes in bytes modes addressing arithmetic operands allowed MMU uses specifier specifier
AMD29000 1 4 1 no no 1 no 1 8 3
MIPS R2000 1 4 1 no no 1 no 1 5 4
SPARC 1 4 2 no no 1 no 1 5 4
MC88000 1 4 3 no no 1 no 1 5 4
HP PA 1 4 10 no no 1 no 1 5 4
IBM RT/PC 2 4 1 no no 1 no 1 4 3
IBM RS/6000 1 4 4 no no 1 yes 1 5 5
Intel i860 1 4 4 no no 1 no 1 5 4
IBM 3090 4 8 2 no yes 2 yes 4 4 2
Intel 80486 12 12 15 no yes 2 yes 4 3 3
NSC 32016 21 21 23 yes yes 2 yes 4 3 3
MC68040 11 22 44 yes yes 2 yes 8 4 3
VAX 56 56 22 yes yes 6 yes 24 4 0
Clipper 4 8 9 no no 1 0 2 4 3
Intel 80960 2 8 9 no no 1 yes 5 3

a RISC that does not conform to this characteristic. (Table can be found on page 554 in the
b CISC that does not conform to this characteristic. textbook.)
Thank you for your listening