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CPE440 - Computer Architecture - FA20 - S1 PDF

This document contains instructions and questions for a computer architecture exam. Question 1 involves calculating cache parameters like block offset bits, number of sets, set index bits, and tag bits for a given cache configuration and physical address. Question 2 asks students to compare two design alternatives for improving latency in a self-driving vehicle's sensor comparison unit: enhancing the hardware of the unit to speed it up by 12x, or making all comparison instructions run 1.8x faster.

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98 views1 page

CPE440 - Computer Architecture - FA20 - S1 PDF

This document contains instructions and questions for a computer architecture exam. Question 1 involves calculating cache parameters like block offset bits, number of sets, set index bits, and tag bits for a given cache configuration and physical address. Question 2 asks students to compare two design alternatives for improving latency in a self-driving vehicle's sensor comparison unit: enhancing the hardware of the unit to speed it up by 12x, or making all comparison instructions run 1.8x faster.

Uploaded by

Abdullah
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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COMSATS University Islamabad, Lahore Campus

□ Sessional - I □ Sessional – II □ Terminal Examination Fall 2020


Course Title: Computer Architecture Course Code: CPE440 Credit Hours: 4(3,1)
Course Dr. Muhammad Naeem Awais Programme Name: BS Computer Engineering
Semester: 7th Batch: FA-17 Section: Date:
Time Allowed: 60 Minutes Maximum Marks: 10
Student’s Name: Reg. No.
Important Instructions / Guidelines:
 Turn on your camera during exam.
 Write your Name and Student Registration Number clearly on the first page.
 Upload your question paper with the answer book on CUonline.

Question 1: (CLO3-C3) (5 marks)

The size of a fully set associative cache is 512 KB with a block size of 1 KB. For each block of main
memory, this fully set associative cache has 8 blocks in it. Assume the physical address generated by the
CPU is 0X 77CA46AC. Compute the followings:

a) Number of bits required for the cache block off-set field


b) Number of sets in the cache
c) Number of bits required for the cache set-index field
d) Number of bits required for the cache tag field
e) Address of the starting byte of the first word in the block

Question 2: (CLO4-C6) (5 Marks)

Self-driven vehicles have thousands of sensors installed on a single car. The latency of each sensor-based
operation can be very critical when it comes to taking the right decision. The brain of such a vehicle is a
fast speed processor. The processor design team are given a task to design a new comparator unit
(COMPU) that compares the values of 4 to 8 sensors at any given time with a latency of closer to zero.
Suppose the COMPU is responsible for 40% of the execution time of a critical benchmark. One proposal
is to enhance the COMPU hardware and speed up this operation by a factor of 12. The other alternative is
just to try to make all comparison instructions in the processor run faster by a factor of 1.8; comparison
instructions are responsible for half of the execution time for the application. The design team believes
that they can make all comparison instructions run 1.8 times faster with the same effort as required for the
COMPU unit. Compare the two design alternatives.

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