ODL SIMULATION MANUAL FOR

PHY340 ELECTRONICS
Semester March - July 2020

NAME : AISYAH BT MOHAMMAD ISHAM

NO ID: 2018446172

SIMULATION 1
BASIC LOGIC GATES

1.0 OBJECTIVE
To study the function of basic logic gates INVERTER, AND, OR and gate conversion using logic
circuit simulator and truth table representation.

4.0 RESULTS

Logic Gates Input Output

A B X
NOT 0 - 1
1 - 0
AND 0 0 0
0 1 0
1 0 0
1 1 1
OR 0 0 0
0 1 1
1 0 1
1 1 1
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Table 1.1

Figure Input Output

A B
0 0 0
1.2 0 1 1
1 0 1
1 1 1
0 0 0
1.3 0 1 0
1 0 0
1 1 1

Table 1.2
5.0 QUESTIONS

QUESTION
1. The output of an AND gate will be high if all of its inputs is/are high.
2. The output of an OR gate will be low if any of its inputs is/are high.
3. The logic equation for a 3-input AND gate shown below is X= A.B.C
4. The logic equation for a 4-input OR gate shown below is X= A.B.C.D
5. The output of the logic circuit shown below is X = A”’
6. The NAND is formed by inverting the inputs and output of an AND gate.
7. The NOR is formed by inverting the inputs and output of an OR gate.
8. The power supply voltage for TTL ICs is typically 5 volt(s).
9. Draw the outputs waveform of the gates shown below.

= 0011010
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= 01000001

END OF SIMULATION 1

SIMULATION 2
NAND AND NOR GATES

OBJECTIVE
To study the operation principles and methods of generating the NAND and NOR gates.

RESULTS

Logic Gate Input Output

A B X
NAND 0 0 1
0 1 1
1 0 1
1 1 0
NOR 0 0 1
0 1 0
1 0 0
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1 1 0

Table 2.1

Input Output
A B X
0 0 0
0 1 0
1 0 0
1 1 1

Table 2.2

Input Output
A B X
0 0 0
0 1 1
1 0 1
1 1 1

Table 2.3
5.0 QUESTIONS

1. Which logic gate can be used to replace the circuits as shown in Figure 2.3(a) and 2.3(b)?
o 2.3(a) can be replace by AND gate, while 2,3(b) by OR gate
2. The AND gate can be obtained by inverting the inputs of a NOR gate.
3. Inverting the output of a NOR gate will produce a/an OR gate.
4. Using logic diagram and Boolean expression, show how 2-input NAND gate can be used
as an inverter.

A B X
0 0 1
0 1 1
1 0 1
1 1 0
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Boolean expression, Q=A.B

Therefore, 2 input NAND gate can be used as an inverter.

5. Draw the output of the logic gate shown below

1101101
1111111
=0010010

6. Construct a 2-input NOR gate using only 2-input NAND gate(s).

7. Draw the electrical equivalent circuits for 2-input NAND gate and 2-input NOR gate.

2-inpur NAND gate

2-input NOR gate

END OF SIMULATION 2
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SIMULATION 3
BOOLEAN ALGEBRA

1.0 OBJECTIVE
To study the logic function of combined logic gates using De Morgan theorem and Boolean algebra
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Figure 3.1

Figure 3.2

1. Referring to Figure 3.1,

a) Write the output expression for gate A
X =A + B
b) Write the output expression for gate B
X =B+ C
c) Write the output expression for gate C
X =C ' + D

d) Write the output expression for gate D

X =( A + B ) .(B+ C)

e) Write the output expression for gate E

X =A ' . (C' + D)

f) Write the output expression for gate F

X =[ ( A + B ) . ( B+C ) ]+{ A ' .(C' + D) ¿

2. Compare the circuits in Figure 3.1 and Figure 3.2.

Circuit figure for 3.1 have four or gate while the circuit for 3.2 only have two or gate.
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Figure 3.5

Figure 3.6

7.

8. Do the circuits in Figure 3.5 and Figure 3.6 perform the same logic function? Explain your

NO, BECAUSE CIRCUIT IN FIGURE 3.5 USE AND GATE , NAND GATE AND OR GATE
WHILE THE CIRCUIT FOR FIGURE 3.6 USE AND GATE .NOR GATE AND OR GATE
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RESULTS

(a) (b)
INPUT OUTPUT INPUT OUTPUT
A B X A B X
0 0 1 0 0 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 1 1 0

Table 3.1

(a) (b)
INPUT OUTPUT INPUT OUTPUT
A B X A B X
0 0 1 0 0 1
1 0 0 1 0 0
0 1 0 0 1 0
1 1 0 1 1 0

Table 3.2

INPUT OUTPUT
A B C D X
0 0 0 0 1
0 1 1 1 0
0 0 1 1 0
0 0 0 1 0
1 1 1 0 1
1 1 0 0 1
1 0 0 0 1
1 0 1 0 0
0 1 0 1 0
0 1 1 0 0
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1 0 0 1 0
0 1 0 0 1
0 0 1 0 1
0 0 1 1 1
0 0 1 0 1
1 1 1 1 0
1
Table 3.3

INPUT OUTPUT
A B C D X
0 0 0 0 1
0 0 0 1 1
0 0 1 1 1
0 1 1 1 0
1 0 0 0 1
1 1 0 0 1
1 1 1 0 0
1 1 0 1 0
1 0 1 0 0
0 1 0 1 0
0 0 1 0 1
0 1 0 0 1
1 0 1 1 0
1 0 0 1 0
0 1 1 0 0
1 1 1 1 0

Table 3.4
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END OF SIMULATION 3 SIMULATION 4

FLIP-FLOPS

OBJECTIVE
To study the logic function of sequential flip-flops circuits using cross-coupled NOR gates and
cross-coupled NAND gates.

RESULTS

INPUT OUTPUT
SET RESET Q Q' STATUS (VALID/INVALID/NO CHANGE)
0 0 0 0 NO CHANGE
0 1 1 0 VALID
1 0 0 1 VALID
1 1 x x INVALID

Table 5.1

INPUT OUTPUT
SET RESET Q Q' STATUS (VALID/INVALID/NO CHANGE)
0 0 0 0 NO CHANGE
0 1 0 1 VALID
1 0 1 0 VALID
1 1 x x INVALID

Table 5.2

1. Discuss the operational logic function for both of the flip-flop circuits

This operational logic function for both of the flip-flop circuits are the SR flip-flop it also known as
a SR latch , it can be considered as one of the most basic sequential logic circuit possible. This
simple flip-flop is basically has two inputs, one which will “set” the device (meaning the output =
1), and is labelled s and one which will “reset” the device (meaning the output = 0), labelled r. The
SR stands for set-reset. Next, a basic NAND gate, SR flip flop can be designed by cross coupling of
two NAND gates. It is an active low input SR flip – flop, when both the set and reset inputs are
high, then the output remains in previous state it holds the previous data. Next, when set input is
high and reset input is low, then the flip flop will be in reset state. Because the low input of NAND
gate with r input drives the other NAND gate with 1, as its output is 1. So both the inputs of the
NAND gate with s input are 1. This will cause the output of the flip – flop to settle in reset state.
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Besides that, SR flip flop can also be designed by cross coupling of two NOR gates. It is an active
high input SR flip – flop, when both the SET and RESET inputs are low, then the output remains in
previous state i.e. it holds the previous data and it also when the set input is low and reset input is
high, then the flip flop will be in reset state. Because the high input of NOR gate with R input
drives the other NOR gate with 0, as its output is 0. So both the inputs of the NOR gate with S input
are 0. This will cause the output of the flip – flop to settle in reset state.

END OF SIMULATION 4