Fault Models PDF
Fault Models PDF
8
¨ Mask contamination
¨ Transistor stuck-on,
¨ Process variations stuck-open
¨ Defective oxide ¨ Resistive shorts and
opens
¨ Change in threshold
l Logical Effects voltage
¨ Logic s-a-0 or 1
¨ Slower transition (delay faults)
¨ AND-bridging, OR-bridging
VDD X
B
X
A Z
X
GND X X
lLogical
S-A-0
A
B X Z
B Faulty
F Good
Break
A=0
Stuck On
B=0
C=1
E=0
l Simplified Models
n Wired-AND, Wired-OR
l More Realistic Models:
n Bridge resistance
n Vth of successor gates
ECE 443 © Copyright 1998 Elizabeth M. Rudnick 12 University of Illinois
l Slow-to-rise (0 to 1) transition l Slow-to-fall (1 to 0) transition
Primary X
Inputs f fault
Primary
Outputs
s-a-0 0 0
e.g. F = ac + ab + bc Vdd
ECE 443 © Copyright 1998 Elizabeth M. Rudnick 20 University of Illinois
s-a -0 1/0 (a) Unobservable
x
1/Z (b) Uncontrollable
1 b
1/? a x
0 x x
Z
TriState Untestable
S-a-0
D
x
D
Sequentially Redundant
Clk
A
F
G
I
D E
C
B H
ECE 443 © Copyright 1998 Elizabeth M. Rudnick 25 University of Illinois
ALGORITHM:
x4 X
f
l Consider the fault f.
¨ Rewrite Z by cutting the wire at f as a 5-variable
function
s Z(x1, x2, x3, x4, f) = x1(x2+x3) + f
¨
DZ must be 1 for f to propagate to the output
df
¨ Also express f = F(x1, x2, x3, x4) = x1x4
¨ If f is stuck-at-0, the excitation requirement is
F(x1, x2, x3, x4) = 1
ECE 443 © Copyright 1998 Elizabeth M. Rudnick 32 University of Illinois
¨ If f is stuck-at-1 then F(x1, x2, x3, x4) = 0.
¨ Therefore, all test vectors are expressed by the
equation
DZ
s
df f = 1 for f stuck-at-0
s DZ f = 1 for f stuck-at-1
df
DZ
¨ df = x1(x2+x3) Å 1 = x1 + x2x3
¨ Tests for f stuck-at-0 are
s x1x4 [x1+x2x3)] = x1x4