724 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO.

4, AUGUST 2002

Multilevel Inverters: A Survey of Topologies,

Controls, and Applications
José Rodríguez, Senior Member, IEEE, Jih-Sheng Lai, Senior Member, IEEE, and
Fang Zheng Peng, Senior Member, IEEE

Abstract—Multilevel inverter technology has emerged re-

cently as a very important alternative in the area of high-power
medium-voltage energy control. This paper presents the most
important topologies like diode-clamped inverter (neutral-point
clamped), capacitor-clamped (flying capacitor), and cascaded
multicell with separate dc sources. Emerging topologies like
asymmetric hybrid cells and soft-switched multilevel inverters are
also discussed. This paper also presents the most relevant control
and modulation methods developed for this family of converters:
multilevel sinusoidal pulsewidth modulation, multilevel selective
harmonic elimination, and space-vector modulation. Special
attention is dedicated to the latest and more relevant applications
Fig. 1. One phase leg of an inverter with (a) two levels, (b) three levels, and
of these converters such as laminators, conveyor belts, and unified (c) n levels.
power-flow controllers. The need of an active front end at the
input side for those inverters supplying regenerative loads is also
discussed, and the circuit topology options are also presented. semiconductors is represented by an ideal switch with several
Finally, the peripherally developing areas such as high-voltage positions. A two-level inverter generates an output voltage
high-power devices and optical sensors and other opportunities with two values (levels) with respect to the negative terminal
for future development are addressed.
of the capacitor [see Fig. 1(a)], while the three-level inverter
Index Terms—Medium-voltage drives, multilevel converter, generates three voltages, and so on.
multilevel inverter, power converters. Considering that is the number of steps of the phase voltage
with respect to the negative terminal of the inverter, then the
I. INTRODUCTION number of steps in the voltage between two phases of the load
is

I N RECENT YEARS, industry has begun to demand higher

power equipment, which now reaches the megawatt level.
Controlled ac drives in the megawatt range are usually con-
(1)

nected to the medium-voltage network. Today, it is hard to con- and the number of steps in the phase voltage of a three-phase
nect a single power semiconductor switch directly to medium- load in wye connection is
voltage grids (2.3, 3.3, 4.16, or 6.9 kV). For these reasons, a (2)
new family of multilevel inverters has emerged as the solution
for working with higher voltage levels [1]–[3]. The term multilevel starts with the three-level inverter intro-
Multilevel inverters include an array of power semicon- duced by Nabae et al. [4]. By increasing the number of levels
ductors and capacitor voltage sources, the output of which in the inverter, the output voltages have more steps generating
generate voltages with stepped waveforms. The commutation a staircase waveform, which has a reduced harmonic distortion.
of the switches permits the addition of the capacitor voltages, However, a high number of levels increases the control com-
which reach high voltage at the output, while the power plexity and introduces voltage imbalance problems.
semiconductors must withstand only reduced voltages. Fig. 1 Three different topologies have been proposed for multilevel
shows a schematic diagram of one phase leg of inverters with inverters: diode-clamped (neutral-clamped) [4]; capac-
different numbers of levels, for which the action of the power itor-clamped (flying capacitors) [1], [5], [6]; and cascaded
multicell with separate dc sources [1], [7]–[9]. In addition, sev-
eral modulation and control strategies have been developed or
Manuscript received December 2002 ; revised April 2002. Abstract published adopted for multilevel inverters including the following: mul-
on the Internet May 16, 2002. This work was supported by the Chilean Research
Fund CONICYT under Grant 1990837, Grant 1010096, and Grant 7010096 and tilevel sinusoidal pulsewidth modulation (PWM), multilevel
by the University Federico Santa María. selective harmonic elimination, and space-vector modulation
J. Rodríguez is with the Departamento de Electronica, Universidad Técnica (SVM).
Federico Santa María, Valparaiso, Chile (e-mail: [email protected]).
J.-S. Lai is with Virginia Polytechnic Institute and State University, Blacks- The most attractive features of multilevel inverters are as fol-
burg, VA 24061-0111 USA. lows.
F. Z. Peng is with the Department of Electrical and Computer Engineering,
Michigan State University, East Lansing, MI 48826-1226 USA. 1) They can generate output voltages with extremely low
Publisher Item Identifier 10.1109/TIE.2002.801052. distortion and lower .
0278-0046/02$17.00 © 2002 IEEE
RODRÍGUEZ et al.: MULTILEVEL INVERTERS 725

2) They draw input current with very low distortion.

3) They generate smaller common-mode (CM) voltage, thus
reducing the stress in the motor bearings. In addition,
using sophisticated modulation methods, CM voltages
can be eliminated [8].
4) They can operate with a lower switching frequency.
The results of a patent search show that multilevel inverter
circuits have been around for more than 25 years. An early
traceable patent appeared in 1975 [9], in which the cascade
inverter was first defined with a format that connects separately
dc-sourced full-bridge cells in series to synthesize a staircase ac
output voltage. Through manipulation of the cascade inverter,
with diodes blocking the sources, the diode-clamped multilevel
inverter was then derived [10]. The diode-clamped inverter
was also called the neutral-point clamped (NPC) inverter Fig. 2. Diode-clamped multilevel inverter circuit topologies. (a) Three-level.
when it was first used in a three-level inverter in which the (b) Five-level.
mid-voltage level was defined as the neutral point. Because
the NPC inverter effectively doubles the device voltage level
without requiring precise voltage matching, the circuit topology the voltage sharing between and with blocking
prevailed in the 1980s. The application of the NPC inverter the voltage across and blocking the voltage across
and its extension to multilevel converter was found in [11]. . Notice that output voltage is ac, and is dc. The
Although the cascade inverter was invented earlier, its applica- difference between and is the voltage across , which
tions did not prevail until the mid–1990s. Two major patents is . If the output is removed out between a and 0, then
[12], [13] were filed to indicate the superiority of cascade the circuit becomes a dc/dc converter, which has three output
inverters for motor drive and utility applications. Due to the voltage levels: , , and 0.
great demand of medium-voltage high-power inverters, the Fig. 2(b) shows a five-level diode-clamped converter in which
cascade inverter has drawn tremendous interest ever since. the dc bus consists of four capacitors, , , , and . For
Several patents were found for the use of cascade inverters in dc-bus voltage , the voltage across each capacitor is ,
regenerative-type motor drive applications [14]–[16]. The last and each device voltage stress will be limited to one capacitor
entry for U.S. multilevel inverter patents, which were defined as voltage level through clamping diodes.
the capacitor-clamped multilevel inverters, came in the 1990s To explain how the staircase voltage is synthesized, the neu-
[17], [18]. Today, multilevel inverters are extensively used tral point n is considered as the output phase voltage reference
in high-power applications with medium voltage levels. The point. There are five switch combinations to synthesize five level
field applications include use in laminators, mills, conveyors, voltages across a and n.
pumps, fans, blowers, compressors, and so on. 1) For voltage level , turn on all upper switches
This paper presents state-of-the-art multilevel technology, – .
considering well-established and emerging topologies as well 2) For voltage level , turn on three upper
as their modulation and control techniques. Special attention switches – and one lower switch .
is dedicated to the latest and more relevant industrial applica- 3) For voltage level , turn on two upper switches
tions of these converters. Finally, the possibilities for future and and two lower switches and .
development are addressed. 4) For voltage level , turn on one upper
switch and three lower switches – .
II. INVERTER TOPOLOGIES 5) For voltage level , turn on all lower
switches – .
A. Diode-Clamped Inverter Four complementary switch pairs exist in each phase. The com-
A three-level diode-clamped inverter is shown in Fig. 2(a). In plementary switch pair is defined such that turning on one of
this circuit, the dc-bus voltage is split into three levels by two the switches will exclude the other from being turned on. In this
series-connected bulk capacitors, and . The middle point example, the four complementary pairs are ( ), ( ),
of the two capacitors n can be defined as the neutral point. The ( ), and ( ).
output voltage has three states: , 0, and . For Although each active switching device is only required to
voltage level , switches and need to be turned on; block a voltage level of , the clamping diodes
for , switches and need to be turned on; and for must have different voltage ratings for reverse voltage blocking.
the 0 level, and need to be turned on. Using of Fig. 2(b) as an example, when lower devices
The key components that distinguish this circuit from a are turned on, needs to block three capacitor voltages,
conventional two-level inverter are and . These two or . Similarly, and need to block , and
diodes clamp the switch voltage to half the level of the dc-bus needs to block . Assuming that each blocking diode
voltage. When both and turn on, the voltage across a voltage rating is the same as the active device voltage rating, the
and 0 is , i.e., . In this case, balances out number of diodes required for each phase will be
726 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 4, AUGUST 2002

c) , , , ( of upper ’s
of ’s of ’s of );
d) , , , ( of upper ’s
of ’s of );
e) , , , ( of ’s of
’s of of lower ’s); and
f) , , , ( of ’s of
of lower ’s).
4) For voltage level , there are three combi-
nations:
a) , , , ( of upper ’s
of ’s);
b) , , , ( of of
lower ’s); and
Fig. 3. Capacitor-clamped multilevel inverter circuit topologies. (a) c) , , , ( of ’s of
Three-level. (b) Five-level.
of lower ’s).
. This number represents a quadratic increase in . When 5) For voltage level , turn on all lower
is sufficiently high, the number of diodes required will make switches, – .
the system impractical to implement. If the inverter runs under In the preceding description, the capacitors with positive
PWM, the diode reverse recovery of these clamping diodes be- signs are in discharging mode, while those with negative
comes the major design challenge in high-voltage high-power sign are in charging mode. By proper selection of capacitor
applications. combinations, it is possible to balance the capacitor charge.
Similar to diode clamping, the capacitor clamping requires a
B. Capacitor-Clamped Inverter large number of bulk capacitors to clamp the voltage. Provided
Fig. 3 illustrates the fundamental building block of a that the voltage rating of each capacitor used is the same as that
phase-leg capacitor-clamped inverter. The circuit has been of the main power switch, an -level converter will require a
called the flying capacitor inverter [1], [5], [6] with independent total of clamping capacitors per phase
capacitors clamping the device voltage to one capacitor voltage leg in addition to main dc-bus capacitors.
level. The inverter in Fig. 3(a) provides a three-level output
across a and n, i.e., , 0, or . For voltage C. Cascaded Multicell Inverters
level , switches and need to be turned on; for A different converter topology is introduced here, which is
, switches and need to be turned on; and for based on the series connection of single-phase inverters with
the 0 level, either pair ( ) or ( ) needs to be turned separate dc sources [7]. Fig. 4 shows the power circuit for one
on. Clamping capacitor is charged when and are phase leg of a nine-level inverter with four cells in each phase.
turned on, and is discharged when and are turned on. The resulting phase voltage is synthesized by the addition of
The charge of can be balanced by proper selection of the the voltages generated by the different cells. Each single-phase
0-level switch combination. full-bridge inverter generates three voltages at the output: ,
The voltage synthesis in a five-level capacitor-clamped 0, and . This is made possible by connecting the capac-
converter has more flexibility than a diode-clamped converter. itors sequentially to the ac side via the four power switches.
Using Fig. 3(b) as the example, the voltage of the five-level The resulting output ac voltage swings from 4 to 4
phase-leg a output with respect to the neutral point n, , can with nine levels, and the staircase waveform is nearly sinusoidal,
be synthesized by the following switch combinations. even without filtering.
Another version of cascaded multilevel inverters using stan-
1) For voltage level , turn on all upper switches
dard three-phase two-level inverters has recently been proposed
– .
[8]. Its circuit, shown in Fig. 5, uses an output transformer to
2) For voltage level , there are three combina-
add the different voltages. In order for the inverter output volt-
tions: ages to be added up, the inverter outputs of the three modules
a) , , , ( of upper ’s need to be synchronized with a separation of 120 between
of ); each phase. For example, obtaining a three-level voltage be-
b) , , , ( of ’s of tween outputs a and b, the voltage is synthesized by
lower ’s); and . The phase between and is pro-
c) , , , ( of upper ’s vided by and through an isolated transformer. With three
of ’s of ’s). inverters synchronized, the voltages , , are
3) For voltage level , there are six combinations: all in phase; thus, the output level is simply tripled.
a) , , , ( of upper ’s
of ’s); D. Generalized Multilevel Cells
b) , , , ( of of A generalized multilevel inverter topology has previously
lower ); been presented [19]. The existing multilevel inverters such as
RODRÍGUEZ et al.: MULTILEVEL INVERTERS 727

Fig. 6. Generalized P2 multilevel inverter structure.

Fig. 4. Cascaded inverter circuit topology and its associated waveform.

Fig. 7. Application example: a four-level P2 converter for the dual-voltage

system in automobiles.

E. Emerging Multilevel Inverter Topologies

Fig. 5. Cascaded inverter with three-phase cells.
1) Mixed-Level Hybrid Multilevel Cells: For high-voltage
high-power applications, it is possible to adopt multilevel
diode-clamped and capacitor-clamped multilevel inverters can diode-clamped or capacitor-clamped inverters to replace the
be derived from this generalized inverter topology. Moreover, full-bridge cell in a cascaded inverter [20]. The reason for
the generalized multilevel inverter topology can balance each doing so is to reduce the amount of separate dc sources. The
voltage level by itself regardless of load characteristics. There- nine-level cascaded inverter shown in Fig. 4 requires four sepa-
fore, the generalized multilevel inverter topology provides a rate dc sources for one phase leg and twelve for a three-phase
true multilevel structure that can balance each dc voltage level inverter. If a three-level inverter replaces the full-bridge cell,
automatically at any number of levels, regardless of active or the voltage level is effectively doubled for each cell. Thus, to
reactive power conversion, and without any assistance from achieve the same nine voltage levels for each phase, only two
other circuits. Thus, in principle, it provides a complete multi- separate dc sources are needed for one phase leg and six for a
level topology that embraces the existing multilevel inverters. three-phase inverter. The configuration can be considered as
Fig. 6 shows the P2 multilevel inverter structure per phase leg. having mixed-level hybrid multilevel cells because it embeds
Each switching device, diode, or capacitor’s voltage is 1 , i.e., multilevel cells as the building block of the cascaded inverter.
of the dc-link voltage. Any inverter with any number Fig. 8 shows the nine-level cascaded inverter incorporating a
of levels, including the conventional two-level inverter can be three-level capacitor-clamped inverter as the cell. It is obvious
obtained using this generalized topology. that a diode-clamped inverter can replace the capacitor-clamped
As an application example, a four-level bidirectional dc/dc inverter to be a mixed-level hybrid multilevel cell.
converter, shown in Fig. 7, is suitable for the dual-voltage 2) Asymmetric Hybrid Multilevel Cells: In previous de-
system to be adopted in future automobiles. The four-level scriptions, the voltage levels of the cascade inverter cells equal
dc/dc converter has a unique feature, which is that no magnetic each other. However, it is possible to have different voltage
components are needed. From this generalized multilevel levels among the cells [21], [22], and the circuit can be called as
inverter topology, several new multilevel inverter structures can asymmetric hybrid multilevel inverter. Fig. 9 shows an example
be derived [19]. of having two separate dc-bus levels, one with , and the
728 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 4, AUGUST 2002

Fig. 10. Asymmetric cascade inverter cell arrangement with different

switching frequencies.

Fig. 8. A mixed-level hybrid cell configuration using the thee-level

diode-clamped inverter as the cascaded inverter cell to increase the voltage
levels.

Fig. 11. Zero-voltage-switching capacitor-clamped inverter circuit.

at all different from that of conventional two-level inverters. For

capacitor- or diode-clamped inverters, however, the choices of
soft-switching circuit can be found with different circuit combi-
nations [23]–[29]. Although zero-current switching is possible
[30], most literatures proposed zero-voltage-switching types in-
cluding auxiliary resonant commutated pole (ARCP), coupled
Fig. 9. Asymmetric hybrid cascaded inverter cell arrangement with different inductor with zero-voltage transition (ZVT), and their combi-
voltage levels.
nations. Fig. 11 shows an example of combining the ARCP
and coupled-inductor ZVT techniques for a capacitor-clamped
other with . Depending on the availability of dc sources, three-level inverter.
the voltage levels are not limited to a specific ratio. This feature The auxiliary switches , , , and are used
allows more levels to be created in the output voltage, and to assist the inner main switches and to achieve soft
thus reduces the harmonic contents with less cascaded cells switching. With as the coupled inductor, the bridge-type
required. circuit formed by , , , and forms a two-level
Even with the same voltage level among them, it is also pos- coupled-inductor ZVT. The basic principle of a two-level ZVT
sible to use high-frequency PWM for one cell, while the other can be found in [31]–[35]. For the outer main switches, the soft
switches at a lower rate. Fig. 10 shows an example with two dif- switching relies on and , , , , , coupled
ferent devices. The top full-bridge cell uses the insulated gate inductor , and split-capacitor pair to form an ARCP
bipolar transistor (IGBT), and the low cell uses the gate-turn-off type soft-switching inverter. Detailed soft-switching circuit
thyristor (GTO) as its switching device. The GTO-based cell operation for inner devices and outer devices can be found in
switches at a lower frequency, typically the fundamental fre- [24], [26].
quency, and the IGBT-based cell switches at a PWM frequency
to smooth the waveform [21], [22]. III. CONTROL AND MODULATION STRATEGIES
3) Soft-Switched Multilevel Inverters: There are numerous
ways of implementing soft-switching methods to reduce the A. Classification of Modulation Strategies
switching loss and to increase efficiency for different multilevel The modulation methods used in multilevel inverters can be
inverters. For the cascaded inverter, because each inverter cell is classified according to switching frequency, as shown in Fig. 12
a two-level circuit, the implementation of soft switching is not [36], [37]. Methods that work with high switching frequencies
RODRÍGUEZ et al.: MULTILEVEL INVERTERS 729

Fig. 12. Classification of multilevel modulation methods.

have many commutations for the power semiconductors in

one period of the fundamental output voltage. A very popular
method in industrial applications is the classic carrier-based si-
nusoidal PWM (SPWM) that uses the phase-shifting technique Fig. 13. Inverter cell voltages. (a) Output voltage and reference with SPWM.
to reduce the harmonics in the load voltage [7], [38], [39]. (b) Output voltage and reference with injection of sinusoidal third harmonic.
Another interesting alternative is the SVM strategy, which has
been used in three-level inverters [36].
Methods that work with low switching frequencies generally
perform one or two commutations of the power semiconduc-
tors during one cycle of the output voltages, generating a stair-
case waveform. Representatives of this family are the multilevel
selective harmonic elimination [40], [41] and the space-vector
control (SVC) [42].

B. Multilevel SPWM
Several multicarrier techniques have been developed to re-
duce the distortion in multilevel inverters, based on the classical
SPWM with triangular carriers. Some methods use carrier dis-
position and others use phase shifting of multiple carrier signals
[38], [43], [44]. Fig. 13(a) shows the typical voltage generated
by one cell for the inverter shown in Fig. 4 by comparing a si-
nusoidal reference with a triangular carrier signal.
A number of –cascaded cells in one phase with their car-
riers shifted by an angle and using the same
Fig. 14. Total voltage of three cells in series connection for different phase
control voltage produce a load voltage with the smallest dis- displacement in the carriers.
tortion. The effect of this carrier phase-shifting technique can
be clearly observed in Fig. 14. This result has been obtained
grams are universal regardless of the type of multilevel inverter.
for the multi-cell inverter in a seven-level configuration, which
In other words, Fig. 15(c) is valid for five-level diode-clamped,
uses three series-connected cells in each phase. The smallest dis-
capacitor-clamped, or cascaded inverter. The adjacent three vec-
tortion is obtained when the carriers are shifted by an angle of
tors can synthesize a desired voltage vector by computing the
.
duty cycle ( , , and ) for each vector
A very common practice in industrial applications for the
multilevel inverter is the injection of a third harmonic in each
(3)
cell, as shown in Fig. 13(b), to increase the output voltage [7],
[20]. Another advantageous feature of multilevel SPWM is that Space-vector PWM methods generally have the following fea-
the effective switching frequency of the load voltage is times tures: good utilization of dc-link voltage, low current ripple, and
the switching frequency of each cell, as determined by its car- relatively easy hardware implementation by a digital signal pro-
rier signal. This property allows a reduction in the switching cessor (DSP). These features make it suitable for high-voltage
frequency of each cell, thus reducing the switching losses. high-power applications.
As the number of levels increases, redundant switching states
C. SVM and the complexity of selecting switching states increase dra-
The SVM technique can be easily extended to all multilevel matically. Some authors have used decomposition of the five-
inverters [45]–[51]. Fig. 15 shows space vectors for the tradi- level space-vector diagram into two three-level space-vector di-
tional two-, three-, and five-level inverters. These vector dia- agrams with a phase shift to minimize ripples and simplify con-
730 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 4, AUGUST 2002

Fig. 16. Generalized stepped-voltage waveform.

contents can be removed from the voltage waveform. In gen-

eral, the most significant low-frequency harmonics are chosen
for elimination by properly selecting angles among different-
level inverters, and high-frequency harmonic components can
be readily removed by using additional filter circuits. According
to (4), to keep the number of eliminated harmonics at a con-
stant level, all switching angles must be less than . How-
ever, if the switching angles do not satisfy the condition, this
scheme no longer exists. As a result, this modulation strategy
basically provides a narrow range of modulation index, which
is its main disadvantage. For example, in a seven-level equally
stepped waveform, its modulation index is only available from
0.5 to 1.05. At modulation indexes lower than 0.5, if this scheme
is still applied, the allowable harmonic components to be elim-
inated will reduce from 2 to 1. The total harmonic distortion
(THD) increases correspondingly.
In order to achieve a wide range of modulation indexes with
minimized THD for the synthesized waveforms, a generalized
selected harmonic modulation scheme was proposed [40], [41].
The method can be illustrated by Fig. 17, in which the positive
Fig. 15. Space-vector diagram: (a) two-level, (b) three-level, and (c) five-level half-cycle of seven-level stepped waveforms are shown with dif-
inverter. ferent modulation index levels. In this case, the range of mod-
ulation indices can be divided into three levels, such as high,
trol [48]. Additionally, a simple space-vector selection method middle, and low. An output waveform with a high modulation
was introduced without duty cycle computation of the adjacent index level is shown in Fig. 17(a). Whenever is greater than
three vectors [37]. , this waveform no longer exists. Therefore, an output wave-
form shown in Fig. 17(b), which gives middle modulation index
level, will be applied instead. When the switching angles to
D. Selective Harmonic Elimination
in Fig. 17(b) are not converged at a low modulation index
Fig. 16 shows a generalized quarter-wave symmetric stepped- level, the output waveform shown in Fig. 17(c) will replace it.
voltage waveform synthesized by a -level inverter, In general, a stepped waveform, which comprises switching
where is the number of switching angles. By applying Fourier angles, can be divided into modulation index levels. By using
series analysis, the amplitude of any odd harmonic of the this technique, low switching frequencies with minimized har-
stepped waveform can be expressed as (4), whereas the ampli- monics in the output waveforms can be achieved with wide mod-
tudes of all even harmonics are zero ulation indexes.
Through mathematical manipulation and observation of
Fig. 17(a)–(c), a generalized harmonic expression for multi-
(4)
level stepped voltage has been derived [41] and is expressed as
the following equation:
where is the level of dc voltage, is an odd harmonic
order, is the number of switching angles, and is the th
switching angle. According to Fig. 16, to must satisfy (5)
.
To minimize harmonic distortion and to achieve adjustable In this expression, the positive sign implies the rising edge, and
amplitude of the fundamental component, up to harmonic the negative sign implies the falling edge.
RODRÍGUEZ et al.: MULTILEVEL INVERTERS 731

Fig. 18. Load voltage space vectors generated by an 11-level inverter.

Fig. 17. A positive half-cycle of a seven-level stepped waveform with different

modulation indexes. (a) High modulation index. (b) Middle modulation index.
(c) Low modulation index.

E. SVC
A conceptually different control method for multilevel
inverters, based on the space-vector theory, has been intro-
duced [37]. This control strategy, called SVC, works with low
switching frequencies and does not generate the mean value of
the desired load voltage in every switching interval, as is the
principle of SVM.
Fig. 18 shows the 311 different space vectors generated by an
11-level inverter. The reference load voltage vector is also
included in this figure. The main idea in SVC is to deliver to
the load a voltage vector that minimizes the space error or dis-
tance to the reference vector . The high density of vectors Fig. 19. Voltages generated by an 11-level inverter with SVC. (a) One-cell
voltage. (b) Resulting load voltage.
produced by the 11-level inverter (see Fig. 18.) will generate
only small errors in relation to the reference vector; it is, there-
F. Direct Torque Control (DTC)
fore, unnecessary to use a more complex modulation scheme
involving the three vectors adjacent to the reference. The DTC technique has been developed for low-voltage two-
The shaded hexagon of Fig. 18 shows the boundary of highest level inverters as an alternative to the field oriented method to
proximity, which means that when the reference voltage is effectively control torque and flux in ac drives [52]. DTC and
located in this area, vector must be selected, because it has hysteresis current control techniques have also been applied in
the greatest proximity to the reference. multilevel inverters [53]. It must be noticed that one major man-
Fig. 19(a) presents the voltage generated by one cell in an ufacturer has been selling medium-voltage three-level diode-
eleven-level multicell inverter with five cells per phase and an clamped inverters controlled with DTC [54].
output frequency of 50 Hz. The load voltage of the inverter
for the same frequency and modulation index 0.99 is shown in G. Capacitor Balancing Techniques
Fig. 19(b). In [55], the voltage unbalancing problem and the mechanism
Finally, Fig. 20 shows the reference vector and the vectors of the diode-clamped multilevel inverter were discussed. The
generated by the inverter using SVC [37]. This method is simple paper demonstrated that the diode-clamped multilevel inverter
and attractive for high number of levels. As the number of levels could not have balanced voltages for real power conversion
decreases, the error in terms of the generated vectors with re- without sacrificing output voltage performance. Thus, the
spect to the reference will be higher; this will increase the load paper proposed that the diode-clamped multilevel inverter be
current ripple. applied to reactive and harmonic compensation without voltage
732 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 4, AUGUST 2002

Fig. 20. Reference and output voltage vectors in an 11-level inverter with Fig. 21. Control diagram of the 11-level cascaded inverter.
SVC.

balancing problem. Reference [56] suggested that the voltage

unbalance problem could be solved by using a back-to-back
rectifier/inverter system and proper voltage balancing control.
Other papers [57]–[59] suggested the use of additional voltage
balancing circuits, such dc chopper, etc.
The capacitor-clamped structure was originally proposed for
high-voltage dc/dc conversions [60]. It is easy to balance the
voltages for such applications because the load current is dc.
For the capacitor-clamped multilevel inverter, voltage balancing
is relatively complicated [60], [61]. It has been shown theoret-
ically that the capacitor-clamped inverter cannot have self-bal-
anced voltage when applied to power conversion in which no
real power is involved, such as reactive power compensation.
However, since each phase leg has its own floating capacitors
that handle the phase current, the voltage balancing and ripple Fig. 22. Vienna rectifier phase-leg structure.
become troublesome.
The cascaded multilevel inverter was first introduced for
motor drive applications, in which an isolated and separate IV. INDUSTRIAL APPLICATIONS AND TECHNOLOGICAL
dc source is needed for each H-bridge unit [7]. However, ASPECTS
another paper presented the idea of using cascade multilevel A. Multilevel Rectifier
inverter for reactive and harmonic compensation, from which
Traditionally, multipulse rectifiers have been used for the re-
isolated dc sources can be omitted [56]. Additional work
duction of harmonics in the line current. These multipulse (12-
further demonstrated that the cascaded inverter is suitable for
pulse, 18-pulse, and so on) rectifiers use transformers for phase
universal power conditioning of power systems, especially
shifting in order to eliminate harmonics. To eliminate the phase-
for medium-voltage systems [62], [63]. The inverter provides
shift transformers, multilevel rectifiers have been proposed.
lower costs, higher performance, less electromagnetic interfer-
For those applications that require no regenerative capability,
ence (EMI), and higher efficiency than the traditional PWM
simplified (or reduced) multilevel rectifiers have been proposed
inverter for power line conditioning applications, both series
in [64]. This specific rectifier, named the Vienna rectifier, has
and parallel compensation. Although the cascaded inverter has
been used for telecommunication power supplies. Fig. 22 shows
an inherent self-balancing characteristic, because of the circuit
the per-phase leg structure for a three-level Vienna rectifier.
component losses and limited controller resolution, a slight
Some reduced-parts-count multilevel rectifiers for the number
voltage imbalance can occur. A simple control scheme, which
more than three levels have been proposed [65].
ensures dc voltage balance, has been proposed for reactive and
harmonic compensation [56]. Fig. 21 shows its control block
diagram that contains a proportional–integral (PI) regulator to B. DC/DC Converters
adjust the trigger angle and to ensure zero steady-state error The phase voltage of a multilevel diode-clamped or capac-
between the reference dc voltage and the dc-bus voltage. itor-clamped inverter resembles that of a full-bridge phase-shift-
RODRÍGUEZ et al.: MULTILEVEL INVERTERS 733

Fig. 24. Three-level diode-clamped inverter with 12-pulse input rectifier.

Fig. 23. Three-level capacitor-clamped inverter for dc–dc converter

application. (a) Circuit diagram. (b) Gating and output waveforms.

modulated dc/dc converter [66]. Fig. 23(a) shows a three-level

dc/dc converter based on a capacitor-clamped inverter circuit
along with diode clamping to ensure neutral-point voltage bal-
ance [67], [68]. The same as the capacitor-clamped inverter, this
converter only allows certain switch pairs to be turned on simul-
taneously. The switch pair { } yields ,{ }
Fig. 25. Three-level capacitor-clamped inverter with 18-pulse input rectifier.
yields , and { } and { } yield zero output.
By applying gate pulses sequentially, as shown in Fig. 23(b), a
three-level output voltage across the transformer primary can be
obtained. With phase-shift operation, this circuit operates inher-
ently under the soft-switching condition.

C. Large Motor Drives With Nonregenerative Front Ends

Diode-clamped three-level inverters are now widely applied
in medium-voltage (2.3, 3.3, 4.16, and even 6 kV) applications,
using an IGBT with forced-air cooling. These applications
cover a wide range of high-power loads including fans, pumps,
blowers, compressors, and conveyors.
An important issue in the application of these inverters is
the injection of current harmonics into the power supply due
to both the high power of the drive and the capacitive filters in
the dc link, which increase the distortion of the input current. A
Fig. 26. Seven-level cascaded inverter with nonregenerative rectifier.
12-pulse configuration of the input rectifier, as shown in Fig. 24,
is a standard solution for reducing the input current harmonics.
Some manufacturers include an 18-pulse and 24-pulse rectifier phase diode rectifier, which does not allow the regeneration of
to improve the quality of the input current. power. Table I presents the number of cells used in each phase
Fig. 25 presents a three-level inverter with capacitor-clamped for different motor voltages, as reported by one manufacturer
topology and 18-pulse configuration of the input rectifier [69]. [7].
The secondary voltages are shifted by 20 from each other. With The high quality of the input current assures compliance with
this type of input rectifier, the harmonics in the input currents are IEEE Standard 519–1992. In the case of 4.16-kV inverters with
drastically reduced, achieving a THD of less than 1.55% [69]. five cells per phase, the quality of the output voltage is very high
Fig. 26 shows a seven-level cascade multicell inverter used in with a voltage distortion THD of 10%. In this 11-level inverter,
nonregenerative drives for 2.3-kV networks. This inverter uses the input current of the inverter has a 30-pulse waveform and a
three cells in each phase. The input part of each cell has a three- THD of 1 [7].
734 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 4, AUGUST 2002

TABLE I The regenerative block shown in Fig. 29 has limited ca-

CASCADED INVERTERS USED IN MEDIUM-VOLTAGE DRIVES [7] pability because the active filter is normally designed with
a smaller power rating. In certain applications in which the
regenerative block also needs rated capability, the circuit shown
in Fig. 29 would not be applicable. A more general-purpose
regenerative four-quadrant-type configuration is shown in
Fig. 30 [16]. In this circuit, each power module contains an
AFE converter and a full-bridge inverter. The AFE converter
corrects the power factor and eliminates the harmonics, thus,
the transformer can be designed in a conventional way, similar
to the one shown in Fig. 29. It allows all the regenerative power
D. Large Motor Drives With Regenerative Front Ends to be pumped back to the source because the AFE converter
The use of a three-level active front end (AFE) at the input needs to be designed with full power rating. The only drawback
side of a three-level diode-clamped inverter has become a to this AFE-based cascaded inverter is that it requires high
very popular solution for high-power regenerative loads. This number of devices. The use of single-phase AFEs at the line
solution, presented in Fig. 27, allows the regeneration of full side of each cell has been considered as an alternative to spare
motor power with reduced harmonics and high power factor. power semiconductors [72]. However, this circuit imposes re-
Drives with three-level AFE are used in laminators [70], strictions to the number of cells that can be connected in series
high-power downhill conveyors [71], and other regenerative to eliminate low-frequency harmonics in the input current.
high-power loads.
A very interesting application of this technology in which two E. Applications in Power Systems
three-level AFEs are used in a so-called tandem configuration When the number of levels is greater than three, both the
is shown in Fig. 28 [71]. This drive uses GTO technology and, diode-clamped and cascaded multilevel inverters have equiv-
for this reason, an operation with low switching frequency is alently separate dc sources for each level in order to enable
highly desirable. The selective harmonic-elimination method is power conversion involving real power such as in motor drives
used with three commutation angles ( , , and ) in each [11], [57]. However, as mentioned previously, both inverters
AFE in order to eliminate harmonics 11 and 13. The equations have a perfect niche in harmonic and reactive power compen-
to achieve this purpose are sation [55], [62], [63]. The capacitor-clamped inverter cannot
have balanced voltage for power conversion involving only re-
active power [61], thus, it is not suited for reactive power com-
(6) pensation.
The first unified power-flow controller (UPFC) in the world
was based on a diode-clamped three-level inverter [73]. The
(7) UPFC is comprised of the back-to-back connection of two iden-
tical GTO thyristor-based three-level converters, each rated at
160 MVA; it was commissioned in mid-1998 at the Inez Sta-
(8) tion of American Electric Power (AEP) in Kentucky for voltage
support and power-flow control. Fig. 31 shows the system con-
where is the modulation index and is the voltage in each figuration.
dc-link capacitor. On the other hand, the cascaded multilevel inverter is best
The wye–wye and wye–delta connection in the input trans- suited for harmonic/reactive compensation and other utility
formers produces a 30 displacement in the input voltages of the applications [13], [62], [63], since each H-bridge inverter unit
AFEs, eliminating all harmonics of order odd : can balance its dc voltage without requiring additional isolated
5, 7, 17, 19, 29, and 31. In this way, the first harmonics are of power sources. GEC Alsthom T&D has commercialized the
the order 23 and 25. An important reduction of the input current cascaded multilevel inverter for reactive power compensa-
harmonics, working with a very low switching frequency, is ob- tion/generation (STATCOM) [74].
tained with this method.
Although this multipulse transformer allows the
V. FUTURE TRENDS
phase-shifted currents to be summed together for a near
sinusoidal input current, the major difficulty is the design of By looking at the number of papers published in recent
the transformer. With irrational turns ratios, it is possible to years, it is easy to conclude that multilevel inverter research and
produce undesirable interharmonic contents. Fig. 29 shows a development activities are experiencing an explosive rate of
solution using an active filter circuit as the regenerative front growth. A trend of having more and more multilevel inverters
end [14]. In this circuit, the transformer does not need to have is obvious. Although this paper has focused on multilevel in-
irrational turns ratios because the secondary winding current verter circuit topology, control, and applications, there is other
is compensated by an active filter. The active filter also allows research and development in related areas, such as high-voltage
power flow to be reversed, which solves the problem found in high-power semiconductor devices, sensors, high-speed DSPs,
Fig. 26. thermal management, and packaging. It is difficult to include
RODRÍGUEZ et al.: MULTILEVEL INVERTERS 735

Fig. 27. Three-level AFE and inverter.

Fig. 28. Two parallel-connected three-level AFEs.

Fig. 30. Cascaded regenerative inverter with three-phase AFEs.

Fig. 29. Cascaded multicell inverter regenerative blocks.

all the related technologies in one paper; however, those

technologies related to multilevel inverter development should
not be neglected from the ongoing development. Based on
the progress of semiconductor devices and advanced circuit
topologies, future trends can be observed in the following areas. Fig. 31. System configuration of the UPFC installed at Inez.
736 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 4, AUGUST 2002

A. Applications for Distribution Voltage Level configured with a separate source connected through the power
There is a strong demand to push voltage-source inverters conversion circuits used as an energy module or building block
(VSIs) into distribution voltage level, which is between 11–16 to provide individual output. A cascaded inverter can then be
kV, or typically 13.8 kV. Currently, the power electronics for dis- configured with multiple modules. Such a system does not need
tribution and transmission voltage levels are mainly dominated a transformer to provide isolation, and the system can be con-
by current source converters, which use thyristor devices with structed in a cost effective manner.
built-in reverse voltage blocking capability. The main problems
with thyristors are their sluggish switching speeds and their in- VI. CONCLUSION
ability to gate off. With the use of gate-turn-off high-voltage This paper has provided a brief summary of multilevel
semiconductor devices in multilevel inverters, the widespread inverter circuit topologies and their control strategies. Dif-
use of VSIs in distribution voltage level can be easily expected. ferent applications using different inverter circuits were also
discussed. As mentioned in Section I, an early patent for the
B. Advanced High-Voltage High-Power Semiconductor
cascaded multilevel inverter can be traced back to 1975. How-
Devices
ever, the commercial products that utilize this superior circuit
The availability of higher-voltage devices allows higher topology were not available until the mid-1990s. Today, more
operating voltages with fewer inverter levels. The major and more commercial products are based on the multilevel
contenders in the device arena are integrated-gate-commutated inverter structure, and more and more worldwide research
thyristor (IGCT) [75], [76], 3.3- and 6.5-kV high-voltage IGBT and development of multilevel inverter-related technologies is
(HV-IGBT) [77], and emitter turn-off (ETO) thyristor [78]. As occurring. This paper cannot cover or reference all the related
power level increased with new devices, the multilevel inverter work, but the fundamental principle of different multilevel
power-handling capability is also proportionally increased. inverters has been introduced systematically. The intention of
With the use of these high voltage devices, an inverter can easily the authors was simply to provide groundwork to readers in-
achieve 5 MW with only three levels required. The application terested in looking back on the evolution of multilevel inverter
to the distribution voltage level can be achieved with less than technologies, and to consider where to go from here.
five levels when the above-mentioned high-voltage devices are
used.
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[66] R. Redl, L. Balogh, and N. O. Sokal, “A novel soft-switching full-bridge Jih-Sheng (Jason) Lai (S’84–M’87–SM’93)
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high input voltage: four switches with peak voltage of V in=2, capacitive a grant from his college and a fellowship from the
turn-off snubber, and zero-voltage turn-on,” in Proc. IEEE PESC’98, National Science Council to study abroad. In 1986,
Fukuoka, Japan, May 1998, pp. 1–7. he became a staff member at the University of
[69] G. Beinhold, R. Jakob, and M. Nahrstaedt, “A new range of medium Tennessee, where he taught control systems and energy conversion courses. In
voltage multilevel inverter drives with floating capacitor technology,” 1989, he joined the Electric Power Research Institute (EPRI) Power Electronics
in Proc. 9th European Conf. Power Electronics (EPE), Graz, Austria, Applications Center (PEAC), where he managed EPRI-sponsored power elec-
2001, CD-ROM. tronics research projects. In 1993, he joined Oak Ridge National Laboratory
[70] M. Koyama, Y. Shimomura, H. Yamaguchi, M. Mukunoki, H. Okayama, as the Power Electronics Lead Scientist, where he initiated a high-power elec-
and S. Mizoguchi, “Large capacity high efficiency three-level GCT in- tronics program and developed several novel high-power converters including
verter system for steel rolling mill drives,” in Proc. 9th European Conf. multilevel converters and auxiliary-resonant-snubber-based soft-switching
Power Electronics (EPE), Graz, Austria, 2001, CD-ROM. inverters. Since August 1996, he has been with Virginia Polytechnic Institute
[71] J. Rodríguez, J. Pontt, G. Alzamora, N. Becker, O. Einenkel, J. L. and State University, Blacksburg, as an Associate Professor. His main research
Cornet, and A. Weinstein, “Novel 20 MW Downhill Conveyor System areas are in high-power electronics converter topologies, motor drives, and
Using Three-Level Converters,” in Conf. Rec. IEEE-IAS Annu. Meeting, utility power electronics interface and application issues. He has authored more
Chicago, IL, Oct. 2001, CD-ROM. than 100 published technical papers and two books. He is the holder of eight
[72] J. Rodríguez, L. Morán, A. González, and C. Silva, “High voltage mul- U.S. patents in the area of high power electronics and their applications. He
tilevel converter with regeneration capability,” in Proc. IEEE PESC’99, chaired the Technical Committee for the 2001 DOE Future Energy Challenge.
Charleston, SC, June 1999, pp. 1077–1082. Dr. Lai is the Chairman of the IEEE Power Electronics Society Standards
[73] B. A. Renz et al., “AEP unified power flow controller performance,” Committee. He is a member of Phi Kappa Phi and Eta Kappa Nu. He was the re-
presented at the IEEE/PES Winter Meeting, Tampa, FL, 1998, Paper cipient of several distinctive awards, including a Technical Achievement Award
PE-042-PWRD-0-12. at Lockheed Martin Award Night, two Conference Paper Awards from the In-
[74] “STATCOM …power electronics on the move,” GEC Alstom T&D, dustrial Power Converter Committee of the IEEE Industry Applications Society,
Villeurbanne, France, brochure, 1998. one IEEE IECON Best Paper Award, and an Advanced Technology Award from
[75] P. K. Steimer, J. K. Steinke, and H. E. Gruning, “A reliable, interface- the Inventors Clubs of America, Inc.
friendly medium voltage drive based on the robust IGCT and DTC tech-
nologies,” in Conf. Rec. IEEE-IAS Annu. Meeting, Phoenix, AZ, Oct.
1999, pp. 1505–1512.
[76] S. Eicher, A. Weber, S. Bernet, and P. Steimer, “The 10 kV IGCT — A
new device for medium voltage drives,” in Conf. Rec. IEEE-IAS Annu.
Meeting, Rome, Italy, Oct. 2000, pp. 2859–2865.
[77] F. Auerbach, M. Glantschnig, A. Porst, J. G. Bauer, D. Reznik, H. J. Fang Zheng Peng (M’93–SM’96) received the B.S.
Schulze, J. Gottert, M. Hierholzer, T. Schutze, and R. Spanke, “6.5 kV degree from Wuhan University, Wuhan, China, in
IGBT modules,” in Conf. Rec. IEEE-IAS Annu. Meeting, Phoenix, AZ, 1983 and the M.S. and Ph.D. degrees from Nagaoka
Oct. 1999, pp. 1770–1774. University of Technology, Nagaoka Japan, in 1987
[78] A. Q. Huang, S. Sirisukprasert, Z. Xu, B. Zhang, and J. S. Lai, “A and 1990, respectively, all in electrical engineering.
high-frequency 1.5 MVA H-bridge building block for cascaded multi- From 1990 to 1992, he was a Research Scientist
level converters using emitter turn-off thyristor (ETO),” in Proc. IEEE with Toyo Electric Manufacturing Company, Ltd.,
APEC, Dallas, TX, Mar. 2002, pp. 25–32. where he was engaged in research and development
of active power filters, flexible ac transmission
systems (FACTS) applications, and motor drives.
From 1992 to 1994, he was a Research Assistant
José Rodríguez (M’81–SM’94) received the Engi- Professor at Tokyo Institute of Technology, where initiated a multilevel inverter
neer degree from the Universidad Técnica Federico program for FACTS applications and a speed-sensorless vector control project.
Santa María, Valparaiso, Chile, in 1977 and the From 1994 to 1997, he was a Research Assistant Professor at the University of
Dr.-Ing. degree from the University of Erlangen, Tennessee, Knoxville, working for Oak Ridge National Laboratory (ORNL).
Erlangen, Germany, in 1985, both in electrical From 1997 to 2000 he was a Senior Staff Member at ORNL and Lead
engineering. (principal) Scientist of the Power Electronics and Electric Machinery Research
Since 1977, he has been with the University Téc- Center. In 2000, he joined Michigan State University, East Lansing, as an
nica Federico Santa María, where he is currently a Associate Professor in the Department of Electrical and Computer Engineering.
Professor and Head of the Department of Electronic He is the holder of ten patents.
Engineering. During his sabbatical leave in 1996, he Dr. Peng has received many awards, including the 1996 First Prize Paper
was responsible for the Mining Division of Siemens Award and the 1995 Second Prize Paper Award from the Industrial Power Con-
Corporation in Chile. He has extensive consulting experience in the mining in- verter Committee at the IEEE Industry Applications Society Annual Meeting,
dustry, especially in the application of large drives like cycloconverter-fed syn- the 1996 Advanced Technology Award of the Inventors Clubs of America, Inc.,
chronous motors for SAG mills, high-power conveyors, controlled drives for the International Hall of Fame, the 1991 First Prize Paper Award from the IEEE
shovels, and power quality issues. His research interests are mainly in the areas TRANSACTIONS ON INDUSTRY APPLICATIONS, and the 1990 Best Paper Award
of power electronics and electrical drives. Recently, his main research interests from the Transactions of the Institute of Electrical Engineers of Japan, and the
have been multilevel inverters and new converter topologies. He has authored Promotion Award of the Electrical Academy. He has been an Associate Editor of
or coauthored more than 100 refereed journal and conference papers and con- the IEEE TRANSACTIONS ON POWER ELECTRONICS since 1997 and is currently
tributed to one chapter in Power Electronics Handbook (New York: Academic, the Chair of the Technical Committee for Rectifiers and Inverters of the IEEE
2001). Power Electronics Society.