TB3104

Boost Converter Using the PIC16F753 Analog Features

Author: Mihnea Rosu-Hamzescu

PERFORMANCE SPECIFICATIONS
Microchip Technology Inc. Electrical specifications over operating range:
3V ≤ VDD ≤ 5V.
INTRODUCTION
TABLE 1: ELECTRICAL SPECIFICATIONS
This technical brief describes a boost power supply
based on the PIC16F753, using 100% analog control Input Voltage Range 3-5 Volts DC
for output regulation. The implementation has the Output Voltage 5 Volts DC
advantage of not using any processor power, leaving Output Current 2 Amperes
the core free for more complex firmware. Also, the
Output Power 10 Watts
analog loop has a much faster response time to load
steps and input voltage changes, making it useful for Code Size 99 Words
many applications. Ram Size 0 Bytes
The peripherals needed for the application are: Efficiency 87% Measured at 2A
• One Complementary Output Generator (CWG) Available Code Size 1949 Words
• One Comparator (COMP) Available RAM Size 128 Bytes
• One Operational Amplifier (OPA)
• One 9-bit Digital-to-Analog Converter (DAC)
• One Fixed Voltage Reference (FVR)
• One Slope Compensation Module (SC)
• One Capture/Compare/PWM Module (CCP)
The peripherals are internally connected through
firmware, significantly reducing the number of external
pins needed for the implementation.

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TB3104
BLOCK DIAGRAM Figure 1 illustrates the block diagram of the power
supply.
The output voltage is regulated using Peak Current
mode control. The output voltage is compared to the
reference voltage by the error amplifier (OPA) and the
result is fed to the peak current comparator. The
internal slope compensation module subtracts a
software programmable ramp from the error amplifier
output before the peak current comparator.
The CCP provides a fixed-frequency, fixed duty cycle
control signal and the peak current comparator output
is selected as a second (level-based) source for the
COG falling edge.

FIGURE 1: BLOCK DIAGRAM

VIN

Load

COG1OUT0
CCP COG
PIC16F753

Falling Edge Event

ISense

+ - COMP
SC
1.2V FVR DAC

OA +
FB
-

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 TB3104
FIGURE 2: EFFICIENCY
94,00 %

92,00 %

90,00 %

88,00 %

86,00 % 4V Input
3V Input
84,00 %

82,00 %

80,00 %

78,00 %
50 mA 100 250 500 750 1000 1200 1400 1600 1800 2000
mA mA mA mA mA mA mA mA mA mA

FUNCTIONAL DESCRIPTION Output current limiting is not integrated into the control
loop, thus a second comparator should be used for this
This power supply is a fixed-frequency Peak Current purpose and selected as an auto-shutdown source for
mode converter. The operational amplifier (OPA) is the COG. The error amplifier output is the inductor peak
used as an error amplifier (EA) for the output voltage, current limit, so keeping this value low by a resistor
and a comparator limits the peak inductor current on divider helps with inrush current problems and
each switching cycle, based on the EA feedback. The catastrophic short-circuit conditions. Of course, the
voltage reference for the EA is generated by the DAC downside of this approach is that the system gain is
and can be changed on-the-fly in firmware. The CCP reduced and that it will respond slower to transients.
peripheral generates a fixed frequency, fixed duty cycle The OPA output pin is the same as the slope
control signal for the COG. The peak current compensation module input pin, so the two peripherals
comparator is used to close the loop through by can be used together without any additional external
selecting it as a second falling edge event source connectivity. If a resistor divider is used to limit OPA
(limits duty cycle on each switching pulse based on EA output voltage, it must be routed externally to the FVR
feedback). buffer input pin.
After the peripherals are configured and connected Input voltage is connected to the microcontroller using
together, the control loop runs by itself, requiring 0% a small diode and is bootstrapped to the output. Thus,
processor time. when the output voltage rises, it will power the
Peak current control schemes require slope microcontroller and MOSFET driver. This is more
compensation for duty cycles over 50% to prevent efficient because a higher VGS will improve RDS(ON)
oscillation. For lower duty cycles, slope compensation and the interval below 4.5V is problematic for most
will also help stabilize the control loop, if the current power transistors. This also makes the FVR the only
shunt is small. The internal slope compensation stable reference available, and the circuit requires a
module subtracts a software programmable ramp from few changes to ensure that the loop reference voltage
the error amplifier output before the peak current is always independent from the supply or output
comparator. voltage. Since the control loop reference voltage is
derived from the DAC, this peripheral needs to have a
For the boost topology, the inductor current is equal to
stable reference, too. The FVR of 1.2V is selected as
the input current. The peak inductor current is
the DAC reference, thus fulfilling all the mentioned
measured directly on a resistor placed between the
requirements.
transistor source and the ground.

 2013 Microchip Technology Inc. DS90003104A-page 3

TB3104
It is important to mention that the boost topology has a APPLICATIONS
clear DC path from the power source to the output,
through the inductor and rectifier diode, even if the The analog control loop makes the power supply fast
switching transistor is blocked. The current limiting loop enough for dynamic loads and input voltage changes.
can only prevent overcurrent until the switching fre- For current-controlled loads like LEDs or
quency becomes zero. From this point on, catastrophic thermoelectric cells, the voltage feedback can be
short-circuit events can occur without an additional pro- replaced by average current feedback. The power
tection switch. A second transistor can be placed on supply can be also used for applications which require
the output low side to cut off the load in case of a short both voltage and current control like CC/CV battery
circuit. chargers. The PIC16F753 DAC has nine bits of
For comparator-based short-circuit protection, the resolution, which translate into a minimum voltage step
reference must be stable over the whole voltage of 50 mV with a 1/5 output divider.
operating range. Since the output current shunt voltage
is usually too small to use with the 1.2V FVR directly, it
needs to be routed outside through the FVR buffer and
then through a resistive divider to obtain the desired
reference voltage for the comparator. Since the FVR
buffer is used this way, the OPA output must be used
directly with the SC, without the additional divider. This
solution uses 0% processor time but also uses more
pins and peripherals. For ADC-based short-circuit
protection, the current shunt voltage and the FVR are
read in firmware. The FVR voltage is necessary to
calculate VDD (when <5V), which in this case is the
ADC reference voltage. While this second solution
does not use the extra comparator, I/O pins and
external resistors, it will need some program space and
processor time.
The component values shown in this document are to
be treated only as a starting point. They need to be
tuned for each design. The converter must be
compensated for a specific load and the stability must
be verified across the entire range of operating
conditions.
Compared to a solution using a specialized PWM
controller chip, performance is similar, but a PIC®
microcontroller-based solution adds invaluable
flexibility. Also, the analog control loop runs by itself, so
the microcontroller core is 100% free to run user
algorithms, measure power supply parameters or
transmit relevant information.

DS90003104A-page 4  2013 Microchip Technology Inc.

 TB3104
MCU PERIPHERAL CONFIGURATION The input-only digital pin, MCLR, can be used for a
button or a similar functionality. During run-time, the
DRAWING
programming data I/O pin (PGD) are free for user-
The application needs one OPA, one comparator and specific functionality.
one DAC. The DAC output can be internally routed to
the OPA, so this feature saves one pin. The CCP
TABLE 2: PIC16F753 PERIPHERAL
module generates a fixed-frequency, fixed duty cycle
signal for the COG. Depending on the user option to CONFIGURATION
limit the OPA output, the resistor divider needs to be Pin
Name Function
externally connected to the FVR buffer input. If not No.
using the resistor divider, only one pin is used instead 1 VDD Supply voltage
of two. In this case, the OPA output, which is the same
14 VSS Ground connection
as the SC input, is configured as an analog pin and
should not be used for other purposes. 10 RC0 Analog input (COMP) – peak
current sensing
9 RC1 Analog input (OPA) – output
voltage feedback
8 RC2 Analog output (OPA) – error
amplifier output
12 RA1/PGC/ Analog input FVR buffer input
FVRIN for peak current limit from error
amplifier/ Programming clock
13 PGD Programming data
5 COG1OUT0/ Transistor control signal (PWM)
RC5

FIGURE 3: PERIPHERAL CONFIGURATION

COG1OUT0
COG PWM
RC5

CCP

COMP 2

+ -

SC ISense

FVR DAC

OPA_EA VREF
+

- FB
RC1
RC2

OPA_OUT

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TB3104
PLOTS OF KEY PARAMETERS TABLE 3: POWER SUPPLY
CHARACTERISTICS
Table 3 contains some characteristics of the charger
Output
obtained with an input of 3V and an output of 5V. The Duty Cycle Efficiency
Current
switching frequency is 250 kHz. (%) (%)
(mA)
500 43.9 91.4
TABLE 3: POWER SUPPLY
750 44.6 90.8
CHARACTERISTICS
1000 45.3 90.1
Output
Duty Cycle Efficiency 1200 45.7 89.6
Current
(%) (%) 1400 46.4 89.0
(mA)
0 skipping N/A 1600 46.9 88.3
50 26.3 83.5 1800 47.4 87.6
100 37.2 87.8 2000 48.2 86.8
250 43.2 90.4 Note 1: Efficiency is calculated including power
loss on current shunt.

FIGURE 4: DUTY CYCLE vs. LOAD CURRENT

60,0 %

50,0 %

40,0 %

30,0 % 4V Input
3V Input
20,0 %

10,0 %

0,0 %
50 mA 100 250 500 750 1000 1200 1400 1600 1800 2000
mA mA mA mA mA mA mA mA mA mA

Figure 4 shows the converter operating frequency for GLOSSARY

3V and 4V input at different output currents. Once the
inductor current becomes continuous, the duty cycle TABLE 4: ACRONYMS
changes very little, only to compensate for component PWM Pulse-Width Modulation
power losses. The power loss becomes very easy to ADC Analog-to-Digital Converter
see on the efficiency graph (see Figure 2).
DAC Digital-to-Analog Converter
COG Complementary Output Generator
FVR Fixed Voltage Reference
OPA Operational Amplifier
EA Error Amplifier
SC(M) Slope Compensation (Module)
CCP Capture Compare PWM

DS90003104A-page 6  2013 Microchip Technology Inc.

 TB3104
APPENDIX A:

FIGURE A-1: SCHEMATIC

 2013 Microchip Technology Inc. DS90003104A-page 7

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ISBN: 9781620777497

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DS90003104A-page 8  2013 Microchip Technology Inc.

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 2013 Microchip Technology Inc. DS90003104A-page 9