CPPC 12 Introduction to HDL Laboratory Notes 2

Laboratory Notes 2 : ModelSim Tutorial

1. Conceptual Overview

Modelsim is a program created by Mentor Graphics, verification and simulation tool for VHDL,
Verilog, SystemVerilog, SystemC, and mixed-language designs. It is the most widely use
simulation program in business and education.

Simulation is a critical step of designing FPGAs and ASICs. Simulation allows the designer to
stimulate his or her design and see how the code that they wrote reacts to the stimulus. A great
simulation will exercise all possible states of the design to ensure that all input scenarios will be
handled appropriately. Did you forget if statement somewhere? Did you remember to give
every possible case statement assignment? These are the types of errors that are very easy to
make when you do not simulate your design. Let's get started.

This lesson provides a brief conceptual overview of the ModelSim simulation environment. It is
divided into five topics, which you will learn more about in subsequent lessons.
• Design Optimizations
• Basic simulation flow
• Project flow
• Multiple library flow
• Debugging tools

Design Optimizations

Before discussing the basic simulation flow, it is important to understand design optimization. By
default, ModelSim optimizations are automatically performed on all designs. These
optimizations are designed to maximize simulator performance, yielding improvements up to
10X, in some Verilog designs, over non-optimized runs.

Global optimizations, however, may have an impact on the visibility of the design simulation
results you can view – certain signals and processes may not be visible. If these signals and
processes are important for debugging the design, it may be necessary to customize the
simulation by removing optimizations from specific modules.

It is important, therefore, to make an informed decision as to how best to apply optimizations to

your design. The tool that performs global optimizations in ModelSim is called vopt.
CPPC 12 Introduction to HDL Laboratory Notes 2

Basic Simulation Flow

The following diagram shows the basic steps for simulating a design in ModelSim.

Figure 2-1. Basic Simulation Flow - Overview Lab

Create a working library

Compile design files

Load and Run simulation

Debug results

• Creating the Working Library

In ModelSim, all designs are compiled into a library. You typically start a new
simulation in ModelSim by creating a working library called "work," which is
the default library name used by the compiler as the default destination for
compiled design units.

• Compiling Your Design

After creating the working library, you compile your design units into it. The
ModelSim library format is compatible across all supported platforms. You
can simulate your design on any platform without having to recompile your
design.
• Loading the Simulator with Your Design and Running the Simulation
With the design compiled, you load the simulator with your design by
invoking the simulator on a top-level module (Verilog) or a configuration or
entity/architecture pair (VHDL).
Assuming the design loads successfully, the simulation time is set to zero,
and you enter a run command to begin simulation.

• Debugging Your Results

If you don’t get the results you expect, you can use ModelSim’s robust
debugging environment to track down the cause of the problem.
CPPC 12 Introduction to HDL Laboratory Notes 2

Project Flow
A project is a collection mechanism for an HDL design under specification or test. Even though
you don’t have to use projects in ModelSim, they may ease interaction with the tool and are
useful for organizing files and specifying simulation settings.

The following diagram shows the basic steps for simulating a design within a ModelSim project.

Figure 2-2. Project Flow

Create a project

Add files to the project

Compile design files

Run simulation

Debug results

As you can see, the flow is similar to the basic simulation flow. However,
there are two important differences:

• You do not have to create a working library in the project flow; it is

done for you automatically.
• Projects are persistent. In other words, they will open every time you invoke
ModelSim unless you specifically close them.

Multiple Library Flow

ModelSim uses libraries in two ways:
1) as a local working library that contains the compiled version of your design;
2) as a resource library.
The contents of your working library will change as you update your design and recompile. A
resource library is typically static and serves as a parts source for your design. You can create
your own resource libraries, or they may be supplied by another design team or a third party
(e.g., a silicon vendor).
CPPC 12 Introduction to HDL Laboratory Notes 2

You specify which resource libraries will be used when the design is compiled, and there are
rules to specify in which order they are searched. A common example of using both a working
library and a resource library is one where your gate-level design and test bench are compiled
into the working library, and the design references gate-level models in a separate resource
library.

The diagram below shows the basic steps for simulating with multiple libraries.

Figure 2-3. Multiple Library Flow

Create a working library

Compile design files

Link to resource libraries

Run simulation

Debug results

You can also link to resource libraries from within a project. If you are using a project, you would
replace the first step above with these two steps: create the project and add the test bench to
the project.

Debugging Tools
ModelSim offers numerous tools for debugging and analyzing your design. Several of these
tools are covered in subsequent lessons, including:

• Using projects
• Working with multiple libraries
• Simulating with SystemC
• Setting breakpoints and stepping through the source code
• Viewing waveforms and measuring time
CPPC 12 Introduction to HDL Laboratory Notes 2

• Exploring the "physical" connectivity of your design

• Viewing and initializing memories
• Creating stimulus with the Waveform Editor
• Analyzing simulation performance
• Testing code coverage
• Comparing waveforms
• Debugging with PSL assertions
• Using SystemVerilog assertions and cover directives
• Using the SystemVerilog DPI
• Automating simulation
CPPC 12 Introduction to HDL Laboratory Notes 2

2. Basic simulation flow

In this lesson you will go step-by-step through the basic simulation flow:

1. Create the Working Design Library

2. Compile the Design Units
3. Optimize the Design
4. Load the Design
5. Run the Simulation

Design Files for this Lesson

The sample design for this lesson is a simple 8-bit, binary up-counter with an associated
test bench. The pathnames are as follows:

Verilog – <install_dir>/examples/tutorials/verilog/basicSimulation/counter.v and

tcounter.v

VHDL – <install_dir>/examples/tutorials/vhdl/basicSimulation/counter.vhd and

tcounter.vhd

This lesson uses the Verilog files counter.v and tcounter.v. If you have a VHDL license,

use

counter.vhd and tcounter.vhd instead. Or, if you have a mixed license, feel free to use the
Verilog test bench with the VHDL counter or vice versa.

2.1 Create the Working Design Library

Before you can simulate a design, you must first create a library and compile the source
code into that library.

1. Create a new directory and copy the design files for this lesson into it. Start by
creating a new directory for this exercise (in case other users will be working with
these lessons).
Start by creating a new directory for this exercise (in case other users will be
working with these lessons).
Verilog: Copy counter.v and tcounter.v files from
/<install_dir>/examples/tutorials/verilog/basicSimulation to the new directory.
VHDL: Copy counter.vhd and tcounter.vhd files from
/<install_dir>/examples/tutorials/vhdl/basicSimulation to the new directory.
CPPC 12 Introduction to HDL Laboratory Notes 2

2. Start ModelSim if necessary.

a. Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows.
Upon opening ModelSim for the first time, you will see the Welcome to
ModelSim dialog. Click Close.
b. Select File > Change Directory and change to the directory you created in
step 1.
3. Create the working library.
a. Select File > New > Library.
This opens a dialog where you specify physical and logical names for the
library (Figure 3-1). You can create a new library or map to an existing library.
We’ll be doing the former.

Figure 3-1. The Create a New Library Dialog

b. Type work in the Library Name field (if it isn’t already entered automatically).
c. Click OK.
ModelSim creates a directory called work and writes a specially-formatted file named
_info into that directory. The _info file must remain in the directory to distinguish it as a
ModelSim library. Do not edit the folder contents from your operating system; all
changes should be made from within ModelSim.

ModelSim also adds the library to the Library window (Figure 3-2) and records the library
mapping for future reference in the ModelSim initialization file (modelsim.ini).
CPPC 12 Introduction to HDL Laboratory Notes 2

Figure 3-2. work Library Added to the Library Window

When you pressed OK in step 3c above, the following was printed to the Transcript
window:

vlib work
vmap work work

These two lines are the command-line equivalents of the menu selections you made.
Many command-line equivalents will echo their menu-driven functions in this fashion.

2.2 Compile the Design Units

With the working library created, you are ready to compile your source files.

You can compile by using the menus and dialogs of the graphic interface, as in the
Verilog example below, or by entering a command at the ModelSim> prompt.

1. Compile counter.v and tcounter.v.

a. Select Compile > Compile. This opens the Compile Source
Files dialog (Figure 3-3).
If the Compile menu option is not available, you probably have a project open.
If so, close the project by making the Library window active and selecting File
> Close from the menus.
b. Select both counter.v and tcounter.v modules from the Compile Source Files
dialog and click Compile. The files are compiled into the work library.
c. When compile is finished, click Done.
CPPC 12 Introduction to HDL Laboratory Notes 2

Figure 3-3. Compile Source Files Dialog

2. View the compiled design units.

a. In the Library window, click the ’+’ icon next to the work library and you will
see two design units (Figure 3-4). You can also see their types (Modules,
Entities, etc.) and the path to the underlying source files.

Figure 3-4. Verilog Modules Compiled into work Library

2.3 Optimize the Design

1. Use the vopt command to optimize the design with full visibility into all design
units.
a. Enter the following command at the ModelSim> prompt in the Transcript
window:
vopt +acc test_counter -o testcounter_opt
CPPC 12 Introduction to HDL Laboratory Notes 2

The +acc switch provides visibility into the design for debugging purposes.
The -o switch allows you designate the name of the optimized
design file (testcounter_opt).

Note
You must provide a name for the optimized design file when you use the vopt
command.

2.4 Load the Design

1. Load the test_counter module into the simulator.
a. Use the optimized design name to load the design with the vsim command:
vsim testcounter_opt
When the design is loaded, a Structure window opens (labeled sim). This
window displays the hierarchical structure of the design as shown in Figure 3-
5. You can navigate within the design hierarchy in the Structure (sim) window
by clicking on any line with a ’+’ (expand) or ’-’ (contract) icon.

Figure 3-5. The Design Hierarchy

In addition, an Objects window and a Processes window opens (Figure 3-6).

The Objects window shows the names and current values of data objects in
the current region selected in the Structure (sim) window. Data objects include
signals, nets, registers, constants and variables not declared in a process,
generics, parameters, and member data variables of a SystemC module.
The Processes window displays a list of HDL and SystemC processes in one
of four viewing modes: Active, In Region, Design, and Hierarchical. The Design
view mode is intended for primary navigation of ESL (Electronic System Level)
designs where processes are a foremost consideration. By default, this
window displays the active processes in your simulation (Active view mode).
CPPC 12 Introduction to HDL Laboratory Notes 2

Figure 3-6. The Object Window and Processes Window

2.5 Run the Simulation

We’re ready to run the simulation. But before we do, we’ll open the Wave window and
add signals to it.

1. Open the Wave window.

a. Enter view wave at the command line.
The Wave window opens in the right side of the Main window. Resize it so it is
visible.
You can also use the View > Wave menu selection to open a Wave window.
The Wave window is just one of several debugging windows available on the
View menu.
2. Add signals to the Wave window.
a. In the Structure (sim) window, right-click test_counter to open a popup context
menu.
b. Select AddTo > Wave > All items in region (Figure 3-7). All signals in the
design are added to the Wave window.
CPPC 12 Introduction to HDL Laboratory Notes 2

Figure 3-7. Using the Popup Menu to Add Signals to Wave Window

1. Run the simulation.

a. Click the Run icon.
The simulation runs for 100 ns (the default simulation length) and waves are
drawn in the Wave window.

b. Enter run 500 at the VSIM> prompt in the Transcript window.

The simulation advances another 500 ns for a total of 600 ns (Figure 3-8).

Figure 3-8. Waves Drawn in Wave Window

c. Click the Run -All icon on the Main or Wave window toolbar.
The simulation continues running until you execute a break command or it hits
a statement in your code (e.g., a Verilog $stop statement) that halts the
simulation.

d. Click the Break icon to stop the simulation.

CPPC 12 Introduction to HDL Laboratory Notes 2

Set Breakpoints and Step through the Source

Next you will take a brief look at one interactive debugging feature of the ModelSim
environment. You will set a breakpoint in the Source window, run the simulation, and then step
through the design under test. Breakpoints can be set only on executable lines, which are
indicated with red line numbers.

1. Open counter.v in the Source window.

a. Select View > Files to open the Files window.
b. Click the + sign next to the sim filename to see the contents of vsim.wlf
dataset.
c. Double-click counter.v (or counter.vhd if you are simulating the VHDL files) to
open the file in the Source window.
2. Set a breakpoint on line 36 of counter.v (or, line 39 of counter.vhd for VHDL).
a. Scroll to line 36 and click in the Ln# (line number) column next to the line
number.
A red ball appears in the line number column at line number 36 (Figure 3-9),
indicating that a breakpoint has been set.

Figure 3-9. Setting Breakpoint in Source Window

3. Disable, enable, and delete the breakpoint.

a. Click the red ball to disable the breakpoint. It will become a black ball.
b. Click the black ball again to re-enable the breakpoint. It will become a red ball.
c. Click the red ball with your right mouse button and select Remove
Breakpoint 36.
d. Click in the line number column next to line number 36 again to re-create the
breakpoint.
4. Restart the simulation.
a. Click the Restart icon to reload the design elements and reset the simulation
time to zero.
CPPC 12 Introduction to HDL Laboratory Notes 2

The Restart dialog that appears gives you options on what to retain during the
restart (Figure 3-10).

Figure 3-10. Setting Restart Functions

a. Click the Restart button in the Restart dialog.

b. Click the Run -All icon.
The simulation runs until the breakpoint is hit. When the simulation hits
the breakpoint, it stops running, highlights the line with a blue arrow in the
Source view (Figure 3-11), and issues a Break message in the Transcript
window.

Figure 3-11. Blue Arrow Indicates Where Simulation Stopped.

When a breakpoint is reached, typically you want to know one or more signal
values. You have several options for checking values:

• look at the values shown in the Objects window (Figure 3-12)

CPPC 12 Introduction to HDL Laboratory Notes 2

Figure 3-12. Values Shown in Objects Window

• set your mouse pointer over a variable in the Source window and a yellow
box will appear with the variable name and the value of that variable at the
time of the selected cursor in the Wave window

• highlight a signal, parameter, or variable in the Source window, right-click

it, and select Examine from the pop-up menu to display the variable and its
current value in a Source Examine window (Figure 3-13)

Figure 3-13. Parameter Name and Value in Source Examine Window

• use the examine command at the VSIM> prompt to output a variable

value to the Transcript window (i.e., examine count)
5. Try out the step commands.
a. Click the Step Into icon on the
Step toolbar. This single-steps
the debugger.
Experiment on your own. Set and clear breakpoints and use the Step, Step
Over, and Continue Run commands until you feel comfortable with their
operation.

Lesson Wrap-Up
This concludes this lesson. Before continuing we need to end the current simulation.

1. Select Simulate > End Simulation.

2. Click Yes when prompted to confirm that you wish to quit simulating.
CPPC 12 Introduction to HDL Laboratory Notes 2

Creating a Project

In this lesson you will practice creating a project.

At a minimum, projects contain a work library and a session state that is stored in an .mpf file. A
project may also consist of:

• HDL source files or references to source files

• other files such as READMEs or other project documentation
• local libraries
• references to global libraries

Design Files for this Lesson

The sample design for this lesson is a simple 8-bit, binary up-counter with an associated test
bench. The pathnames are as follows:

Verilog – <install_dir>/examples/tutorials/verilog/projects/counter.v and tcounter.v

VHDL – <install_dir>/examples/tutorials/vhdl/projects/counter.vhd and tcounter.vhd

This lesson uses the Verilog files tcounter.v and counter.v. If you have a VHDL license, use
tcounter.vhd and counter.vhd instead.

Create a New Project

1. Create a new directory and copy the design files for this lesson into it.
Start by creating a new directory for this exercise (in case other users will be
working with these lessons).
Verilog: Copy counter.v and tcounter.v files from
/<install_dir>/examples/tutorials/verilog/projects to the new directory.
VHDL: Copy counter.vhd and tcounter.vhd files from
/<install_dir>/examples/tutorials/vhdl/projects to the new directory.

2. If you just finished the previous lesson, ModelSim should already be

running. If not, start ModelSim.
a. Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows.
b. Select File > Change Directory and change to the directory you created in
step 1.
3. Create a new project.
a. Select File > New > Project (Main window) from the menu bar.
CPPC 12 Introduction to HDL Laboratory Notes 2

This opens the Create Project dialog where you can enter a Project Name,
Project Location (i.e., directory), and Default Library Name (Figure 4-1). You can
also reference library settings from a selected .ini file or copy them directly into
the project. The default library is where compiled design units will reside.
b. Type test in the Project Name field.
c. Click the Browse button for the Project Location field to select a directory
where the project file will be stored.
d. Leave the Default Library Name set to work.
e. Click OK.

Figure 4-1. Create Project Dialog - Project Lab

Add Objects to the Project

Once you click OK to accept the new project settings, a blank Project window and the
“Add items to the Project” dialog will appear (Figure 4-2). From the dialog you can create
a new design file, add an existing file, add a folder for organization purposes, or create a
simulation configuration (discussed below).

Figure 4-2. Adding New Items to a Project

CPPC 12 Introduction to HDL Laboratory Notes 2

1. Add two existing files.

a. Click Add Existing File.
This opens the Add file to Project dialog (Figure 4-3). This dialog lets you browse
to find files, specify the file type, specify a folder to which the file will be added,
and identify whether to leave the file in its current location or to copy it to the
project directory.

Figure 4-3. Add file to Project Dialog

b. Click the Browse button for the File Name field. This opens
the “Select files to add to project” dialog and displays the
contents of the current directory.
c. Verilog: Select counter.v and tcounter.v and click Open.
VHDL: Select counter.vhd and tcounter.vhd and click Open.

This closes the “Select files to add to project” dialog and displays the selected
files in the “Add file to Project” dialog (Figure 4-3).
d. Click OK to add the files to the project.
e. Click Close to dismiss the Add items to the Project dialog.
You should now see two files listed in the Project window (Figure 4-4). Question-
mark icons in the Status column indicate that the file has not been compiled or
that the source file has changed since the last successful compile. The other
columns identify file type (e.g., Verilog or VHDL), compilation order, and modified
date.

Figure 4-4. Newly Added Project Files Display a ’?’ for Status
CPPC 12 Introduction to HDL Laboratory Notes 2

Changing Compile Order (VHDL)

By default ModelSim performs default binding of VHDL designs when you load the design with
vsim. However, you can elect to perform default binding at compile time. (For details, refer to
the section Default Binding in the User’s Manual.) If you elect to do default binding at compile,
then the compile order is important. Follow these steps to change compilation order within a
project.

1. Change the compile order.

a. Select Compile > Compile Order.
This opens the Compile Order dialog box.
b. Click the Auto Generate button.
ModelSim determines the compile order by making multiple passes over the files. It starts
compiling from the top; if a file fails to compile due to dependencies, it moves that file to the
bottom and then recompiles it after compiling the rest of the files. It continues in this manner
until all files compile successfully or until a file(s) can’t be compiled for reasons other than
dependency.
Alternatively, you can select a file and use the Move Up and Move Down buttons to put the files
in the correct order (Figure 4-5).

Figure 4-5. Compile Order Dialog

c. Click OK to close the Compile Order dialog.

CPPC 12 Introduction to HDL Laboratory Notes 2

Compile the Design

1. Compile the files.
a. Right-click either counter.v or tcounter.v in the Project window and select
Compile
> Compile All from the pop-up menu.

ModelSim compiles both files and changes the symbol in the Status column to a green check
mark. A check mark means the compile succeeded. If compile fails, the symbol will be a red ’X’,
and you will see an error message in the Transcript window.
2. View the design units.
a. Click the Library tab (Figure 4-6).
b. Click the ’+’ icon next to the work library.
You should see two compiled design units, their types (modules in this case), and the path to the
underlying source files.

Figure 4-6. Library Window with Expanded Library

Optimize for Design Visibility

1. Use the vopt command to optimize the design with full visibility into all design
units.
a. Enter the following command at the QuestaSim> prompt in the Transcript
window:
vopt +acc test_counter -o testcounter_opt
CPPC 12 Introduction to HDL Laboratory Notes 2

The +acc switch provides visibility into the design for debugging
purposes.
The -o switch allows you designate the name of the optimized design file
(testcounter_opt).

Note
You must provide a name for the optimized design file when you use the vopt command.

Load the Design

1. Load the test_counter design unit.
a. Use the optimized design name to load the design with the vsim command:
vsim testcounter_opt
The Structure (sim) window appears as part of the tab group with the Library
and Project windows (Figure 4-7).

Figure 4-7. Structure(sim) window for a Loaded Design

At this point you would typically run the simulation and analyze or debug your design like
you did in the previous lesson. For now, you’ll continue working with the project.
However, first you need to end the simulation that started when you loaded test_counter.
2. End the simulation.
a. Select Simulate > End Simulation.
b. Click Yes.
CPPC 12 Introduction to HDL Laboratory Notes 2

Organizing Projects with Folders

If you have a lot of files to add to a project, you may want to organize them in folders. You can
create folders either before or after adding your files. If you create a folder before adding files,
you can specify in which folder you want a file placed at the time you add the file (see Folder
field in Figure 4-3). If you create a folder after adding files, you edit the file properties to move it
to that folder.

Add Folders
As shown previously in Figure 4-2, the Add items to the Project dialog have an option for adding
folders. If you have already closed that dialog, you can use a menu command to add a folder.

1. Add a new folder.

a. Right-click in the Projects window and select Add to Project > Folder.
b. Type Design Files in the Folder Name field (Figure 4-8).

Figure 4-8. Adding New Folder to Project

c. Click OK.
The new Design Files folder is displayed in the Project window (Figure 4-9).

Figure 4-9. A Folder Within a Project

2. Add a sub-folder.
CPPC 12 Introduction to HDL Laboratory Notes 2

a. Right-click anywhere in the Project window and select Add to Project >
Folder.
b. Type HDL in the Folder Name field (Figure 4-10).

Figure 4-10. Creating Subfolder

c. Click the Folder Location drop-down arrow and select Design Files.
d. Click OK.

A ’+’ icon appears next to the Design Files folder in the Project window (Figure 4-
11).

Figure 4-11. A folder with a Sub-folder

e. Click the ’+’ icon to see the HDL sub-folder.

Moving Files to Folders

If you don’t place files into a folder when you first add the files to the project, you can move
them into a folder using the properties dialog.

1. Move tcounter.v and counter.v to the HDL folder.

a. Select both counter.v and tcounter.v in the Project window.
b. Right-click either file and select Properties.
This opens the Project Compiler Settings dialog (Figure 4-12), which allows you to set a
variety of options on your design files.
CPPC 12 Introduction to HDL Laboratory Notes 2

Figure 4-12. Changing File Location via the Project Compiler Settings Dialog

c. Click the Place In Folder drop-down arrow and select HDL.

d. Click OK.

The selected files are moved into the HDL folder. Click the ’+’ icon next to the HDL folder to see
the files.
The files are now marked with a ’?’ in the Status column because you moved the files. The
project no longer knows if the previous compilation is still valid.

Simulation Configurations
A Simulation Configuration associates a design unit(s) and its simulation options. For example,
let’s say that every time you load tcounter.v you want to set the simulator resolution to
picoseconds (ps) and enable event order hazard checking. Ordinarily, you would have to specify
those options each time you load the design. With a Simulation Configuration, you specify
options for a design and then save a “configuration” that associates the design and its options.
The configuration is then listed in the Project window and you can double-click it to load
tcounter.v along with its options.

1. Create a new Simulation Configuration.

a. Right-click in the Project window and select Add to Project > Simulation
Configuration from the popup menu.
This opens the Add Simulation Configuration dialog (Figure 4-13). The tabs in this dialog
present several simulation options. You may want to explore the tabs to see what is available.
You can consult the ModelSim User’s Manual to get a description of each option.
CPPC 12 Introduction to HDL Laboratory Notes 2

Figure 4-13. Simulation Configuration Dialog

b. Type counter in the Simulation Configuration Name field.

c. Select HDL from the Place in Folder drop-down.
d. Click the ’+’ icon next to the work library and select test_counter.
e. Click the Resolution drop-down and select ps.
f. Uncheck the Enable optimization selection box.
g. For Verilog, click the Verilog tab and check Enable hazard checking (-
hazards).
h. Click Save.
The files tcounter.v and counter.v show question mark icons in the status column
because they have changed location since they were last compiled and need to be
recompiled.
i. Select one of the files, tcounter.v or counter.v.
j. Select Compile > Compile All.
CPPC 12 Introduction to HDL Laboratory Notes 2

The Project window now shows a Simulation Configuration named counter in the
HDL folder (Figure 4-14).

Figure 4-14. A Simulation Configuration in the Project window

2. Load the Simulation Configuration.

a. Double-click the counter Simulation Configuration in the Project window.
In the Transcript window of the Main window, the vsim (the ModelSim simulator) invocation
shows the -hazards and -t ps switches (Figure 4-15). These are the command-line equivalents
of the options you specified in the Simulate dialog.

Figure 4-15. Transcript Shows Options for Simulation Configurations

Lesson Wrap-Up
This concludes this lesson. Before continuing you need to end the current simulation and
close the current project.

1. Select Simulate > End Simulation. Click Yes.

2. In the Project window, right-click and select Close Project.

If you do not close the project, it will open automatically the next time you start ModelSim.
CPPC 12 Introduction to HDL Laboratory Notes 2

Laboratory Exercise 1

The code that we will be simulating is the VHDL design below. The actual code is not important,
so if you are learning Verilog that's OK! You don't need to know VHDL for this tutorial. The
VHDL code creates a simple and Gate and provides some inputs to it via a test bench. Copy
the code below to and_gate.vhd and the testbench to and_gate_tb.vhd.

and_gate.vhd:
1
2 library ieee;
3 use ieee.std_logic_1164.all;
4
entity and_gate is
5 port (
6
input_1 : in std_logic;
7
input_2 : in std_logic;
8 and_result : out std_logic
9 );
10 end and_gate;
11
12 architecture rtl of and_gate is
signal and_gate : std_logic;
13 begin
14 and_gate <= input_1 and input_2;
15 and_result <= and_gate;
16 end rtl;
17

and_gate_tb.vhd:
1 library ieee;
2 use ieee.std_logic_1164.all;
3
4 entity and_gate_tb is
end and_gate_tb;
5
6 architecture behave of and_gate_tb is
7 signal r_SIG1 : std_logic := '0';
8 signal r_SIG2 : std_logic := '0';
9 signal w_RESULT : std_logic;
10
11 component and_gate is
port (
12
input_1 : in std_logic;
13
input_2 : in std_logic;
14 and_result : out std_logic);
15 end component and_gate;
16
17 begin
18
19 and_gate_INST : and_gate
20 port map (
CPPC 12 Introduction to HDL Laboratory Notes 2

21 input_1 => r_SIG1,

22 input_2 => r_SIG2,
and_result => w_RESULT
23 );
24
25 process is
26 begin
27 r_SIG1 <= '0';
r_SIG2 <= '0';
28 wait for 10 ns;
29 r_SIG1 <= '0';
30 r_SIG2 <= '1';
31 wait for 10 ns;
32 r_SIG1 <= '1';
r_SIG2 <= '0';
33 wait for 10 ns;
34 r_SIG1 <= '1';
35 r_SIG2 <= '1';
36 wait for 10 ns;
end process;
37
38
end behave;
39
40
41
42
43
44

Let's open Modelsim. You are greeted with a window that looks like this

Modelsim Main Window

CPPC 12 Introduction to HDL Laboratory Notes 2

In order to run your simulation, you need to create a project. Click File -> New -> Project. You
will see the window presented on the left. Choose a location for your new project and give it the
name and_gate. Projects in Modelsim have the file extension .prj. Leave the other settings to
their default. This just says that all code will be compiled into the library "work".

Click on Add Existing File as shown in the picture to the right. Navigate to the location where you
downloaded and_gate.vhd and and_gate_tb.vhd and add both of those to your project. Keep other
settings at their default. Click OK when done.
CPPC 12 Introduction to HDL Laboratory Notes 2

Modelsim Project Window - Files Added to Project

Notice now that the files have been added successfully to your project. See those two blue question
marks in the Modelsim Project Window Figure above? That means that Modelsim has not compiled
the files yet. You will need to compile the source files. To do this, right click on and_gate.vhd, click
on Compile, then click on Compile All. You should see messages in the Console window appear in
green that the compile was successful as shown in the screenshot below.

Results of a Successful Compile

To start your simulation, click on Simulate in the Menu Bar, then click Start Simulation. This opens
the Start Simulation Window. Click on the plus sign next to work, then click on the plus sign next to
and_gate_tb. Make sure you select and_gate_tb and not and_gate as we want to simulate the
design at the test bench level. Once and_gate_tb is highlighted, click OK.
CPPC 12 Introduction to HDL Laboratory Notes 2

Modelsim Simulation Window - Simulation Ready

Almost there! The simulation is ready and waiting. Now, the majority of the time that you use
Modelsim will be spent looking at the waveform view. The waveform view contains waves (binary 0's
and 1's, hexadecimal digits, binary digits, enumerated types, etc) for all of the signals in your design.
It shows how your module reacts to different stimulus. The next figure shows you what your
waveform view looks like, but first you need to add some signals to monitor. In this example, we will
monitor all of the signals in the test bench. To do this, right click on and_gate_tb in the sim window
and click Add Wave. You can also click and drag signals to the waveform window from other
windows in Modelsim.
CPPC 12 Introduction to HDL Laboratory Notes 2

Here is your waveform window. All of the test bench signals have been added as signals your can
monitor. To run the simulation, click the Icon with a little piece of paper and a down arrow next to the
100 ns time. This will run your simulation for 100 nanoseconds. Watch how the signals change!
Congratulations! You've created your first Modelsim simulation!

This tutorial showed you how to create your own project in ModelSim, add files to your project,
compile your source files, start your simulation, and view your waveforms.

References:
ModelSim User’s Manual