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Implementation of A Full Adder

This document reports on a laboratory experiment to implement a full adder using logical functions in an FPGA. It begins with an introduction that describes a full adder and its truth table. The methodology section explains how the "S" and "C" logical functions of the full adder were implemented in Verilog code and tested using a testbench simulation. The results section shows the truth table and simulations verifying the correct logic. It concludes that full adders can be represented in different equivalent ways and truth tables are used to define the logic.

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Rebeca Cu
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75 views2 pages

Implementation of A Full Adder

This document reports on a laboratory experiment to implement a full adder using logical functions in an FPGA. It begins with an introduction that describes a full adder and its truth table. The methodology section explains how the "S" and "C" logical functions of the full adder were implemented in Verilog code and tested using a testbench simulation. The results section shows the truth table and simulations verifying the correct logic. It concludes that full adders can be represented in different equivalent ways and truth tables are used to define the logic.

Uploaded by

Rebeca Cu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Implementation of a full adder

Cu Rebeca, Gutiérrez José, Ventura Adriana, Yerbes Pablo


Digital Signal Processing
Universidad Autónoma de Yucatán, Facultad de Ingeniería
Mérida, México

Abstract — FPGA is a digital reconfigurable ASIC. Today, it II. METODOLOGY


is being used in many industries for a variety of reasons. This The implementation of Boolean functions corresponding to a
document is a report on Laboratory 2 and how to use logical complete adder using as a tool the simulation of logical
functions. functions and their implementation in an FPGA. In this case,
we will implement the "S" and "C" functions previously
I. INTRODUCTION analyzed to verify their correct implementation and operation.
The implementation of Boolean functions begins to make
sense when the implementation of the design in an FPGA is A. Testbench
oriented towards a practical application.
For example, a full adder is a digital circuit that can perform
the sum of three bits. Figure 1. Shows the truth table of a full
adder.

Figure 3. Testbench simulation

Figure 1. Full adder

As we can see, the sum of the 1 of the possible input


combinations defined in “x”, “y” and “z” is reflected in the
outputs “S” and “C”, where “S” is the sum of the bits and "C".

Figure 4. Testbench simulation

The output of the existing carry of the sum of three bits.


Analyzing Figure 1, we can see that the outputs can be
expressed as follows ...

Figure 5. Functions generated by blocks


Figure 2. Logical diagram of a full adder
As a result of the code implemented in Verilog, the code of the
test bench and the simulations, we can verify that the behavior
is what we expected from the logic diagram.

III. RESULTS
A. Truth table C

IV. CONCLUSIONS
One of the characteristics that we must take into account is that
a logic circuit does not have to be represented in a standardized
and common way. There are several ways for this to occur as
alternative factors to the ones and zeros presented by the binary
information that has been loaded into a digital component. For
example, we can see it with the balance that exists between the
truth table S: on and off function or in which you simply resort
to a switch that is open or closed with respect to the
transmission of energy. Therefore, depending on the position
occupied by a switch, a digital device can act or not without a
major change in its internal processes. To count and manage
these variables, truth tables are used.

V. REFERENCES
Viewpoint Systems (2019). FPGA Basics for Industrial
Applications. IEEE Communications Spectrum.

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