A Novel Approach to High Performance and Low cost IS-95A CDMA

Transceivers through FPGA

S. Rajaram, S. Dhinesh Joseph, K. Deepa, V. Abhaikumar
Department of Electronics and Communication Engineering,
Thiagarajar College of Engineering, Madurai-625015, INDIA.
[email protected]

ABSTRACT modules of Block Interleaver and Viterbi

In this paper, proficient architectures Decoder are dealt in detail.
for IS-95A CDMA Transceivers are modeled
and optimized for hardware implementation on 2. CONVENTIONAL BLOCK
FPGA. The efficiency of the transceivers is INTERLEAVER
improved by incorporating a novel Interleaver, The process of interleaving [7]
developed for mobile communication channel. separates consecutive bits wide apart and
The Interleaver improves the performance of thereby avoiding burst errors to a superior
the transceivers at lower SNR levels. The degree. The effect of interleaving is equivalent
architecture applies a new-fangled scheme for to multiplying the input sequence by a
implementing Viterbi decoder and thereby permutation matrix, which corresponds to a
results in reduced computation operations and linear operation [8]. For large block size
memory requirements. The model is interleavers, most random interleavers perform
implemented in V100CS144 chip with XILINX well. On the other hand, for some applications it
using VHDL. The FPGA hardware uses 88% of is preferable to have a deterministic interleaver,
a 1200 slice VIRTEX FPGA device and to reduce the hardware requirements for
delivers a satisfactory performance with a interleaving and de-interleaving operations. One
reduction in memory by 7.6% (for rate 1/2), of the goals of this paper is to propose a
40.9% (for rate 1/3) and with maximum net deterministic interleaver design to address this
delays much within the allowable limits of problem. In IS-95A CDMA architecture an
maximum data rate of 9.6Kbps. Intra-frame Rectangular Block interleaving is
performed on each frame length [5-6]. It writes
1. INTRODUCTION in column wise and reads out row wise. It
Cellular technology [1-2] has grown maintains 2 memory pages of size (16 x 24)
tremendously, both in its size of traffic and in each. When one is being written on, the other is
the amount of services it offers. It has become read out. Each page contains a single instance
an alternative to the traditional wireline of data for one 20 ms frame. The idea of block
telecommunication services. But, it is relatively rectangular interleaving is best expressed in
a new technology and hence has not attained Figure 1.
maturity to get globally standardized. One of
the most promising standards is the IS-95A 3. PROPOSED INTERLEAVER
CDMA. The IS-95A standard describes a Code For short block length interleavers,
Division Multiple Access (CDMA) system. The selection of the interleaver has a significant
advantages of IS-95A CDMA standard over effect on the performance of the Convolutional
other standards are Bandwidth Recycling, code. The randomness is much improved by
Efficient Power Control, Provision of Soft following proposed N mod M scheme and
handoffs, Multi Layered Diversity and thereby the burst errors can be reduced. The
Compatibility with variable rate vocoders [3-4]. mapping equation between the input and output
The forward link frequency is in the range of bit positions of the N mod M Interleaver with, x
(869-894) MHz and the reverse link frequency as the output bit position and F(x) as the
is in the range of (824-849) MHz. The forward corresponding input bit position is given by (1)
and reverse architectures are referred from [5- F(x) = (x*N) mod M (1)
6]. To ensure the squatness of the paper, the
 In IS-95A CDMA standard, the number The Viterbi decoder that decodes the
of bits in a page at anytime is a constant and is convolutionally encoded data from a
384 and hence M takes on the value of 385 to Convolutional encoder with rate 1/n, constraint
ensure a one-to-one mapping between the input length k and frame length L bits consists of the
and the output. The variable x takes on non- following three functional units as seen in
repeating values over [1,384]. By substituting Figure 2.
various values for N it is found that it is much • Encoder Engine
more efficient to use N=18 interleaving (that is • Branch metric generator
exemplified below) than to use the conventional • Add-Compare-Select (ACS) unit
Rectangular Interleaver. The mapping of the And three RAM Tables
proposed interleaver is given below. • Branch and Path Metric Memory
Output bit position = 10 • Present State Memory
Input bit position = (10*18) mod 385 • Survivor Memory
= 180. The encoder engine replicates the
Convolutional encoder at the receiver and
4. CONVOLUTIONAL DECODING calculates the next state and the output for the
The Viterbi algorithm is an extremely various given states and inputs simultaneously.
fast and efficient method to decode the coded This reduces the memory requirement of the
data obtained from the channel [9]. Viterbi entire trellis structure. 2*2(k-1)*n XOR
decoding has the advantage that it has a fixed operations are performed with the received n
decoding time but its computational bits and the generated output n bits at each of
requirements grow exponentially as a function the 2(k-1) states in the branch metric unit. Parallel
of the constraint length, so it is usually limited architecture is used to enhance the speed of the
in practice to a constraint lengths of K = 9 or decoder. The present state is obtained from the
less. present state memory. Output and branch metric
In the literature there has been much is calculated for input ‘1’ and ‘0’ and the path
interest in implementing the Viterbi decoder metric is calculated. These path metric values
using FPGAs the last 5 years. The recent related are stored in the two sets of registers in the Path
works reveal that the implementation of the metric memory, provided for storing them. The
Viterbi decoder on FPGA is certainly a branch metric, being manipulated in the
contemporary issue. In [10] the authors have previous block is added with the corresponding
implemented a Viterbi decoder with constraint path metric memory and is compared at each
length 7 using 4 XILINX 4028EX FPGAs. In state for either input and the state that ensures a
[11] a Viterbi decoder with constraint length 9 lower path metric is registered in the survivor
and speed near 19.2 Kbps is presented. In [12] path memory. At the (l+2)th time instant, the
another Viterbi decoder with constraint length 9 survivor path with the lowest metric value is
and speed 32Kbps is implemented using 2 retraced. At any instance t, ‘the survivor paths’
ALTERA Flex81500 FPGAs. Finally in [13] a final states are entered in the present state
Viterbi decoder with constraint length 14 and memory and are retrieved during survivor path
speed 41Kbps is implemented on 36 XILINX identification. Registers of length l are used in
XC4010 FPGAs. Conventional Viterbi survivor Memory Unit. The number of registers
decoders, those discussed above suffers from used is equal to the number of states (ie. 2(k-1))
the fact that they require enormous amount of in the Convolutional encoder. Each register is
memory. The memory wasted is due to the used for storing each survivor path.
storing up of error metric at each state and at The algorithm could be still improved
each level. The wastage can be avoided by the in a field where the probability of error could be
proposed scheme. pre-estimated. In such a case a threshold could
be fixed and if a path metric exceeds the
5. A NEW-FANGLED SCHEME FOR THE threshold, it could be eliminated, thereby
IMPLEMENTATION OF VITERBI conserving space and computation time.
DECODER
 6. RESULTS will work after fabrication. The paper will be
6.1. Simulation extended to 4G Technology in the near future
The comparison results between the and the design could be worked on reducing
conventional Interleaver and the proposed power consumption by adopting
Interleaver is tabulated in Table 1. In the table, transformations [15].
the first distance is the number of bit positions
by which the consecutive input bits are 8. REFERENCES
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Figure 1. Block Rectangular interleaving Figure 2 . Proposed Scheme for Viterbi

Decoding

Figure 3 . Comparison of the N mod M Interleavers

Figure 4. Comparison on the Memory requirement of the Proposed Viterbi Decoder with
the conventional Viterbi Decoders
Figure 5 . Simulation Results of the Proposed Viterbi Decoder and the Proposed
Interleaver

Figure 6 . FPGA Layout of transceiver Figure 7 . FPGA Layout of transceiver

at the Base Station at the Mobile Unit

Measuring Parameter Proposed Interleaver Block Rectangular

Interleaver
First Distance 106 23
Second Distance 170 47
Third Distance 63 71
Table 1 : Comparison Results of Proposed Interleaver

Implemented Architecture Maximum net delay Number of Slices

Transceiver at the Mobile Unit 10.6 x 10-6 s 1012
Transceiver at the Base station 11.2 x 10-6 s 1108
Table 2 : Chip Details