25LC080C 25LC320A

25LC080D 25LC640A
25LC160C 25LC128
25LC160D 25LC256
8K-256K SPI Serial EEPROM High Temp Family Data Sheet

Features: Description:
• Max. Clock 5 MHz Microchip Technology Inc. 25LCXXX* devices are Mid-
• Low-power CMOS Technology: density 8 through 256 Kbit Serial Electrically Erasable
- Max. Write Current: 5 mA at 5.5V, 5 MHz PROMs (EEPROM). The devices are organized in
blocks of x8-bit memory and support the Serial Periph-
- Read Current: 5 mA at 5.5V, 5 MHz
eral Interface (SPI) compatible serial bus architecture.
- Standby Current: 10 μA at 5.5V Byte-level and page-level functions are supported.
• 1024 x 8 through 32768 x 8-bit Organization
The bus signals required are a clock input (SCK) plus
• Byte and Page-level Write Operations separate data in (SI) and data out (SO) lines. Access to
• Self-timed Erase and Write Cycles (6 ms max.) the device is controlled through a Chip Select (CS)
• Block Write Protection: input.
- Protect none, 1/4, 1/2 or all of array Communication to the device can be paused via the
• Built-in Write Protection: hold pin (HOLD). While the device is paused, transi-
- Power-on/off data protection circuitry tions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
- Write enable latch
interrupts.
- Write-protect pin
The 25LCXXX is available in a standard 8-lead SOIC
• Sequential Read
package. The package is Pb-free.
• High Reliability:
- Endurance: >1M erase/write cycles Package Types (not to scale)
- Data retention: > 200 years
- ESD protection: > 4000V SOIC
• Temperature Range Supported: (SN)
- Extended (H): -40°C to +150°C CS 1 8 VCC
• Package is Pb-free and RoHS Compliant SO 2 7 HOLD
WP 3 6 SCK
Pin Function Table VSS 4 5 SI

Name Function

CS Chip Select Input

SO Serial Data Output
WP Write-Protect
VSS Ground
SI Serial Data Input
SCK Serial Clock Input
HOLD Hold Input
VCC Supply Voltage

*25LCXXX is used in this document as a generic part number for the 25 series devices.

© 2009 Microchip Technology Inc. Preliminary DS22131C-page 1

25LCXXX
Device Selection Table
Density Max Speed Page Size Temp.
Part Number Organization VCC Range Package
(bits) (MHz) (Bytes) Range

25LC080C 8K 1,024 x 8 2.5V - 5.5V 5 16 H SN

25LC080D 8K 1,024 x 8 2.5V - 5.5V 5 32 H SN
25LC160C 16K 2,048 x 8 2.5V - 5.5V 5 16 H SN
25LC160D 16K 2,048 x 8 2.5V - 5.5V 5 32 H SN
25LC320A 32K 4,096 x 8 2.5V - 5.5V 5 32 H SN
25LC640A 64K 8,192 x 8 2.5V - 5.5V 5 32 H SN
25LC128 128K 16,384 x 8 2.5V - 5.5V 5 64 H SN
25LC256 256K 32,768 x 8 2.5V - 5.5V 5 64 H SN

DS22131C-page 2 Preliminary © 2009 Microchip Technology Inc.

 25LCXXX
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V
Storage temperature ................................................................................................................................. -65°C to 155°C
Ambient temperature under bias........................................................................................................... -40°C to 150°C(1)
ESD protection on all pins.......................................................................................................................................... 4 kV

Note 1: AEC-Q100 reliability testing for devices intended to operate at 150°C is 1,000 hours. Any design in which
the total operating time between 125°C and 150°C will be greater than 1,000 hours is not warranted with-
out prior written approval from Microchip Technology Inc.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.

TABLE 1-1: DC CHARACTERISTICS

DC CHARACTERISTICS Extended (H): TA = -40°C to +150°C VCC = 2.5V to 5.5V

Param.
Sym. Characteristic Min. Max. Units Test Conditions
No.
D001 VIH1 High-level input .7 VCC VCC+1 V
voltage
D002 VIL1 Low-level input -0.3 0.3VCC V VCC ≥ 2.7V
D003 VIL2 voltage -0.3 0.2VCC V VCC < 2.7V
D004 VOL1 Low-level output — 0.4 V IOL = 2.1 mA
D005 VOL2 voltage — 0.2 V IOL = 1.0 mA
D006 VOH High-level output VCC -0.5 — V IOH = -400 μA
voltage
D007 ILI Input leakage current — ±2 μA CS = VCC, VIN = VSS OR VCC
D008 ILO Output leakage — ±2 μA CS = VCC, VOUT = VSS OR VCC
current
D009 CINT Internal Capacitance — 7 pF TA = 25°C, CLK = 1.0 MHz,
(all inputs and VCC = 5.0V (Note)
outputs)
D010 ICC Read — 5 mA VCC = 5.5V; FCLK = 5.0 MHz;
— SO = Open
Operating Current 2.5 mA VCC = 2.5V; FCLK = 3.0 MHz;
SO = Open
D011 ICC Write — 5 mA VCC = 5.5V
— 3 mA VCC = 2.5V
D012 ICCS Standby Current — 10 μA CS = VCC = 5.5V, Inputs tied to VCC or
VSS, 150°C
Note: This parameter is periodically sampled and not 100% tested.

© 2009 Microchip Technology Inc. Preliminary DS22131C-page 3

25LCXXX
TABLE 1-2: AC CHARACTERISTICS

AC CHARACTERISTICS Extended (H): TA = -40°C to +150°C VCC = 2.5V to 5.5V

Param.
Sym. Characteristic Min. Max. Units Test Conditions
No.

1 FCLK Clock Frequency — 5 MHz 4.5V ≤ Vcc ≤ 5.5V

— 3 MHz 2.5V ≤ Vcc < 4.5V
2 TCSS CS Setup Time 100 — ns 4.5V ≤ Vcc ≤ 5.5V
150 — ns 2.5V ≤ Vcc < 4.5V
3 TCSH CS Hold Time 200 — ns 4.5V ≤ Vcc ≤ 5.5V
250 — ns 2.5V ≤ Vcc < 4.5V
4 TCSD CS Disable Time 50 — ns —
5 Tsu Data Setup Time 20 — ns 4.5V ≤ Vcc ≤ 5.5V
30 — ns 2.5V ≤ Vcc < 4.5V
6 THD Data Hold Time 40 — ns 4.5V ≤ Vcc ≤ 5.5V
50 — ns 2.5V ≤ Vcc < 4.5V
7 TR CLK Rise Time — 2 μs (Note 1)
8 TF CLK Fall Time — 2 μs (Note 1)
9 THI Clock High Time 100 — ns 4.5V ≤ Vcc ≤ 5.5V
150 — ns 2.5V ≤ Vcc < 4.5V
10 TLO Clock Low Time 100 — ns 4.5V ≤ Vcc ≤ 5.5V
150 — ns 2.5V ≤ Vcc < 4.5V
11 TCLD Clock Delay Time 50 — ns —
12 TCLE Clock Enable Time 50 — ns —
13 TV Output Valid from Clock — 100 ns 4.5V ≤ Vcc ≤ 5.5V
Low — 160 ns 2.5V ≤ Vcc < 4.5V
14 THO Output Hold Time 0 — ns (Note 1)
15 TDIS Output Disable Time — 80 ns 4.5V ≤ Vcc ≤ 5.5V(Note 1)
— 160 ns 2.5V ≤ Vcc ≤ 4.5V(Note 1)
16 THS HOLD Setup Time 40 — ns 4.5V ≤ Vcc ≤ 5.5V
80 — ns 2.5V ≤ Vcc < 4.5V
17 THH HOLD Hold Time 40 — ns 4.5V ≤ Vcc ≤ 5.5V
80 — ns 2.5V ≤ Vcc < 4.5V
18 THZ HOLD Low to Output 60 — ns 4.5V ≤ Vcc ≤ 5.5V(Note 1)
High-Z 160 — ns 2.5V ≤ Vcc < 4.5V(Note 1)
19 THV HOLD High to Output 60 — ns 4.5V ≤ Vcc ≤ 5.5V
Valid 160 — ns 2.5V ≤ Vcc < 4.5V
20 TWC Internal Write Cycle Time — 6 ms (Note 2)
21 — Endurance 1,000,000 — E/W Page Mode, 25°C, VCC = 5.5V (Note 3)
Cycles
Note 1: This parameter is periodically sampled and not 100% tested.
2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.
3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from our web site:
www.microchip.com.

DS22131C-page 4 Preliminary © 2009 Microchip Technology Inc.

 25LCXXX
TABLE 1-3: AC TEST CONDITIONS
AC Waveform:
VLO = 0.2V —
VHI = VCC – 0.2V (Note 1)
VHI = 4.0V (Note 2)
CL = 50 pF —
Timing Measurement Reference Level
Input 0.5 VCC
Output 0.5 VCC
Note 1: For VCC ≤ 4.0V
2: For VCC > 4.0V

© 2009 Microchip Technology Inc. Preliminary DS22131C-page 5

25LCXXX
FIGURE 1-1: HOLD TIMING
CS
17 17
16 16

SCK
18 19
High-Impedance
SO n+2 n+1 n n n-1

Don’t Care 5
SI n+2 n+1 n n n-1

HOLD

FIGURE 1-2: SERIAL INPUT TIMING

CS 12
2 11
7
Mode 1,1 8 3

SCK Mode 0,0

5 6

SI MSB in LSB in

High-Impedance
SO

FIGURE 1-3: SERIAL OUTPUT TIMING

CS

9 10 3
Mode 1,1
SCK Mode 0,0
13
14 15

SO MSB out ISB out

Don’t Care
SI

DS22131C-page 6 Preliminary © 2009 Microchip Technology Inc.

 25LCXXX
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1. The WP pin function is blocked when the WPEN bit in
the STATUS register is low. This allows the user to
TABLE 2-1: PIN FUNCTION TABLE install the 25LCXXX in a system with WP pin grounded
and still be able to write to the STATUS register. The
Name Pin Number Function WP pin functions will be enabled when the WPEN bit is
set high.
CS 1 Chip Select Input
SO 2 Serial Data Output 2.4 Serial Input (SI)
WP 3 Write-Protect Pin The SI pin is used to transfer data into the device. It
VSS 4 Ground receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
SI 5 Serial Data Input
SCK 6 Serial Clock Input 2.5 Serial Clock (SCK)
HOLD 7 Hold Input
The SCK is used to synchronize the communication
VCC 8 Supply Voltage between a master and the 25LCXXX. Instructions,
addresses or data present on the SI pin are latched on
2.1 Chip Select (CS) the rising edge of the clock input, while data on the SO
A low level on this pin selects the device. A high level pin is updated after the falling edge of the clock input.
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
2.6 Hold (HOLD)
initiated or in progress will be completed, regardless of The HOLD pin is used to suspend transmission to the
the CS input signal. If CS is brought high during a 25LCXXX while in the middle of a serial sequence
program cycle, the device will go into Standby mode as without having to retransmit the entire sequence
soon as the programming cycle is complete. When the again. It must be held high any time this function is not
device is deselected, SO goes to the high-impedance being used. Once the device is selected and a serial
state, allowing multiple parts to share the same SPI sequence is underway, the HOLD pin may be pulled
bus. A low-to-high transition on CS after a valid write low to pause further serial communication without
sequence initiates an internal write cycle. After power- resetting the serial sequence. The HOLD pin must be
up, a low level on CS is required prior to any sequence brought low while SCK is low, otherwise the HOLD
being initiated. function will not be invoked until the next SCK high-to-
low transition. The 25LCXXX must remain selected
2.2 Serial Output (SO) during this sequence. The SI, SCK and SO pins are in
The SO pin is used to transfer data out of the a high-impedance state during the time the device is
25LCXXX. During a read cycle, data is shifted out on paused and transitions on these pins will be ignored.
this pin after the falling edge of the serial clock. To resume serial communication, HOLD must be
brought high while the SCK pin is low, otherwise serial
2.3 Write-Protect (WP) communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
This pin is used in conjunction with the WPEN bit in the
STATUS register to prohibit writes to the nonvolatile
bits in the STATUS register. When WP is low and
WPEN is high, writing to the nonvolatile bits in the STA-
TUS register is disabled. All other operations function
normally. When WP is high, all functions, including
writes to the nonvolatile bits in the STATUS register
operate normally. If the WPEN bit is set, WP low during
a STATUS register write sequence will disable writing
to the STATUS register. If an internal write cycle has
already begun, WP going low will have no effect on the
write.

© 2009 Microchip Technology Inc. Preliminary DS22131C-page 7

25LCXXX
3.0 FUNCTIONAL DESCRIPTION

3.1 Principles of Operation Block Diagram

The 25LCXXX are Mid-Density Serial EEPROMs STATUS
HV Generator
designed to interface directly with the Serial Peripheral Register
Interface (SPI) port of many of today’s popular micro-
controller families, including Microchip’s PIC® micro-
controllers. It may also interface with microcontrollers
that do not have a built-in SPI port by using discrete I/
O lines programmed properly in firmware to match the Memory EEPROM
I/O Control X
Control Array
SPI protocol. Logic
Logic Dec
The 25LCXXX contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being Page Latches
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation. SI
Table 3-1 contains a list of the possible instruction SO Y Decoder
bytes and format for device operation. All instructions, CS
addresses, and data are transferred MSB first, LSB SCK
last. HOLD Sense Amp.
R/W Control
Data (SI) is sampled on the first rising edge of SCK WP
after CS goes low. If the clock line is shared with other VCC
VSS
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25LCXXX in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.

TABLE 3-1: INSTRUCTION SET

Instruction Name Instruction Format Description
READ 0000 0011 Read data from memory array beginning at selected address
WRITE 0000 0010 Write data to memory array beginning at selected address
WRDI 0000 0100 Reset the write enable latch (disable write operations)
WREN 0000 0110 Set the write enable latch (enable write operations)
RDSR 0000 0101 Read STATUS register
WRSR 0000 0001 Write STATUS register

DS22131C-page 8 Preliminary © 2009 Microchip Technology Inc.

 25LCXXX
3.2 Read Sequence Once the write enable latch is set, the user may
proceed by setting the CS low, issuing a WRITE instruc-
The device is selected by pulling CS low. The 8-bit tion, followed by the 16-bit address, and then the data
READ instruction is transmitted to the 25LCXXX fol- to be written. Depending upon the density, a page of
lowed by the 16-bit address. After the correct READ data that ranges from 16 bytes to 64 bytes can be sent
instruction and address are sent, the data stored in the to the device before a write cycle is necessary. The only
memory at the selected address is shifted out on the restriction is that all of the bytes must reside in the
SO pin. The data stored in the memory at the next same page.
address can be read sequentially by continuing to pro-
vide clock pulses. The internal Address Pointer is auto- Note: Page write operations are limited to writing
matically incremented to the next higher address after bytes within a single physical page,
each byte of data is shifted out. When the highest regardless of the number of bytes
address is reached, the address counter rolls over to actually being written. Physical page
address 0000h allowing the read cycle to be continued boundaries start at addresses that are
indefinitely. The read operation is terminated by raising integer multiples of the page buffer size (or
the CS pin (Figure 3-1). ‘page size’) and, end at addresses that are
integer multiples of page size – 1. If a
3.3 Write Sequence Page Write command attempts to write
across a physical page boundary, the
Prior to any attempt to write data to the 25LCXXX, the result is that the data wraps around to the
write enable latch must be set by issuing the WREN beginning of the current page (overwriting
instruction (Figure 3-4). This is done by setting CS low data previously stored there), instead of
and then clocking out the proper instruction into the being written to the next page as might be
25LCXXX. After all eight bits of the instruction are expected. It is therefore necessary for the
transmitted, the CS must be brought high to set the application software to prevent page write
write enable latch. If the write operation is initiated operations that would attempt to cross a
immediately after the WREN instruction without CS page boundary.
being brought high, the data will not be written to the For the data to be actually written to the array, the CS
array because the write enable latch will not have been must be brought high after the Least Significant bit (D0)
properly set. of the nth data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-2 and Figure 3-3
for more detailed illustrations on the byte write
sequence and the page write sequence, respectively.
While the write is in progress, the STATUS register may
be read to check the status of the WPEN, WIP, WEL,
BP1 and BP0 bits (Figure 3-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.

FIGURE 3-1: READ SEQUENCE

CS

0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK

Instruction 16-bit Address

SI 0 0 0 0 0 0 1 1 15 14 13 12 2 1 0

Data Out
High-Impedance
SO 7 6 5 4 3 2 1 0

© 2009 Microchip Technology Inc. Preliminary DS22131C-page 9

25LCXXX
FIGURE 3-2: BYTE WRITE SEQUENCE

CS
Twc
0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction 16-bit Address Data Byte
SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0

High-Impedance
SO

FIGURE 3-3: PAGE WRITE SEQUENCE

CS

0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction 16-bit Address Data Byte 1
SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0

CS

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
Data Byte 2 Data Byte 3 Data Byte n (16/32/64 max)

SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

DS22131C-page 10 Preliminary © 2009 Microchip Technology Inc.

 25LCXXX
3.4 Write Enable (WREN) and Write The following is a list of conditions under which the
Disable (WRDI) write enable latch will be reset:
• Power-up
The 25LCXXX contains a write enable latch. See
Table 5-1 for the write-protect functionality matrix. This • WRDI instruction successfully executed
latch must be set before any write operation will be com- • WRSR instruction successfully executed
pleted internally. The WREN instruction will set the latch, • WRITE instruction successfully executed
and the WRDI will reset the latch.

FIGURE 3-4: WRITE ENABLE SEQUENCE (WREN)

CS

0 1 2 3 4 5 6 7
SCK

SI 0 0 0 0 0 1 1 0

High-Impedance
SO

FIGURE 3-5: WRITE DISABLE SEQUENCE (WRDI)

CS

0 1 2 3 4 5 6 7
SCK

SI 0 0 0 0 0 1 10 0

High-Impedance
SO

© 2009 Microchip Technology Inc. Preliminary DS22131C-page 11

25LCXXX
3.5 Read Status Register Instruction The Write Enable Latch (WEL) bit indicates the status
(RDSR) of the write enable latch and is read-only. When set to
a ‘1’, the latch allows writes to the array, when set to a
The Read Status Register instruction (RDSR) provides ‘0’, the latch prohibits writes to the array. The state of
access to the STATUS register. The STATUS register this bit can always be updated via the WREN or WRDI
may be read at any time, even during a write cycle. The commands regardless of the state of write protection
STATUS register is formatted as follows: on the STATUS register. These commands are shown
in Figure 3-4 and Figure 3-5.
TABLE 3-2: STATUS REGISTER The Block Protection (BP0 and BP1) bits indicate
7 6 5 4 3 2 1 0 which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
W/R – – – W/R W/R R R
bits are nonvolatile, and are shown in Table 3-3.
WPEN X X X BP1 BP0 WEL WIP
See Figure 3-6 for the RDSR timing sequence.
W/R = writable/readable. R = read-only.
The Write-In-Process (WIP) bit indicates whether the
25LCXXX is busy with a write operation. When set to a
‘1’, a write is in progress, when set to a ‘0’, no write is
in progress. This bit is read-only.

FIGURE 3-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR)

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SCK

Instruction

SI 0 0 0 0 0 1 0 1

Data from STATUS Register

High-Impedance
SO 7 6 5 4 3 2 1 0

DS22131C-page 12 Preliminary © 2009 Microchip Technology Inc.

 25LCXXX
3.6 Write Status Register Instruction The Write-Protect Enable (WPEN) bit is a nonvolatile
(WRSR) bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
The Write Status Register instruction (WRSR) allows the (WPEN) bit in the STATUS register control the
user to write to the nonvolatile bits in the STATUS programmable hardware write-protect feature. Hard-
register as shown in Table 3-2. The user is able to ware write protection is enabled when WP pin is low
select one of four levels of protection for the array by and the WPEN bit is high. Hardware write protection is
writing to the appropriate bits in the STATUS register. disabled when either the WP pin is high or the WPEN
The array is divided up into four segments. The user bit is low. When the chip is hardware write-protected,
has the ability to write-protect none, one, two or all four only writes to nonvolatile bits in the STATUS register
of the segments of the array. The partitioning is are disabled. See Table 5-1 for a matrix of functionality
controlled as shown in Table 3-3. on the WPEN bit.
See Figure 3-7 for the WRSR timing sequence.

TABLE 3-3: ARRAY PROTECTION

Array Addresses Array Addresses

BP1 BP0
Write-Protected Unprotected
0 0 None All
0 1 Upper 1/4 Lower 3/4
1 0 Upper 1/2 Lower 1/2
1 1 All None

TABLE 3-4: ARRAY PROTECTED ADDRESS LOCATIONS

Density Upper 1/4 Upper 1/2 All

8K 300h - 3FFh 200h - 3FFh 000h - 3FFh
16K 600h - 7FFh 400h - 7FFh 000h - 7FFh
32K C00h - FFFh 800h - FFFh 000h - FFFh
64K 1800h - 1FFFh 1000h - 1FFFh 0000h - 1FFFh
128K 3000h - 3FFFh 2000h - 3FFFh 0000h - 3FFFh
256K 6000h - 7FFFh 4000h - 7FFFh 0000h - 7FFFh

FIGURE 3-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SCK

Instruction Data to STATUS Register

SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0

High-Impedance
SO

Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register
sequence.

© 2009 Microchip Technology Inc. Preliminary DS22131C-page 13

25LCXXX
4.0 DATA PROTECTION 5.0 POWER-ON STATE
The following protection has been implemented to The 25LCXXX powers on in the following state:
prevent inadvertent writes to the array: • The device is in low-power Standby mode
• The write enable latch is reset on power-up (CS = 1)
• A write enable instruction must be issued to set • The write enable latch is reset
the write enable latch • SO is in high-impedance state
• After a byte write, page write or STATUS register • A high-to-low-level transition on CS is required to
write, the write enable latch is reset enter active state
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued

TABLE 5-1: WRITE-PROTECT FUNCTIONALITY MATRIX

WEL WPEN WP
Protected Blocks Unprotected Blocks STATUS Register
(SR bit 1) (SR bit 7) (pin 3)
0 x x Protected Protected Protected
1 0 x Protected Writable Writable
1 1 0 (low) Protected Writable Protected
1 1 1 (high) Protected Writable Writable
x = don’t care

DS22131C-page 14 Preliminary © 2009 Microchip Technology Inc.

 25LCXXX
6.0 PACKAGING INFORMATION

6.1 Package Marking Information

8-Lead SOIC Example:

XXXXXXXT 25LC32AH
XXXXYYWW SN e3 0728
NNN 1L7

8-Lead SOIC Package Marking (Pb-Free)

Device Line 1 Marking

25LC080C 25LC80CT
25LC080D 25LC80DT
25LC160C 25LC16CT
25LC160D 25LC16DT
25LC320A 25LC32AT
25LC640A 25L640AT
25LC128 25LC128T
25LC256 25LC256T
Note 1: T = Temperature Grade (H).

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

Note: Custom marking available.

© 2009 Microchip Technology Inc. Preliminary DS22131C-page 15

25LCXXX


 


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DS22131C-page 16 Preliminary © 2009 Microchip Technology Inc.

 25LCXXX


 


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© 2009 Microchip Technology Inc. Preliminary DS22131C-page 17

25LCXXX
REVISION HISTORY

Revision A (01/2009)
Original Release.

Revision B (04/2009)
Revised part number from 25XX to 25LCXXX; Added
Note 1 to Electrical Characteristics.

Revision C (06/2009)
Revised Features: Endurance and Package; Revised
Table 1-2, Para. 21.

DS22131C-page 18 Preliminary © 2009 Microchip Technology Inc.

 25LCXXX
THE MICROCHIP WEB SITE CUSTOMER SUPPORT
Microchip provides online support via our WWW site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the web site contains the following informa-
tion: • Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata, appli-
cation notes and sample programs, design • Development Systems Information Line
resources, user’s guides and hardware support Customers should contact their distributor, representa-
documents, latest software releases and archived tive or field application engineer (FAE) for support.
software Local sales offices are also available to help custom-
• General Technical Support – Frequently Asked ers. A listing of sales offices and locations is included in
Questions (FAQ), technical support requests, the back of this document.
online discussion groups, Microchip consultant Technical support is available through the web site
program member listing at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Micro-
chip sales offices, distributors and factory repre-
sentatives

CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a spec-
ified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change Notifi-
cation and follow the registration instructions.

© 2009 Microchip Technology Inc. Preliminary DS22131C-page 19

25LCXXX
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager Total Pages Sent ________

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From: Name
Company
Address
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Application (optional):
Would you like a reply? Y N

Device: 25LCXXX Literature Number: DS22131C

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS22131C-page 20 Preliminary © 2009 Microchip Technology Inc.

 25LCXXX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X – X /XX
Examples:
Device Tape & Reel Temp Range Package a) 25LC080CT-H/SN = 8k-bit, 16-byte page, 2.5V
Serial EEPROM, Extended temp., Tape &
Reel, SOIC package
Device: 25LC080C = 8k-bit, 2.5V, 16 Byte Page, SPI Serial EEPROM b) 25LC080D-H/SN = 8k-bit, 32-byte page, 2.5V
25LC080D = 8k-bit, 2.5V, 32 Byte Page, SPI Serial EEPROM Serial EEPROM, Extended temp., SOIC pack-
25LC160C = 16k-bit, 2.5V, 16 Byte Page, SPI Serial EEPROM age
25LC160D = 16k-bit, 2.5V, 32 Byte Page, SPI Serial EEPROM c) 25LC160CT-H/SN = 16k-bit, 16-byte page,
25LC320A = 32k-bit, 2.5V, 32 Byte Page, SPI Serial EEPROM 2.5V Serial EEPROM, Extended temp., Tape &
25LC640A = 64k-bit, 2.5V, 32 Byte Page, SPI Serial EEPROM Reel, SOIC package
25LC128 = 128k-bit, 2.5V, 64 Byte Page, SPI Serial EEPROM d) 25LC160D-H/SN = 16k-bit, 32-byte page, 2.5V
25LC256 = 256k-bit, 2.5V, 64 Byte Page, SPI Serial EEPROM Serial EEPROM, Extended temp., SOIC pack-
age
Tape & Reel: Blank = Standard packaging
T = Tape & Reel e) 25LC320AT-H/SN = 32k-bit, 32-byte page,
2.5V Serial EEPROM, Extended temp., Tape &
Temperature H = -40°C to+150°C Reel, SOIC package
Range: f) 25LC640A-H/SN = 64k-bit, 32-byte page, 2.5V
Serial EEPROM, Extended temp., SOIC pack-
age
Package: SN = Plastic SOIC (3.90 mm body), 8-lead g) 25LC128T-H/SN = 128k-bit, 64-byte page,
2.5V Serial EEPROM, Extended temp., Tape &
Reel, SOIC package
h) 25LC256-H/SN = 256k-bit, 64-byte page, 2.5V
Serial EEPROM, Extended temp., SOIC pack-
age

© 2009 Microchip Technology Inc. Preliminary DS22131C-page 21

25LCXXX
NOTES:

DS22131C-page 22 Preliminary © 2009 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
rfPIC and UNI/O are registered trademarks of Microchip
MICROCHIP MAKES NO REPRESENTATIONS OR
Technology Incorporated in the U.S.A. and other countries.
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
OTHERWISE, RELATED TO THE INFORMATION, MXDEV, MXLAB, SEEVAL and The Embedded Control
INCLUDING BUT NOT LIMITED TO ITS CONDITION, Solutions Company are registered trademarks of Microchip
QUALITY, PERFORMANCE, MERCHANTABILITY OR Technology Incorporated in the U.S.A.
FITNESS FOR PURPOSE. Microchip disclaims all liability Analog-for-the-Digital Age, Application Maestro, CodeGuard,
arising from this information and its use. Use of Microchip dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
devices in life support and/or safety applications is entirely at ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
the buyer’s risk, and the buyer agrees to defend, indemnify and Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
hold harmless Microchip from any and all damages, claims, Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP,
suits, or expenses resulting from such use. No licenses are Omniscient Code Generation, PICC, PICC-18, PICkit,
conveyed, implicitly or otherwise, under any Microchip PICDEM, PICDEM.net, PICtail, PIC32 logo, REAL ICE, rfLAB,
intellectual property rights. Select Mode, Total Endurance, TSHARC, WiperLock and
ZENA are trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

© 2009 Microchip Technology Inc. Preliminary DS22131C-page 23

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Fax: 905-673-6509

03/26/09

DS22131C-page 24 Preliminary © 2009 Microchip Technology Inc.