Digital Integrated

Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic

The Wire
July 30, 2002
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 The Wire

1. An increase in propagation delay, or,

equivalently, a drop in performance.
2. An impact on the energy dissipation
and the power distribution.
3. An introduction of extra noise sources,
which affects the reliability of the
circuit.

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 The Wire

transmitters receivers

schematics physical

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 The Wire
Simplifications in analyzing schematics:

 Inductive effects can be ignored if the resistance of

the wire is substantial.
 When the wires are short, the cross-section of the
wire is large, or the interconnect material used has a
low resistivity, a capacitance-only model can be used.
 When the separation between neighboring wires is
large, or when the wires only run together for a short
distance, inter-wire capacitance can be ignored, and
all the parasitic capacitance can be modeled as
capacitance to ground.
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 Interconnect Impact on Chip

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 Wire Models

All-inclusive model Capacitance-only

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 Impact of Interconnect Parasitics

 Interconnect parasitics
 reduce reliability
 affect performance and power consumption
 Classes of parasitics
 Capacitive
 Resistive
 Inductive

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Nature of Interconnect

Local Interconnect Pentium Pro (R)

Pentium(R) II
Pentium (MMX)
Pentium (R)
Pentium (R) II

Global Interconnect
(Log Scale)
No of nets

SGlobal = SDie
SLocal = STechnology

Source: Intel
10 100 1,000 10,000 100,000
Length (u)
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 INTERCONNECT

Capacitance

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Capacitance of Wire Interconnect
VDD VDD

M2
Cdb2 Cg4 M4
Cgd12
Vin Vout Vout2

Cdb1 Cw Cg3
M1 M3
Interconnect

Fanout
Vin Vout
Simplified
Model CL

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Capacitance: The Parallel Plate Model

Current flow

W Electrical-field lines

tdi Dielectric

Substrate

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 Capacitance: The Parallel Plate Model

cint - Total Capacitance

t di - Thickness of the dielectric

 di  di Layer

cint 
- Permittivity of the dielectric
WL W Layer
tdi L - Width of the wire
- Length of the wire

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 Permittivity

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Fringing Capacitance
The fringing-field capacitance. The
model decomposes the capacitance
into two contributions: a parallel-plate
capacitance, and a fringing
capacitance, modeled by a
cylindrical wire with a diameter equal
to the thickness of the wire.

(a)

H W - H/2

(b)
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Fringing versus Parallel Plate

For larger values of (W/H) the

total capacitance approaches the
parallel-plate model. For (W/H)
smaller than 1.5, the fringing
component actually becomes the
dominant component.

(from [Bakoglu89])
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Interwire Capacitance

fringing parallel

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Impact of Interwire Capacitance

Interconnect capacitance as a
function of design rules. It
consists of a capacitance to
ground and an inter-wire
capacitance

(from [Bakoglu89])

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 Wiring Capacitances (0.25 mm CMOS)

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 INTERCONNECT

Resistance

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 Wire Resistance

 The resistance of a wire is proportional

to its length L and inversely proportional
to its cross-section A.

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Wire Resistance

R= L
HW

L Sheet Resistance
H Ro

R1 R2
W

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Interconnect Resistance

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 Sheet Resistance

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Polycide Gate MOSFET
Silicide

PolySilicon

SiO2

n+ n+
p

Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi

Conductivity: 8-10 times better than Poly

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 Dealing with Resistance

 SelectiveTechnology Scaling
 Use Better Interconnect Materials
 reduce average wire-length
 e.g. copper, silicides
 More Interconnect Layers
 reduce average wire-length

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 Modern Interconnect

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 Example: Intel 0.25 micron Process

5 metal layers
Ti/Al - Cu/Ti/TiN
Polysilicon dielectric

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 INTERCONNECT

Inductance

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 Inductance

Consequences of on-chip inductance:

 Ringing and overshoot effects
 Reflections of signals due to impedance
mismatch
 Inductive coupling between lines
 Switching Noise due to voltage drops

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 Inductance

 The inductance of a section of a circuit

can always be evaluated with the aid of
its definition, which states that a
changing current passing through an
inductor generates a voltage drop V

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 Electric Wire
Models

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 The Ideal Wire

 Simplistic, concentrates on the

properties and the behavior of the
transistors that are being connected.
 Wires tend to be short and their
parasitics ignorable.

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 The Lumped Model

 The circuit parasitics of a wire are distributed

along its length and are not lumped into a
single position.
 Yet, when only a single parasitic component
is dominant, when the interaction between
the components is small, or when looking at
only one aspect of the circuit behavior, it is
often useful to lump the different fractions into
a single circuit element.

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 The Lumped Model
Vo ut

cwi re
Driver

Distributed versus lumped

capacitance model of wire.
Clumped = Lcwire, with L the
Rdriver
Vout length of the wire and cwire the
capacitance per unit length. The
Vin
driver is modeled as a voltage
Clumped source and a source resistance
Rdriver.

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 The Lumped RC Model

 A first approach lumps the total wire

resistance of each wire segment into one
single R and similarly combines the global
capacitance into a single capacitor C.

 Inaccurate for long interconnect wires.

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 The Lumped RC Model

 The distributed rc-model is complex and no

closed form solutions exist. The behavior of
the distributed rc-line can be adequately
modeled by a simple RC network.

 A common practice in the study of the

transient behavior of complex transistor-wire
networks is to reduce the circuit to an RC
network.

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 The Lumped RC-Model
The Elmore Delay

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 The Lumped RC-Model
The Elmore Delay
Properties:
 the network has a single input node
 all the capacitors are between a node
and the ground
 the network does not contain any
resistive loops

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 The Ellmore Delay
RC Chain

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 The Ellmore Delay
RC Chain

Assume: Wire modeled by N equal-length segments

For large values of N:

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 The Ellmore Delay
RC Chain
Conclusion:
 The delay of a wire is a quadratic function
of its length. This means that doubling the
length of the wire quadruples its delay.

 The delay of the distributed rc-line is one half

of the delay that would have been predicted
by the lumped RC model.

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 The Distributed RC Line

 More appropriate model for longer

interconnect wires.

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The Distributed RC-line

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 Step-response of RC wire as a
function of time and space
2.5

x= L/10
2

x = L/4
voltage (V)

1.5

x = L/2
1
x= L
0.5

0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
time (nsec)

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 RC-Models

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 Driving an RC-line
Rs (r w,cw,L)
Vout

Vin

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 Design Rules of Thumb

 rc delays should only be considered when

tpRC >> tpgate of the driving gate
Lcrit >>  tpgate/0.38rc
 rc delays should only be considered when the
rise (fall) time at the line input is smaller than
RC, the rise (fall) time of the line
trise < RC
 when not met, the change in the signal is slower
than the propagation delay of the wire

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 Perspective: A look into the Future

 Similar to the approach we followed for the

MOS transistor, it is worthwhile to explore
how the wire parameters will evolve with
further scaling of the technology. As transistor
dimensions are reduced, the interconnect
dimensions must also be reduced to take full
advantage of the scaling process.

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 Perspective: A look into the Future

Ideal scaling
 Local interconnections can be scaled in
the same way as transistors.
 However, global interconnections
display a different kind of scaling
behavior.

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 Perspective: A look into the Future

Distribution of wire
lengths in an advanced
microprocessor as a
function of the gate
pitch.

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 Perspective: A look into the Future

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