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CSE 205 Digital Logic Design: Dr. Mahmuda Naznin

This lecture covered don't-care conditions, gate-level minimization using maps, and implementation of logic functions using NAND and NOR gates. It discussed how to simplify Boolean functions using don't-care conditions and how to convert logic functions represented as sums of products or products of sums into their NAND or NOR gate implementations through standard rules. Multilevel NAND and NOR circuits were also introduced along with their implementation rules.

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58 views23 pages

CSE 205 Digital Logic Design: Dr. Mahmuda Naznin

This lecture covered don't-care conditions, gate-level minimization using maps, and implementation of logic functions using NAND and NOR gates. It discussed how to simplify Boolean functions using don't-care conditions and how to convert logic functions represented as sums of products or products of sums into their NAND or NOR gate implementations through standard rules. Multilevel NAND and NOR circuits were also introduced along with their implementation rules.

Uploaded by

asbul
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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CSE 205

Digital Logic Design

Lecture 3
Dr. Mahmuda Naznin
This Lecture
• Review of last lecture: Gate-Level
Minimization
• Continue Chapter 3:Don’t-Care Conditions,
Implementation

2
Gate-Level Minimization
• The Map Method:
• A simple method for minimizing Boolean
functions

• Map: diagram made up of squares


• Each square represents a minterm

3
Three-Variable Map

Each variable is 1 in 4 squares, 0 in 4 squares


Variable appears unprimed in squares equal to 1
Variable appears primed in squares equal to 0

4
Four-Variable Map

5
Five-Variable Map

Maps for more than four variables are not easy to use.

Five-variable maps require 32 squares.

Alternative: Use two four-variable maps to make a five-variable one

Minterms 0 to 15 in one map. 16 to 31 in the other one.

6
Five-Variable Map
Each square in the A=0 map is adjacent to the corresponding one in the A=1 map.

7
0’s in the map

For a function F, combining the 0 squares gives us F’.

By using F’ and the DeMorgan’s law, we can simplify the function to product of sums.

F’=AB+CD+BD’

8
Gate implementation-example 4

SUM of Products Products of Sums

9
Don’t-Care Conditions
• There are applications that the function is not
specified for certain combinations and
variables.

• Mark don’t-cares with X, assume either 1 or 0


to simplify the function.

10
Don’t-Care Conditions

Simplify the Boolean function F(w,x,y,z)=Σ(1,3,7,11,15) which has the don’t-care conditions
d(w,x,y,z)= Σ(0,2,5)

11
NAND and NOR implementations

Ease of fabrication:

Digital circuits are made of NAND or NOR, rather than AND and OR gates.

We need rules to convert from AND/OR/NOT to NAND/NOR circuits.

NAND gate is a universal gate because any digital circuit can be implemented using it.

12
Graphic symbols for NAND gates

13
Two-Level Implementation

Three implementations for A.B+C.D

14
Example

Implement the following function with NAND gates: F(x,y,z)=(1,2,3,4,5,7)

15
Multilevel NAND circuits
• Sum of Products and Product of Sums result in two level
designs

• Not all designs are of two-levels e.g., F=A.(C.D+B)+B.C’

• How do we convert multilevel circuits to NAND circuits?

Rules
• 1-Convert all ANDs to NAND gates with AND-invert
• 2-Convert all ORs to NAND gates with invert-OR
• 3-Check the bubbles, insert bubble if not compensated

16
Multilevel NAND circuits

BC’

17
Multilevel NAND circuits

18
NOR implementation
NOR is NAND dual so all NOR rules are dual of NAND rules.

All designs can be made by NORs

19
NOR symbols

NOR implementation requires the function expressed in product of sums

NOR implementation Rules


1-Convert all ORs to NOR gates with OR-invert symbol
2-Convert all ANDs to NOR gates with invert-AND symbols
3-Check the bubbles, insert bubble

20
NOR circuits

21
NAND and NOR gate

22
Summary
• NAND and NOR implementations

• Gate-level Minimization, Implementation

23

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