FAKULTI KEJURUTERAAN ELEKTRIK

UNIVERSITI TEKNOLOGI MALAYSIA

SEEU1223 Exercise for Test 2

1. Draw the block diagram of a 2-to-1 multiplexer, obtain the minimize SOP and
POS expressions and implement the circuit in NOR-NOR and NAND-NAND
configurations.

2. (i) Analyse the circuit and obtain the Boolean function F(A,B).

0 I0
F(A,B)
A I1
S0

(ii) Show how a NOT function can be implemented using a single 2-to-1
multiplexer.

3. (a) Implement a Boolean function F(A,B,C,D) =  m (1,4,6,7,8,9,10,11) using

8-to-1 multiplexer.
(b) When the circuit in (a) is built and tested using 74151 chip, the output of
the multiplexer gives
(i) LOW reading for all the input combinations. [VCC and GND are
properly connected and wiring connections are all good]
(ii) complemented values of the function.
What could be the reason for each case?

4. Analyse the circuit and obtain the maxterm expression F(A,B,C,D) =  M ( ).

C
I0
D I1 4-1
1
I2 MUX F
0 I3
S1 S0

A B
5. A Boolean function F(A,B,C) = (A  B).( B  C) . Implement the function using a
4-to-1 multiplexer and other logic gates if necessary.

6. A function F(A,B,C) is implemented using 2-to-1 multiplexer with logic gates.

Obtain the truth table for F and re-implement the function using a 4-to-1
multiplexer with other logic gates if necessary.

C
I0
B F
I1
S0

7. A 6-segment display is used to show the directions of North, South, East and
West. A decoder is connected to the display. Design the decoder using one 7486
integrated circuit chip only. A 7486 chip has four 2-input Exclusive-OR gates.

a b a b b a
e e e

f f f
d c d c c d

north south east west

a
a b S1 S0 direction
b e
S1 0 0 north
c
S0 d f 0 1 south
e d c 1 0 east
f 1 1 west

8. A BCD to 7-segment display decoder is connected to a 7-segment display.

a a
B3 b
c f b
B2 g
d
B1 e
e c
B0 f
g
d

BCD to 7-segment 7-segment display

display decoder
 (i) For an active-HIGH output decoder connected to a common-cathode
display, which segments will light-up if the input B3B2B1B0 = 0101?
(ii) For an active-LOW output decoder, which outputs of the decoder will be
HIGH if B3B2B1B0 = 1001?
(iii) Which segments of the display will light-up when B3B2B1B0 = 0011 if an
active-HIGH output decoder is connected to a common-anode display?

9. A Boolean function is implemented using a 74138 decoder. Implement the same

function using 4-1 multiplexer.

1 G1 O0
0 G2A O1
0 G2B O2 I0
O3 I1
F F
O4 I2
A S2 I3
O5 S1 S0
B S1
O6
C S0
O7 A B

10. The diagram shows the logic symbol of a 2 by 2 multiplier and how the
multiplication process is done. Implement the circuit using half-adders and AND
gates only.
A1 A0

A1 O3 X B1 B0
A0 O2
carry2 carry1 A1B0 A0B0
B1 O1 A1B1 A0B1
B0
O0
carry2 carry1 A1B0 A0B0
+ A1B1 + A0B1

(O3) (O2) (O1) (O0)

11. The following shows a 4-1 multiplexer with a D flip-flop. Show how these two
devices can be connected to become a J-K flip-flop. The J and K inputs are
connected to the select bits S1 and S0 respectively. You can't use any additional
gates.
 I0 D0 Q0
I1
I2 F
I3 Q0
S1 S0

12. Three flip-flops are connected and subjected to clock and input signals. Complete
the timing diagram for the three outputs. All the outputs are initially 0.

signal 1 J Q output 1

clock

signal 2 K

D Q output 2

T Q output 3

clock

signal 1

signal 2

output 1

output 2

output 3
13. (i) What is the difference between a synchronous input and an asynchronous
input?
(ii) A J-K flip-flop is shown in the following diagram. Identify which inputs
are synchronous and which are asynchronous.

J PRE Q

CLK

K Q
CLR

14. The input and output logic levels for a 3.3 V CMOS logic family are shown.
(i) Calculate the HIGH-level (VNH) and LOW-level (VNL) noise margins.
(ii) Explain the existence of unallowed regions.

input output
3.3 V VIH(max) 3.3 V VOH(max)
Logic 1
Logic 1
2.4 V VOH(min)
2V VIH(min)
unallowed unallowed

0.8 V VIL(max)
Logic 0 0.4 V VOL(max)
Logic 0
0V VIL(min) 0V VOL(min)