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Activity 2 CPE07

The Von Neumann architecture uses a single memory for both instructions and data, allowing the processor to fetch instructions and access data with a single clock cycle. However, it is slower than the Harvard architecture. The Harvard architecture uses separate memories and buses for instructions and data, allowing simultaneous access and faster single clock cycle processing. However, it has a more complex design. Digital signal processors and microcontrollers often use the Harvard architecture for its speed advantages in processing instructions and data concurrently. Overall, the Von Neumann architecture is preferable for its simpler, more cost effective design despite being slower.

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Ralstine Jane Igne
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62 views3 pages

Activity 2 CPE07

The Von Neumann architecture uses a single memory for both instructions and data, allowing the processor to fetch instructions and access data with a single clock cycle. However, it is slower than the Harvard architecture. The Harvard architecture uses separate memories and buses for instructions and data, allowing simultaneous access and faster single clock cycle processing. However, it has a more complex design. Digital signal processors and microcontrollers often use the Harvard architecture for its speed advantages in processing instructions and data concurrently. Overall, the Von Neumann architecture is preferable for its simpler, more cost effective design despite being slower.

Uploaded by

Ralstine Jane Igne
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Activity # 2:

Instruction. Please answer the following questions in your own words.

1. Describe the Von-Neumann Architecture and how it works?

John von Neumann is a mathematician who introduces the idea of stored


program computer in the 1940s that we now call as Von-Neumann Architecture.
This architecture based on the stored-program computer concept, where the
instruction data and program data are stored in the same memory. The
computers operate using four simple steps, called as the “Machine Cycle”.

a. Fetch. The first step is to get the instructions from the Ram and puts them
in the cache for the Control Unit gets access with the data
b. Decode. The Control Unit decodes the instructions into a form the
Arithmetic Logic Unit can understand and feeds them to the Arithmetic
logic unit.
c. Execute. The Arithmetic logic unit executes the instructions, and outputs
the results to the cache.
d. Store. Once the program counter says stop, the result is offloaded to the
main memory.

2. Describe the Harvard Architecture and how it works?

The Harvard Architecture offers separate storage and signal buses for
instructions and data. The architecture has data storage entirely contained
within the CPU, and there is no access to the instruction storage as data.
Computers have separate memory areas for program instructions and data
using internal data buses, allowing simultaneous access to both instructions
and data. Programs needed to be loaded by an operator; the processor could
not boot itself. In a Harvard Architecture, there is no need to make the two
memories share properties.
3. What is the difference between Von-Neumann architecture and Harvard
architecture?

There are a lot of difference between the Von-Neumann


architecture and Harvard architecture. Von-Neumann Architecture has a
single memory to be shared by both code and data. Processors needs to
fetch code in a separate clock cycle and data in another clock cycle, so it
requires two clock cycles. Higher speed, thus less time consuming and
simple in design. On the other hand, Harvard Architecture has separate
memories for code and data. Single clock cycle is sufficient, as separate
buses are used to access code and data. Slower in speed, thus more
time-consuming. Complex in design.

4. What devices uses Harvard architecture?

Digital Signal processors (DSP) generally execute small, highly


optimized audio or video processing algorithms. They avoid caches
because their behavior must be extremely reproducible. The difficulties of
coping with multiple address spaces are of secondary concern to speed of
execution. Consequently, some DSPs feature multiple data memories in
distinct address spaces to facilitate SIMD (Single Instruction, Multiple
Data) and VLIW (Very Long Instruction Word) processing. Texas
instruments TMS320 C55x processors, for one example, feature
multiple parallel data buses (two write, three read) and one instruction
bus.

Microcontrollers characterized by having small amounts of program


and data memory, and take advantage of the Harvard architecture to
speed processing by concurrent instruction and data access. The
separate storage means the program and data memories may feature
different bit widths, for example using 16-bit-wide instructions and 8-bit-
wide data. They also mean that instruction pre-fetch performed in parallel
with other activities. Example include the PIC by Microchip Technology,
Inc. and the AVR by Atmel Corp (now part of Microchip Technology.)

5. Which is better? Von-Neumann Architecture or Harvard architecture.

I will choose Von-Neumann Architecture since it requires less


hardware and only a common memory needed in this architecture. It
requires less space and it is budget friendly. The design is also simple
rather than the Harvard Architecture has complex design.

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