®

ISL6596

Data Sheet November 2, 2005 FN9240.0

Synchronous Rectified MOSFET Driver Features

The ISL6596 is a high frequency, MOSFET driver optimized • Drives Two N-Channel MOSFETs
to drive two N-Channel power MOSFETs in a synchronous
• Adaptive Shoot-Through Protection
buck converter topology. This driver combined with Intersil’s
Multi-Phase Buck PWM controllers forms a complete single- • 0.4Ω On-Resistance and 4A Sink Current Capability
stage core-voltage regulator solution with high efficiency • Supports High Switching Frequency
performance at high switching frequency for advanced
- Fast Output Rise and Fall Time
microprocessors.
- Low Tri-State Hold-Off Time (20ns)
The IC is biased by a single low voltage supply (5V),
• Support 3.3V and 5V PWM Input
minimizing driver switching losses in high MOSFET gate
capacitance and high switching frequency applications. • Low Quiescent Supply Current
Each driver is capable of driving a 3nF load with less than • Power-On Reset
10ns rise/fall time. Bootstrapping of the upper gate driver is
implemented via an internal low forward drop diode, • Expandable Bottom Copper Pad for Heat Spreading
reducing implementation cost, complexity, and allowing the • Dual Flat No-Lead (DFN) Package
use of higher performance, cost effective N-Channel - Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat
MOSFETs. Adaptive shoot-through protection is integrated No Leads-Product Outline
to prevent both MOSFETs from conducting simultaneously. - Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
The ISL6596 features 4A typical sink current for the lower
gate driver, enhancing the lower MOSFET gate hold-down • Pb-Free Plus Anneal Available (RoHS Compliant)
capability during PHASE node rising edge, preventing power
loss caused by the self turn-on of the lower MOSFET due to
the high dV/dt of the switching node. Ordering Information
The ISL6596 also features an input that recognizes a high- TEMP
PART PART RANGE PKG.
impedance state, working together with Intersil multi-phase NUMBER MARKING (°C) PACKAGE DWG. #
3.3V or 5V PWM controllers to prevent negative transients
ISL6596CBZ 6596CBZ 0 to 70 8 Ld SOIC M8.15
on the controlled output voltage when operation is (Note)
suspended. This feature eliminates the need for the schottky
ISL6596CBZ-T 6596CBZ 8 Ld SOIC Tape and Reel
diode that may be utilized in a power system to protect the (Note)
load from negative output voltage damage.
ISL6596CRZ 596Z 0 to 70 10 Ld 3x3 DFN L10.3x3
(Note)
Applications
ISL6596CRZ-T 596Z 10 Ld DFN Tape and Reel
• Core Voltage Supplies for Intel® and AMD® (Note)
Microprocessors
ISL6596IBZ -40 to 85 8 Ld SOIC M8.15
• High Frequency Low Profile High Efficiency DC/DC (Note)
Converters ISL6596IBZ-T 8 Ld SOIC Tape and Reel
(Note)
• High Current Low Voltage DC/DC Converters
ISL6596IRZ 96IZ -40 to 85 10 Ld 3x3 DFN L10.3x3
• Synchronous Rectification for Isolated Power Supplies (Note)

Related Literature ISL6596IRZ-T 96IZ 10 Ld DFN Tape and Reel

(Note)
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN (MLFP) Packages” NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
• Technical Brief TB363 “Guidelines for Handling and matte tin plate termination finish, which are RoHS compliant and
Processing Moisture Sensitive Surface Mount Devices compatible with both SnPb and Pb-free soldering operations. Intersil
(SMDs)” Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005. All Rights Reserved
Intel® is a registered trademark of Intel Corporation. AMD® is a registered trademark of Advanced Micro Devices, Inc.
 ISL6596

Pinout
ISL6596 (SOIC) ISL6596 (DFN)
TOP VIEW TOP VIEW

UGATE 1 8 PHASE UGATE 1 10 PHASE

BOOT 2 7 VCTRL BOOT 2 9 VCTRL
PWM 3 6 VCC N/C 3 8 N/C
GND 4 5 LGATE PWM 4 7 VCC
GND 5 6 LGATE

Block Diagram
ISL6596

VCC BOOT

VCTRL UGATE

PHASE
SHOOT-
7k THROUGH
PROTECTION
CONTROL VCC
PWM
LOGIC
7k LGATE

GND

VCTRL = CONTROLLER VCC

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 ISL6596

Typical Application - Multi-Phase Converter Using ISL6596 Gate Drivers

VIN

+5V

+3.3V

+3.3V VCC BOOT

FB COMP
VCTRL RUGPH
VCC UGATE
VSEN PWM
PWM1
ISL6596
PGOOD PWM2 PHASE
LGATE
PWM
CONTROLLER
(ISL69XX)

VID ISEN1
(OPTIONAL) +VCORE
ISEN2 +5V VIN

VCC BOOT
FS/EN
GND VCTRL RUGPH
UGATE
PWM
ISL6596
PHASE
LGATE

RUGPH IS REQUIRED FOR SPECIAL POWER SEQUENCING APPLICATIONS

(SEE APPLICATION INFORMATION SECTION ON PAGE 8)

3 FN9240.0
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 ISL6596

Absolute Maximum Ratings Thermal Information

Supply Voltage (VCC, VCTRL) . . . . . . . . . . . . . . . . . . . -0.3V to 7V Thermal Resistance (Notes 1, 2, & 3) θJA (°C/W) θJC (°C/W)
Input Voltage (VEN, VPWM) . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V SOIC Package (Note 1) . . . . . . . . . . . . 110 N/A
BOOT Voltage (VBOOT-GND). . . -0.3V to 25V (DC) or 36V (<200ns) DFN Package (Notes 2 & 3). . . . . . . . . 48 7
BOOT To PHASE Voltage (VBOOT-PHASE) . . . . . . -0.3V to 7V (DC) Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 9V (<10ns)
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
PHASE Voltage . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 15V (DC)
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
. . . . . . . . . GND -8V (<20ns Pulse Width, 10µJ) to 30V (<100ns)
UGATE Voltage . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT (SOIC - Lead Tips Only)
. . . . . . . . . . . VPHASE - 5V (<20ns Pulse Width, 10µJ) to VBOOT
LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V Recommended Operating Conditions
. . . . . . . . . . GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to 125°C Ambient Temperature Range. . . . . . . . . . . . . . . . . . . -40°C to 100°C
HBM ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV Maximum Operating Junction Temperature. . . . . . . . . . . . . . 125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
3. θJC, "case temperature" location is at the center of the package underside exposed pad. See Tech Brief TB379 for details.

Electrical Specifications These specifications apply for Recommended Operating Conditions, unless otherwise noted.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VCC SUPPLY CURRENT
Bias Supply Current IVCC PWM pin floating, VVCC = 5V - 190 - µA
POR Rising - 3.4 4.2
POR Falling 2.2 3.0 -
Hysteresis - 400 - mV
VCTRL INPUT
Rising Threshold - 2.75 2.90 V
Falling Threshold 2.4 2.65 - V
PWM INPUT
Sinking Impedance RPWM_SNK - 3.5 - kΩ
Source Impedance RPWM_SRC - 3.5 - kΩ
Tri-State LowerThreshold VVCTRL = 3.3V (-110mV Hysteresis) - 1.1 - V
VVCTRL = 5V (-250mV Hysteresis) - 1.5 - V
Tri-State Upper Threshold VVCTRL = 3.3V (+110mV Hysteresis) - 1.9 - V
VVCTRL = 5V (+250mV Hysteresis) - 3.25 - V
Tri-State Shutdown Holdoff Time tTSSHD tPDLU or tPDLL + Gate Falling Time - 20 - ns
SWITCHING TIME (See Figure 1 on Page 5)
UGATE Rise Time (Note 4) tRU VVCC = 5V, 3nF Load - 8.0 - ns
LGATE Rise Time (Note 4) tRL VVCC = 5V, 3nF Load - 8.0 - ns
UGATE Fall Time (Note 4) tFU VVCC = 5V, 3nF Load - 8.0 - ns
LGATE Fall Time (Note 4) tFL VVCC = 5V, 3nF Load - 4.0 - ns
UGATE Turn-Off Propagation Delay tPDLU VVCC = 5V, Outputs Unloaded - 20 - ns
LGATE Turn-Off Propagation Delay tPDLL VVCC = 5V, Outputs Unloaded - 15 - ns
UGATE Turn-On Propagation Delay tPDHU VVCC = 5V, Outputs Unloaded - 19 - ns
LGATE Turn-On Propagation Delay tPDHL VVCC = 5V, Outputs Unloaded - 18 - ns
Tri-state to UG/LG Rising Propagation Delay tPTS VVCC = 5V, Outputs Unloaded - 30 - ns
OUTPUT (Note 4)
Upper Drive Source Resistance RUG_SRC 250mA Source Current - 1.0 2.5 Ω
Upper Drive Sink Resistance RUG_SNK 250mA Sink Current - 1.0 2.5 Ω
Lower Drive Source Resistance RLG_SRC 250mA Source Current - 1.0 2.5 Ω
Lower Drive Sink Resistance RLG_SNK 250mA Sink Current - 0.4 1.0 Ω
NOTE:
4. Guaranteed by Characterization. Not 100% tested in production.

4 FN9240.0
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 ISL6596

Functional Pin Description LGATE (Pin 5)

Note: Pin numbers refer to the SOIC package. Check Lower gate drive output. Connect to gate of the low side
diagram for corresponding DFN pinout. N-Channel power MOSFET. A gate resistor is never
recommended on this pin, as it interferes with the operation
UGATE (Pin 1) shoot-through protection circuitry.
Upper gate drive output. Connect to gate of high-side
N-Channel power MOSFET. A gate resistor is never VCC (Pin 6)
recommended on this pin, as it interferes with the operation Connect this pin to a +5V bias supply. Locally bypass with a
shoot-through protection circuitry. high quality ceramic capacitor to ground.

BOOT (Pin 2) VCTRL (Pin 7)

Floating bootstrap supply pin for the upper gate drive. This pin sets the PWM logic threshold. Connect this pin to
Connect a bootstrap capacitor between this pin and the 3.3V source for 3.3V PWM input and pull it to 5V source for
PHASE pin. The bootstrap capacitor provides the charge 5V PWM input.
used to turn on the upper MOSFET. See the Bootstrap
PHASE (Pin 8)
Considerations section for guidance in choosing the
Connect this pin to the source of the upper MOSFET. This
appropriate capacitor value.
pin provides the return path for the upper gate driver current.
PWM (Pin 3)
Thermal Pad (in DFN only)
The PWM signal is the control input for the driver. The PWM
The metal pad underneath the center of the IC is a thermal
signal can enter three distinct states during operation, see the
substrate. The PCB “thermal land” design for this exposed
Tri-state PWM Input section for further details. Connect this pin
die pad should include vias that drop down and connect to
to the PWM output of the controller.
one or more buried copper plane(s). This combination of
GND (Pin 4) vias for vertical heat escape and buried planes for heat
Ground pin. All signals are referenced to this node. spreading allows the DFN to achieve its full thermal
potential. This pad should be either grounded or floating,
and it should not be connected to other nodes. Refer to
TB389 for design guidelines.

Timing Diagram

50% of VCC
PWM tPDHU
tPDLU tTSSHD

tRU tRU
tFU
tPTS

1V
UGATE

LGATE
tPTS
1V

tRL

tTSSHD
tPDLL tPDHL
tFL

FIGURE 1. TIMING DIAGRAM

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 ISL6596

Operation and Adaptive Shoot-Through Protection not exceed either output’s turn-off propagation delay plus the
Designed for high speed switching, the ISL6596 MOSFET MOSFET gate discharge time to ~1V. Abnormally long PWM
driver controls both high-side and low-side N-Channel FETs signal transition times through the shutdown window will simply
from one externally provided PWM signal. introduce additional dead time between turn off and turn on of
the synchronous bridge’s MOSFETs. For optimal performance,
A rising transition on PWM initiates the turn-off of the lower no more than 50pF parasitic capacitive load should be present
MOSFET (see Timing Diagram). After a short propagation on the PWM line of ISL6596 (assuming an Intersil PWM
delay [tPDLL], the lower gate begins to fall. Typical fall times controller is used).
[tFL] are provided in the Electrical Specifications. Adaptive
shoot-through circuitry monitors the LGATE voltage and turns Bootstrap Considerations
on the upper gate following a short delay time [tPDHU] after This driver features an internal bootstrap diode. Simply
the LGATE voltage drops below ~1V. The upper gate drive adding an external capacitor across the BOOT and PHASE
then begins to rise [tRU] and the upper MOSFET turns on. pins completes the bootstrap circuit.

A falling transition on PWM indicates the turn-off of the upper The following equation helps select a proper bootstrap
MOSFET and the turn-on of the lower MOSFET. A short capacitor size:
propagation delay [tPDLU] is encountered before the upper gate
Q GATE
begins to fall [tFU]. The adaptive shoot-through circuitry C BOOT_CAP ≥ --------------------------------------
∆V BOOT_CAP
monitors the UGATE-PHASE voltage and turns on the lower (EQ. 1)
MOSFET a short delay time, tPDHL, after the upper MOSFET’s
Q G1 • VCC
gate voltage drops below 1V. The lower gate then rises [tRL], Q GATE = ------------------------------- • N Q1
V GS1
turning on the lower MOSFET. These methods prevent both the
lower and upper MOSFETs from conducting simultaneously
where QG1 is the amount of gate charge per upper MOSFET
(shoot-through), while adapting the dead time to the gate
at VGS1 gate-source voltage and NQ1 is the number of
charge characteristics of the MOSFETs being used.
control MOSFETs. The ∆VBOOT_CAP term is defined as the
This driver is optimized for voltage regulators with large step allowable droop in the rail of the upper gate drive.
down ratio. The lower MOSFET is usually sized larger
As an example, suppose two IRLR7821 FETs are chosen as
compared to the upper MOSFET because the lower
the upper MOSFETs. The gate charge, QG, from the data
MOSFET conducts for a longer time during a switching
sheet is 10nC at 4.5V (VGS) gate-source voltage. Then the
period. The lower gate driver is therefore sized much larger
QGATE is calculated to be 22nC at VCC level. We will
to meet this application requirement. The 0.4Ω on-resistance
assume a 200mV droop in drive voltage over the PWM
and 4A sink current capability enable the lower gate driver to
cycle. We find that a bootstrap capacitance of at least
absorb the current injected into the lower gate through the
0.110µF is required. The next larger standard value
drain-to-gate capacitor of the lower MOSFET and help
capacitance is 0.22µF. A good quality ceramic capacitor is
prevent shoot through caused by the self turn-on of the lower
recommended.
MOSFET due to high dV/dt of the switching node.

PWM Input and Threshold Control

2.0
A unique feature of the ISL6596 is the programmable PWM
logic threshold set by the control pin (VCTRL) voltage. The 1.8

VCTRL pin should connect to the VCC of the controller, thus 1.6
the PWM logic threshold follows with the voltage level of the
1.4
controller. For 5V applications, this pin can tie to the driver
CBOOT_CAP (µF)

VCC and simplify the routing. 1.2

The ISL6596 also features the adaptable tri-state PWM input. 1.0
Once the PWM signal enters the shutdown window, either
0.8
MOSFET previously conducting is turned off. If the PWM signal
remains within the shutdown window for longer than the gate 0.6 QGATE = 100nC
turn-off propagation delay of the previously conducting
50

0.4
nC

MOSFET, the output drivers are disabled and both MOSFET

gates are pulled and held low. The shutdown state is removed 0.2
20nC
when the PWM signal moves outside the shutdown window.
0.0
The PWM rising and falling thresholds outlined in the Electrical 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Specifications determine when the lower and upper gates are ∆VBOOT_CAP (V)
enabled. During normal operation in a typical application, the FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
PWM rise and fall times through the shutdown window should VOLTAGE

6 FN9240.0
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 ISL6596

Power Dissipation The total gate drive power losses are dissipated among the
Package power dissipation is mainly a function of the resistive components along the transition path. The drive
switching frequency (FSW), the output drive impedance, the resistance dissipates a portion of the total gate drive power
external gate resistance, and the selected MOSFET’s losses, the rest will be dissipated by the external gate
internal gate resistance and total gate charge. Calculating resistors (RG1 and RG2, should be a short to avoid
the power dissipation in the driver for a desired application is interfering with the operation shoot-through protection
critical to ensure safe operation. Exceeding the maximum circuitry) and the internal gate resistors (RGI1 and RGI2) of
allowable power dissipation level will push the IC beyond the MOSFETs. Figures 3 and 4 show the typical upper and lower
maximum recommended operating junction temperature of gate drives turn-on transition path. The power dissipation on
125°C. The maximum allowable IC power dissipation for the the driver can be roughly estimated as:
SO8 package is approximately 800mW at room temperature, P DR = P DR_UP + P DR_LOW + I Q • VCC (EQ. 4)
while the power dissipation capacity in the DFN package,
with an exposed heat escape pad, is much higher. See  R HI1 R LO1  P Qg_Q1
P DR_UP =  -------------------------------------- - • ---------------------
+ ---------------------------------------
Layout Considerations paragraph for thermal transfer  R HI1 + R EXT1 R LO1 + R EXT1 2
improvement suggestions. When designing the driver into an
 R HI2 R LO2  P Qg_Q2
application, it is recommended that the following calculation P DR_LOW =  -------------------------------------- - • ---------------------
+ ---------------------------------------
 R HI2 + R EXT2 R LO2 + R EXT2 2
is used to ensure safe operation at the desired frequency for
the selected MOSFETs. The total gate drive power losses R GI1 R GI2
due to the gate charge of MOSFETs and the driver’s internal R EXT2 = R G1 + ------------- R EXT2 = R G2 + -------------
N Q1 N Q2
circuitry and their corresponding average driver current can
be estimated with Equations 2 and 3, respectively:

P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q • VCC (EQ. 2) VCC BOOT

D
Q G1 • VCC 2
P Qg_Q1 = ---------------------------------- • F SW • N Q1 CGD
V GS1
RHI1 G
CDS
Q G2 • VCC 2
P Qg_Q2 = ---------------------------------- • F SW • N Q2 RLO1 RG1 RGI1
V GS2 UGATE
CGS
Q1
S
 Q G1 • N Q1 Q G2 • N Q2
- + ------------------------------ • VCC • F SW + I Q
I VCC =  ----------------------------- PHASE
 V GS1 V GS2 
(EQ. 3) FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

where the gate charge (QG1 and QG2) is defined at a

VCC
particular gate to source voltage (VGS1and VGS2) in the
corresponding MOSFET datasheet; IQ is the driver’s total D
quiescent current with no load at both drive outputs; NQ1 CGD
and NQ2 are the number of upper and lower MOSFETs, RHI2 LGATE
G
respectively. The IQ VCC product is the quiescent power of CDS
the driver without capacitive load and is typically negligible. RLO2 RG2 RGI2
CGS
Q2

GND S

FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

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 ISL6596

Application Information Upper MOSFET Self Turn-On Effects At Startup

MOSFET Selection Should the driver have insufficient bias voltage applied, its
The parasitic inductances of the PCB and of the power outputs are floating. If the input bus is energized at a high
devices’ packaging (both upper and lower MOSFETs) can dV/dt rate while the driver outputs are floating, because of
cause serious ringing, exceeding absolute maximum rating self-coupling via the internal CGD of the MOSFET, the
of the devices. The negative ringing at the edges of the UGATE could momentarily rise up to a level greater than the
PHASE node could increase the bootstrap capacitor voltage threshold voltage of the MOSFET. This could potentially turn
through the internal bootstrap diode, and in some cases, it on the upper switch and result in damaging inrush energy.
may overstress the upper MOSFET driver. Careful layout, Therefore, if such a situation (when input bus powered up
proper selection of MOSFETs and packaging can go a long before the bias of the controller and driver is ready) could
way toward minimizing such unwanted stress. conceivably be encountered, it is a common practice to
place a resistor (RUGPH) across the gate and source of the
The D2-PAK, or D-PAK packaged MOSFETs, have large upper MOSFET to suppress the Miller coupling effect. The
parasitic lead inductances and are not recommended unless value of the resistor depends mainly on the input voltage’s
additional circuits are implemented to prevent the BOOT and rate of rise, the CGD/CGS ratio, as well as the gate-source
PHASE pins from exceeding the device rating. Low-profile threshold of the upper MOSFET. A higher dV/dt, a lower
MOSFETs, such as Direct FETs and multi-SOURCE leads CDS/CGS ratio, and a lower gate-source threshold upper
devices (SO-8, LFPAK, PowerPAK), have low parasitic lead FET will require a smaller resistor to diminish the effect of
inductances and are preferred. the internal capacitive coupling. For most applications, a
5kΩ to 10kΩ resistor is typically sufficient, not affecting
Layout Considerations
normal performance and efficiency.
A good layout helps reduce the ringing on the switching
The coupling effect can be roughly estimated with the
node (PHASE) and significantly lowers the stress applied to
following equations, which assume a fixed linear input ramp
the output drives. The following advice is meant to lead to an
and neglect the clamping effect of the body diode of the
optimized layout:
upper drive and the bootstrap capacitor. Other parasitic
• Keep decoupling loops (VCC-GND and BOOT-PHASE) as components such as lead inductances and PCB
short as possible. capacitances are also not taken into account. These
• Minimize trace inductance, especially on low-impedance equations are provided for guidance purpose only.
lines. All power traces (UGATE, PHASE, LGATE, GND, Therefore, the actual coupling effect should be examined
VCC) should be short and wide, as much as possible. using a very high impedance (10MΩ or greater) probe to
ensure a safe design margin.
• Minimize the inductance of the PHASE node. Ideally, the
source of the upper and the drain of the lower MOSFET DS
–V
 ----------------------------------
should be as close as thermally allowable.  ⋅ C iss
dV
dV ------- ⋅ R
V GS_MILLER = ------- ⋅ R ⋅ C rss  1 – e dt 
(EQ. 5)
• Minimize the current loop of the output and input power dt  
 
trains. Short the source connection of the lower MOSFET  
to ground as close to the transistor pin as feasible. Input
capacitors (especially ceramic decoupling) should be R = R UGPH + R GI C rss = C GD C iss = C GD + C GS
placed as close to the drain of upper and source of lower
MOSFETs as possible.
VCC BOOT VIN
In addition, for heat spreading, place copper underneath the
IC whether it has an exposed pad or not. The copper area D
CBOOT
can be extended beyond the bottom area of the IC and/or CGD
connected to buried power ground plane(s) with thermal DU UGATE G CDS
vias. This combination of vias for vertical heat escape,
ISL6596

DL RGI
extended copper plane, and buried planes improve heat
RUGPH

dissipation and allow the part to achieve its full thermal CGS QUPPER
potential. S
PHASE

FIGURE 5. GATE TO SOURCE RESISTOR TO REDUCE

UPPER MOSFET MILLER COUPLING

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 ISL6596

Dual Flat No-Lead Plastic Package (DFN)

2X L10.3x3
0.15 C A
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
A D
2X MILLIMETERS
0.15 C B SYMBOL MIN NOMINAL MAX NOTES
A 0.80 0.90 1.00 -
A1 - - 0.05 -
E A3 0.20 REF -
6
INDEX b 0.18 0.23 0.28 5,8
AREA D 3.00 BSC -

TOP VIEW
D2 1.95 2.00 2.05 7,8
B
E 3.00 BSC -
E2 1.55 1.60 1.65 7,8
0.10 C
e 0.50 BSC -
A
0.08 C k 0.25 - - -
L 0.30 0.35 0.40 8
C SIDE VIEW
SEATING A3
N 10 2
PLANE
Nd 5 3
7 8 Rev. 3 6/04
D2 NOTES:
(DATUM B)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
D2/2
6 1 2 2. N is the number of terminals.
INDEX 3. Nd refers to the number of terminals on D.
AREA NX k
4. All dimensions are in millimeters. Angles are in degrees.
(DATUM A)
5. Dimension b applies to the metallized terminal and is measured
E2
between 0.15mm and 0.30mm from the terminal tip.
E2/2
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
NX L either a mold or mark feature.
N N-1 7. Dimensions D2 and E2 are for the exposed pads which provide
NX b
e improved electrical and thermal performance.
8
5 8. Nominal dimensions are provided to assist with PCB Land
(Nd-1)Xe 0.10 M C A B Pattern Design efforts, see Intersil Technical Brief TB389.
REF.
BOTTOM VIEW
C
L
0.415
NX (b) (A1) L
0.200
NX L
5
e
SECTION "C-C"
NX b
C C TERMINAL TIP
C
FOR ODD TERMINAL/SIDE

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 ISL6596

Small Outline Plastic Packages (SOIC)

N
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA H 0.25(0.010) M B M
INCHES MILLIMETERS
E
SYMBOL MIN MAX MIN MAX NOTES
-B-
A 0.0532 0.0688 1.35 1.75 -

1 2 3 A1 0.0040 0.0098 0.10 0.25 -

L
B 0.013 0.020 0.33 0.51 9
SEATING PLANE C 0.0075 0.0098 0.19 0.25 -
-A- D 0.1890 0.1968 4.80 5.00 3
D A h x 45°
E 0.1497 0.1574 3.80 4.00 4
-C- e 0.050 BSC 1.27 BSC -
α
H 0.2284 0.2440 5.80 6.20 -
e A1
C h 0.0099 0.0196 0.25 0.50 5
B 0.10(0.004)
L 0.016 0.050 0.40 1.27 6
0.25(0.010) M C A M B S
N 8 8 7
NOTES: α 0° 8° 0° 8° -
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Rev. 1 6/05
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

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10 FN9240.0
November 2, 2005