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Instructions To Paper Setters: Maximum Marks: 75

This document outlines the syllabus for a VLSI design course. It is divided into 4 units covering topics such as MOS transistor theory, CMOS logic gates, clocked CMOS logic, and VLSI design methodology. Unit 1 discusses MOS transistor basics and CMOS inverter characteristics. Unit 2 covers switching characteristics, interconnect effects, and CMOS logic gate design. Unit 3 focuses on clocked CMOS logic, pass transistor logic, and clocking strategies. Unit 4 addresses two-phase logic structures, four-phase memory structures, and VLSI design flow and tools. The document provides reading materials and instructs that there will be one compulsory question covering the entire syllabus worth 25 marks, and four additional unit

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69 views

Instructions To Paper Setters: Maximum Marks: 75

This document outlines the syllabus for a VLSI design course. It is divided into 4 units covering topics such as MOS transistor theory, CMOS logic gates, clocked CMOS logic, and VLSI design methodology. Unit 1 discusses MOS transistor basics and CMOS inverter characteristics. Unit 2 covers switching characteristics, interconnect effects, and CMOS logic gate design. Unit 3 focuses on clocked CMOS logic, pass transistor logic, and clocking strategies. Unit 4 addresses two-phase logic structures, four-phase memory structures, and VLSI design flow and tools. The document provides reading materials and instructs that there will be one compulsory question covering the entire syllabus worth 25 marks, and four additional unit

Uploaded by

arup
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Paper Code: ETEC-

308 L T C
Paper: VLSI
DESIGN 3 1 4
INSTRUCTIONS TO PAPER SETTERS: MAXIMUM MARKS: 75
1. Question No. 1 should be compulsory and cover the entire syllabus. This question should have objective or short answer type questions.
It should be of 25 marks.
2. Apart from Q. No. 1 rest of the paper shall consist of four units as per the syllabus. Every unit should have two questions. However,
student may be asked to attempt only 1 question from each unit. Each question should be of 12.5 marks.

Unit I
Evolution of VLSI, MOS transistor theory – MOS structure, enhancement &
depletion transistor, Threshold voltage, MOS device design equations,
CMOS inverter- DC characteristics, static load MOS inverter, pull up/pull down
ratio, state & Dynamic power dissipation, CMOS & NMOS process technology –
explanation of different stages in fabrication, latch
up. [No. of
Hours: 11]

Unit II
Switching characteristics & inter connection effects: Rise time, fall time delays
Inverter design with delay constants. Parasitic effect, Super buffer.
CMOS logic gate design: Fan in, fan out Typical NAND, NOR, delays Transistor
Sizing XOR, and XNOR gates.
CMOS logic structures: CMOS complimentary logic, Pseduo NMOS
logic, [No. of Hours: 11]

Unit III
Clocked CMOS logic , pass transistor logic , domino , zipper CMOS.
Clocking strategies: clocked system, latches & Registers, system timing set-up &
hold timing, signal phase memory structure, 2 phase clocking, Two phase memory
structure, [No. of Hours: 11]

Unit IV
Two phase logic structure; four phase memory & logic structure
VLSI designing methodology – Introduction, VLSI designs flow, Design
Hierarchy Concept of regularity, Modularity & Locality, VLSI design style,
Design quality. Computer aided design technology: Design capture and
verification tools. [No. of Hours: 11]

Text Books:
1. S. M. Kang, Y. Lebiebici, “CMOS digital integrated circuits analysis &
design” TMH,
3rd Edition.
2. Weste and Eshrighian, “Principle of CMOS VLSI Design” Pearson
Education, 2001.

Reference Book:
1. R. J. Baker, H.W.Li, D. E. Boyce, “CMOS Circuit Design, Layout and
Simulation” PHI – 2000.
2. J. M. Rabaey, “Digital Integrated Circuits” PHI – 2nd Edition.
3. W. Wolf Pearson, “Modern VLSI Design Systems on Silicon” Pearson
Education – 2nd Edition.
4. J. P. Vyenmura, “Introduction to VLSI Circuits and Systems” John Wiely,
st
1 Edition.

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