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Introduction To Verilog

This document provides an introduction to Verilog, a hardware description language. It outlines prerequisites and the suggested time needed to learn Verilog. The motivation for using Verilog is that it allows designers to simulate hardware at different levels before implementing a design in silicon. The learning outcomes are listed, including understanding design flow, installing Verilog simulators, compiling and simulating circuits, syntax, and modeling circuits. An overview of the design flow using HDLs is provided. Verilog supports bottom-up, top-down, and hybrid design styles. It also supports different levels of abstraction including behavioral, register-transfer, and gate levels. A 1-bit multiplexer is used as an example to demonstrate coding at each level in Verilog

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80 views7 pages

Introduction To Verilog

This document provides an introduction to Verilog, a hardware description language. It outlines prerequisites and the suggested time needed to learn Verilog. The motivation for using Verilog is that it allows designers to simulate hardware at different levels before implementing a design in silicon. The learning outcomes are listed, including understanding design flow, installing Verilog simulators, compiling and simulating circuits, syntax, and modeling circuits. An overview of the design flow using HDLs is provided. Verilog supports bottom-up, top-down, and hybrid design styles. It also supports different levels of abstraction including behavioral, register-transfer, and gate levels. A 1-bit multiplexer is used as an example to demonstrate coding at each level in Verilog

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abduljabaar
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Introduction to Verilog

Pre-requisites
1. A little knowledge of various digital combinational and sequential
circuits will make the learning easier.
2. People with the basic knowledge of C or C++ will have an edge in
Verilog programming.

Suggested Time
8 hrs

Motivation
As digital systems become more complex, it becomes very important to
verify the functionality of a design before implementing it in a system.
A Hardware description language allows us to simulate the hardware at
different levels i.e. gate level, behavioral level etc before actually
implementing it on a silicon chip.
Verilog is one of the most popular HARDWARE DESCRIPTION
LANGUAGE (HDL). Another standard HDL is VHDL. In this course we will
focus on Verilog and use it as standard language to implement any
logic.

Learning Outcome
By end of this module you will know

 What is meant by Design Flow in VLSI?


 How to install Verilog Simulator.
 How to compile and simulate basic circuits in Verilog.
 What is syntax of Verilog coding?
 How to model any circuit in HDL (Hardware Description Language)
and analyze it.
 And you will develop top-down and bottom-up approach in writing
Verilog code.

Introduction
Verilog is a hardware description language, which is used to model any
system before fabrication. In the silicon chip design process, the final
fabrication is very costly so before implementing any system on actual
silicon chip we have to make sure that the system is working perfectly
by implementing it in a hardware description language. Verilog is the
most popular HDL which is standardized by IEEE.

Overall design flow in Circuit development using HDL


Verilog Design Styles
Verilog, like any other hardware description language, permits a design
in either Bottom-up or Top-down methodology.
Bottom-Up Design
The traditional method of electronic design is bottom-up. Each design is
performed at the gate-level using the standard gates. With the
increasing complexity of new designs this approach is nearly impossible
to maintain. New systems consist of ASIC or microprocessors with a
complexity of thousands of transistors. These traditional bottom-up
designs have to give way to new structural, hierarchical design
methods. Without these new practices it would be impossible to handle
the new complexity.
Top-Down Design
The desired design-style of all designers is the top-down one. A real
top-down design allows early testing, easy change of different
technologies and a structured system design along with many other
advantages.
Hybrid approach
It is very difficult to follow a pure top-down design or a pure bottom up
design because of their advantages and disadvantages. Top-down
approach allows rapid development and early testing but it does not
consider circuit delay and other practical aspect. In bottom-up design
the development rate is very slow. Due to this fact most designs are a
mix of both methods, implementing some key elements of both design
styles.

Verilog Abstraction Levels


Verilog supports designing at many different levels of abstraction.
Three of them are very important:
1. Behavioral level
2. Register-Transfer Level
3. Gate Level
In this part will explain the different level of abstraction by designing a
simple 1-bit multiplier using different level of abstraction in Verilog. 1
Bit multiplexer has two inputs and 1 control. It outputs the one of the
input depending on the selection control. The circuit diagram, pseudo
code and k-map of 1 bit multiplexer are given in Fig 1.

Fig.1 1 bit Multiplexer KNN map and circuit

Behavioral level
Behavior is highest level of abstraction in Verilog. To implement the
circuit in this abstraction level the behavior of circuit is required.
Functions, Tasks and Always blocks are the main elements of this level.
There is no regard to the structural realization of the design. In the Fig.
2 we design 1-bit multiplexer on behavioral level.
NOTE: If you are not comfortable with C, I will recommend you to
quickly brush up the basic of C before proceeding.
Fig. 2 Behavioral and Register transfer level code for 1 bit Multiplexer
Register-Transfer Level
Designs using the Register-Transfer Level specify the characteristics of a
circuit by operations and the transfer of data between the registers.
This abstraction level is lower than behavioral level but higher than
register level. The keyword assign is used for different types of
assignment in this abstraction level. In the Fig 2 we design 1-bit
multiplexer on RTL level.
Gate Level
In the logic level the characteristics of a system are described by logical gates and their
timing properties. In this level all signals are discrete signals, which can
only have definite logical values (`0', `1', `X', `Z`). We have to specify
gate connection of each and every gate and net/wire. This is similar to
drawing the actual circuit of the system but only in code form.
Gate level diagram of 1-bit multiplexer and Verilog code is given in Fig.
Fig. 3 Gate level Verilog code for 1 bit Multiplexer
Summary
We learned that there are 3 different levels of abstractions in Verilog.
In reality there is 1 more abstraction level called transistor level but for
practical purposes it is not very useful as it is even lower abstraction
level compared to gate level.

We also saw the codes in all abstraction levels for a simple circuit, it is
okay if you don’t understand the code below, and the only thing that
we should observe is

 Verilog is a strongly typed language; you need to define the


variables and their type before you can use them. Read below to
know what strongly typed language means
 There are many abstraction levels in Verilog.
 In all abstraction levels the special keywords and operators used
are different.
Fig.4 Simple 1-bit multiplexer behavioral level code in Verilog
Look at the example of Fig. 4. Above code is self explanatory as the
name of the module is mux2. This is similar to functions in
programming languages; we can use this module by calling this mux2
name. It has 3 input ports and 1 output port and the type of output
port is register. Modules are similar to functions; below are some
properties of their properties:

 Basic building block in Verilog


 Module
 Created by “declaration” (can’t be nested)
 Used by “instantiation”
 Interface is defined by ports
 May contain instances of other modules
 All modules run concurrently

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