14/09/20

UNIT 3 - Microcontrollers
14/09/2020 M 

MICROCONTROLLER - CLOCK SYSTEM 

- all mcu contains a clock module to drive a CPU and Peripherals 

- the conflicting requirements for clock in high performance and low power
microcontrollers 


theoretically , one clock is enough 


- a clock is a square wave signal whose edge triggers the hardware

- a clock may be generated by various sources of pulses ex) crystal 

- but, systems have conflicting requirements 

- low power, fast start/ stop, accurate

DIFFERENT REQUIREMENTS FOR THE CLOCK

Devices often in low power mode until some event occurs, the must wake
up and handle event rapidly - clock must be stablished quickly

Device also need to keep a track of real time 


- can wake up periodically or 

- time stamp external events

Therefore , two kinds of clocks are often needed:


- a fast clock - to drive CPU , which can be started and stopped rapidly
but need not be accurate 


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- a slow clock - that runs continuously to monitor real time that uses
little power and is accurate

Different clock sources also have different characteristics 


- crystal : accurate and stable - wrt temperature or time 

expensive, delicate, draws large current, external component 

slow to start up and stabilise 

- resister and capacitor (RC): cheap, quick to start, integrated within mcu
and sleep with cpu; poor accuracy and stability 

- ceramic resonator and MEMS clocks in between

MSP430 addresses the conflicting demands for high performance, low

power, precise frequency by using 3 internal clocks, which can be
derived from upto 4 sources 

- Master clock(mclk): for cpu and some peripherals, normally driven by
digitally controlled oscillator (DCO) in MHz range 

- subsystem master clock(smclk): distributed to peripherals, driven by
DCO

- Auxiliary clock (aclk): distributed to peripherals, normally for real time
clocking, driven by a low-frequency crystal oscillator, typically at 32KHz

Need multiple clocks



CLOCK SOURCES IN MSP430

Low or high frequency crystal oscillator , LFXT1:


external ; used with a low or high frequency crystal ;

an external clock signal can be used;

connected to MSP430 through XIN and XOUT pins

High frequency crystal oscillator , XT2:


external;

similar to LFXT1 but at high frequency

Very low power , low frequency oscillator , VLO:


internal at 12 KHz;

alternative to LFXT1 when accuracy of a crystal is needed;

may not available in all devices

Digitally controlled oscillator, DCO:


internal;

a highly controllable RC oscillator that starts fast

FROM SOURCES TO CLOCKS

Typical sources of clocks:


- MCLK, SMCLK: DCO - typically at 1.1 MHz

- ACLK: LFXT1 - typically at 32 KHz

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Control registers for clock system

DCOCTL and BCSCTL1 combined define the frequency of DCO, among other

settings

Can use tag-length-value (TLV) that are stored in the flash memory to set
DCOCTL and BCSCTL1 for DCO frequency

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BCSCTL1 = CALBC1_1MHz // set range

DCOCTL = CALDCO_1MHz

CLOCK SYSTEM

Different peripherals may use different clock domains 


each of the three clock domains above can be sourced by oscillator sources
- section 5.8 of tb 

each of the three clock domains can also be divided down by a factor of
1,2,4 or 8

How long will the system run without a reset?


is precise timing needed?

are you keeping track of real time ?

what range of temperatures will your system be operating in?

STATUS REGISTER CONTROL of clock module

4 bits in the SR enable and disable parts of the clock module to facilitate
low power modes

OSCILLATOR FAULT - having multiple oscillator candidates for a clock

source allows for some fault tolerance 

What happens if an external crystal oscillator fails and your system in a
part of a satellite in space ?

ans) software can switch over to an alternate, less desirable or backup
oscillator as a fail safe

An RC circuit can be used at primitive way of detecting an oscillator fault

MSP430 uses a more sophisticated hardware technique

τ = RC

Vout = Vin · e-(t/τ)

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MSP430 RESETS

Power-Up Clear (PUC)


Distinctive from power on reset 

caused by software conditions 

watchdog timer expiration 

software generated reset condition - bad watchdog password 

runaway flash memory programming - bad flash controller password 

access violation - reading IC from peripheral registers

If rom is overwritten , reset occurs , accessed is denied

Reset has Dif sequence of programs

Brownout is response of hardware which causes the reset. When the power
requirement is not met

How is the reset found out ?


can be determined through flags

Brownout protection is available

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WATCHDOG TIMER

It keeps monitoring a code 


used to generate timers 

why timers is required ? - to generate a delay (delay subroutine) - delay
generation 

- counting 

WDT

- check if the software works properly after the reset occurs - if counting
has been started 

- kind of automation 

- delay generator

8 software selectable time interval 


16 bit wide

8 - MSB - password compare

8 - LSB - control registers 

32ms to count from 00 to ff 

password protected

The primary function of the watchdog timer module is

- to perform a controlled system restart after a software problem occurs 


if the selected time interval expires, a system reset is generated

- If the watchdog function is not needed in an application, the module can

work as an interval timer, to generate an interrupt after the selected
time interval

Features of the watchdog timer include :

- eight software selectable time intervals

- Two operating mode : as watchdog and interval timer

- Expiration of the time interval in the watchdog mode , which generates a

system reset or in timer mode, which generates an interrupt request

- Safeguards which ensure that writing to the WDT control register is only
possible using a password

- Support of ultra low - power using the hold mode 


Watchdog / timer two functions :

- SW watchdog mode

- Interval timer mode

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The watchdog timer counter (WDTCNT) is a 16 bit up counter 


that is not directly accessible by software 

is controlled through the watchdog timer control register (WDTCTL)

WDTCTL is a 16 bit read/write register 

WDTCT is located at the low byte of word address 0120h 

any read or write access must be done using word instructions with no
suffix or .w suffix 

in both operating modes (watchdog or timer), it is only possible to write to
WDTCT using the correct password

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Bits 0, 1: Bits IS0 and IS1 select one of four taps from the WDTCNT, as
described in following table. Assuming f crystal = 32,768 Hz and f
System = 1 MHz, the following intervals are possible:

SSEL IS1 IS0 Interval [ms]

0 1 1 0.064 tSMCLK . 26
0 1 0 0.5 tSMCLK . 29
1 1 1 0.5 tSMCLK . 26
0 0 1 8 tSMCLK . 213
1 1 0 16 tACLK . 29
0 0 0 32 tSMCLK . 215
value after PUC
(reset)

1 0 1 250 tACLK . 213

1 0 0 1000 tACLK . 215

Bit 2: The SSEL bit selects the clock source for WDTCNT.

SSEL = 0: WDTCNT is clocked by SMCLK .

SSEL = 1: WDTCNT is clocked by ACLK.

Bit 3: Counter clear bit. In both operating modes, writing a 1 to this bit

restarts the WDTCNT at 00000h. The value read is not defined.

Bit 4: The TMSEL bit selects the operating mode: watchdog or timer.

TMSEL = 0: Watchdog mode

TMSEL = 1: Interval-timer mode

Bit 5: The NMI bit selects the function of the RST/NMI input pin. It is
cleared by the PUC signal.

NMI = 0: The RST/NMI input works as reset input.

As long as the RST/NMI pin is held low, the internal signal is

active (level sensitive).

NMI = 1: The RST/NMI input works as an edge-sensitive non-

maskable interrupt input

Bit 6: If the NMI function is selected, this bit selects the activating edge
of the RST/NMI input. It is cleared by the PUC signal.

NMIES = 0: A rising edge triggers an NMI interrupt.

NMIES = 1: A falling edge triggers an NMI interrupt.

CAUTION: Changing the NMIES bit with software can generate an NMI
interrupt.

Bit 7: This bit stops the operation of the watchdog counter. The clock
multiplexer is disabled and the counter stops incrementing. It holds the

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last value until the hold bit is reset and the operation continues. It is
cleared by the PUC signal.

HOLD = 0: The WDT is fully active.

HOLD = 1: The clock multiplexer and counter are stopped

16/09/2020 Wednesday

Aclk and smclk is not used for cpu

Start of program trigger clock

Low power mode - not all clocks are on

Resets

- hardware and software trigger

- How ports are triggered (default ports are input)

Wdt looks over the software

Time interval depends on the counter - 16 bits (0001 - 16 bits )

32ms to reset (default value)

Timer - delay generation

When reset , wdt is used as itself but for timer we need to change the
setting

Upper bit -> password compare ; password - 01011010

Wdt - counter mode

Wdtmtssel -> which clock service is needed

Wdtis - input source

Default clock - smclk (0)

Ssel - 1 for aclk

Aclk give low frequency

Nand checks for equality of password

.w only as it is 16 bit

Nm1 =1 - edge sensitive

System is enabled or disabled during edges (rising or falling)

PUC is due to hardware

Interrupt flag - indicate the status of wdt

IFG1 is in flash memory

Interrupt Service subroutine is also subprogram - wdt is used - acts as

timer and not a watchdog

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Flag = 1 timer mode

Flag =0 something other than wdt caused the PUC

In timer mode , flag has to be reset manually

In interval mode, flag is reset automatically

Time is in millisecond ex) 250 ms

Make bits high by concatenation

Password is key

.equ all the places mentions the name will be equated to that number

ex) WDT_key .equ 05A00h

Why 80h ? As hold is present on the 8 bit and hold pin is enabled to high

Most is done internally

Aclk - 250ms

All bits of SR are enabled or disabled due to ALU

Negative number is seen as two’s compliment

Negative number operation and subtraction operation

WATCHDOG TIMER (WDT) - INTERRUPT FUNCTION

The watchdog timer (wdt) uses two bits in the SFR’s for interrupt control

The WDT interrupt flag (WDTIFG) - Located in IFG1.0 , initial state is reset

The WDT interrupt enable (WDTIE) - Located in IE1.0 , initial state is reset

When using the watchdog mode the WDTIFG flag is used by the reset
Interrupt service routine to determine if the watchdog caused the
device to reset

If the flag is set , the the wdt initiated the reset condition (either by
timing out or by a security key violation)

If the flag is cleared, then the PUC was caused by a different source

When using the wdt in interval timer mode, the WDTIFG is set after the
selected time interval and a watchdog interval timer Interrupt is
requested

The interrupt vector address in the interval timer mode is different from
that in a watchdog mode

In the interval timer mode, the WDTIFG flag is reset automatically when
the interrupt is serviced

The WDTIE bit is used to enable or disable the interrupt from the WDT
when it is being used in the interval mode

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Also the GIE bit enables or disables the interrupt from the wdt then it is
being used in the interval timer mode.

Setting the WDTCTL register bit TMSEL to 1 selects the timer mode.

This mode provides periodic interrupts at the selected time interval.

A time interval can also be initiated by writing a 1 to bit CNTCL in the

WDTCTL register.

When the wdt is configured to operate in the timer mode, the WDTIFG
flag is set after the selected time interval and it requests a standard
interrupt service.

The WDT interrupt flag is a single source interrupt flag and is

automatically reset when it is serviced.

The enable bit remains unchanged. In the interval timer mode, the wdt
interrupt enable bit and the GIE bit must be set to allow the WDT to
request an interrupt.

The interrupt vector address in timer mode is different from that in

watchdog mode.

How to select timer mode :

/* WDT is clocked by fACLK (assumed 32KHz) */

WDTCL = WDT_ADLY_250; // WDT 250ms/4 interval timer

IE1 |= WDTIE // enable not interrupt

How to stop watchdog timer :

WDTCTL = WDTPW + WDTHOLD; // stop watchdog timer

Assembly programming :

WDT_key .equ 05A00h ;key to access WDT

WDTStop mov #(WDT_Key + 80h), &WDTCTL ;hold the watchdog

WDT250 mov #(WDT_Key + 10h), &WDTCTL ;WDT, 250ms interval

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INTERRUPTS :

Reaction of mcu to an unknown event

In mcu the interrupt should be handled

Polling is round robin method (polling the memory) - search the interrupt
one after the other

Interrupt may be due to different reasons ???

Every processor has to be written a diff interrupt

all the entities should be active hence no low power mode

All mcu has polling mode

Interrupt has different subroutine - interrupt vector table present in flash

memory

Where the interrupt has occurred is known hence easier

Interrupt is a event which diverts the mcu from main task

- intentional or unintentional subroutine

- Display something in between the program is considered as a interrupt

How to enable interrupt :

GIE = 1 (global interrupt enable) - flag bit in SR - 1mc

PC address to saved on Stack - 2 mc

SR values / address should be saved - 2 mc

Find the labelling - 1 mc

ISR - interrupt handler - software to take care of / execute the interrupts

When interrupt is called ?

When reset is given , the task is done immediately

SR value changes

Hardware is preprogrammed

Flag registers is associated with every interrupt

Timer register flag has to cleared manually, others are cleared

automatically when the interrupt is over

Reset is also unintentional interrupt

Maskable : system will enable or disable - timer

Non maskable : user will enable or disable - reset; GIE should be 1

All system have exceptional handling

Its like call and return

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RETI coming back from the interrupt to main program by popping PC
address stored in SR ; automatic flag register like GIE are cleared ;
come back from low power mode when going back to the main memory

RET return for normal subroutine

Mov #number , IER - interruption enable register

RETI

Clocks are set to low power mode when an interrupt occurs

No of interrupts in mcu - around 31 interrupts

Types of interrupts

Timer

Reset

Serial communication

Power up - PURI

External reset

Watchdog timer

Comparator

Flash key violation - key is overwritten

PC out of range - lengthy codes - too long to execute and hence

modularisation is used - save space in the editor window

Priority from bottom to up (highest)

Arduino is a microcontroller

Non editable / maskable interrupt has higher priority

R22R - DAC or ADC??

Flash - ADC

GPIO address ??

Ports are eight bit

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A computer has 2 basic ways to react to input :

1. Polling : the processor regularly looks at the input and reacts as

appropriate 

Adv) easy to implement and debug 

Disadv) processor intensive ; if the event is rare , a lot of time is
wasted in checking ; processor can’t go into low power - (slow or
stopped) modes

2. Interrupts : the processor is interrupted by an event 


adv) very efficient time wise : no time wasted looking for an event
that hasn’t occured

very efficient energy wise : processor can be asleep most of the
time 

Disadv) can be hard to debug

What happens on interrupt ?

Interrupt acceptance :

the interrupt latency is 6 cycles (CPU), from the acceptance of an

interrupt request to the start of the execution of the interrupt service
routine

The interrupt logic executes the following :

- any current executing instruction is completed

- The PC, which points to the next instruction, is pushed onto the stack

- The SR is pushed onto the stack

- The interrupt with the highest priority is selected if multiple interrupts

occurred during the last instruction and are pending for service

- The interrupt request flag resets automatically on the single source flags
remain set for servicing by the software

- The SR is cleared. This terminates any low power mode. because the GIE
bit is cleared, further interrupts are disabled.

- The content of the interrupt vector is loaded into the PC: the program
continues with the interrupt service routine at that address.

Return from interrupt.

The interrupt handling routing terminates with instructions : RETI - return

from ISR

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The return from the interrupt takes 5 cycles (CPU) or 3 cycles (CPUx) to
execute the following actions

1. The SR with all pervious settings pop from the stack. All previous
setting of GIE, CPUOFF etc are now in effect, regardless of the setting
used during the interrupt service routine

2. The PC pops from the stack and begins execution at the point where it
was interrupted

PROCESSING AN INTERRUPT:

1) Current instruction completed

2) MCLK started if CPU was off

3) Processor pushes PC on stack

4) Processor pushes SR on stack

5) Interrupt with highest priority selected

6) Interrupt request flag cleared if single sourced

7) Status register is cleared :


disables further maskable interrupts - GIE cleared 

terminates low power mode

8) Processor fetches interrupt vector and stores it in the program counter

9) User ISR must do the rest !

INTERRUPT STACK:

prior to interrupt service routine = ISR

ISR hardware - automatically

- PC pushed

- SR pushed

- Interrupt vector moved to PC

- GIE, CPUOFF, OSCOFF and SCG1 cleared

- IFG cleared on single source flag

RETI - automatically

- SR popped - original

- PC popped

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INTERRUPT SERVICE ROUTINE:

1) Look superficially like a subroutine

2) However unlike subroutines 


ISR can execute at unpredictable times 

Must carry out action and thoroughly clean up

must be concerned with shared variables

must return using RETI not RET

3) ISR must handle interrupt in such a way that the interrupted code can
be resumed without error

copies of all the registers used in the ISR must be saved-
preferably on the stack

4) Well written ISR’s:


should be short and fast 

should affect the rest of the system as little as possible 

require a balance between doing very little - thereby leaving the
background code with nothing to do

5) Applications that use interrupts should 


disable interrupts as little as possible 

respond to interrupt as quickly as possible

6) Interrupt related runtime problems can be exceptionally hard to debug

7) Common interrupt - related errors include 


- failing to protect global variables 

- forgetting to actually include ISR - no linker error 

- not testing or validating thoroughly 

- stack overflow 

- running out of the CPU horsepower 

- interrupting critical code 

- trying to outsmart the compiler

INTERRUPT VECTORS:

a) The CPU must know when to fetch the next instruction following an
interrupt

b) The address of an ISR is defined in an interrupt vector

c) The MSP430 uses vectored interrupts where each ISR has its own
vector stored in a vector table located at the end of the program
memory

d) Note: The vector table is a fixed location (defined by the processor data
sheet), nut the ISR’s can located anywhere in the memory

INTERRUPT FLAGS

a) Each interrupt has flag that is raised (set) when the interrupt occurs

b) Each interrupt flag has a correspond enable bit - setting this bit allows
a hardware module to request an interrupt

c) Most of the interrupt are maskable - which mean they can interrupt
only if 

- enabled and 

- GIE(general interrupt enable) is set in the SR

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INTERRUPTS:

I) Reaction to something in I/O (human, communication link)

II) Usually asynchronous to processor activities

III)interrupt handler or ISR invoked to take care of condition causing

interrupt

- change the value of internal variable (count)

- read a data value (sensor, receive)

- write a data value (actuator, send)

IV) Interrupts are commonly used for 


- urgent tasks with higher priority than the main code 

- infrequent task to save polling overhead 

- waking the CPU from sleep 

- call to an OS - software interrupt

V) Event-driven programming 

- the flow of the program is determined by events I.e, sensor
outputs or user actions (mouse clicks, key process) or messages from
other programs or threads 

- the application has a main loop with event detection and event
handlers

VI) Interrupts pre-empt normal code execution 


- interrupt code runs in the foreground 

- normal main code runs in the background

VII)Interrupts cab be enabled and disabled 


- globally

- individually on a per-peripheral basis 

- non-maskable interrupt (NMI)

VIII)The occurrence of each interrupt is unpredictable 


- when an interrupt occurs 

- where an interrupt occurs

IX) Interrupts are associated with a variety of on-chip and off-chip

peripherals 

- watchdog, timers, D/A, accelerometer 

- NMI, change on pin - switch

22/09/20 tuesday

Timers have more accuracy in delay generation

Timers is used for counting of events - counter

Mcu can have 1 or 2 or 3 timers

MSP has 2 timer

MSP2 series has 1 timer - timer A

Larger mcu has more timers

Brownout protection for reset

Timer0_A2 in MSP430G2x31

Baud rate - rate at which data is transferred in one second - number of

bits per second ; all communication sys have a standard board rate

Timer is used generate Baud rate - serial communication - what rate data
packets are transferred.

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Timer is used for PWM waveform generation

Every timer has its own block diagram

TAR - timer A register block - 16 bit mode working - number is loaded

here - example ) 5 delay is stored her

Timer is also 16 bit - 0000 to 65535 delay - 0000 to ffff

TASSELx - timer A source select block - select which source to give

Clock source decides how much time is taken to increase by 1 - rate of

switching / counting is decided by the clock

Clock is used decide on and off time , and pulse given is also decided

INCLK - internal clock with fixed frequency

TACLK - timer a clock

IDX - internal divider circuitry - 1 - same frequency is given

2 - divide freq by 2 etc

Idx default is 1 divider

Clock source decides the duration of the count (0 to 1)

Mcx - mode counter selection - mode selection - how the counting should
happens - up count or down count , up-down (0-256-0), stop x=0,1,2,3

TACLR - timer a clear - after one count finishes , timer is cleared

Taclr = 0 bit will be cleared - divider is also cleared

TAIFG - timer interrupt flag, when the count is began - flag becomes high
, when the count is over , flag becomes low

Timer will roll back to 0 from 256 in one clock cycle - after reaching 256,
the timer will not be idle , flag should be cleared manually - timer is
ready for next action

Another number needed is stored in the TAR

TAR is usually an empty block - usually hexadecimal block

Clock - synchronous count with duration

External clock is also used

Multiplex circuit is used

Taifg is in interrupt vector table

timer_A control register “TACTL”

16 bit register

Everything is memory mapped

LSB - taifg

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1 - timer a interrupt enable - timer is used as an ISR then we need to use
this bit - timer is used is as interrupt and not as main file

2 - clear

3- unused - upto to the user

4 and 5 - mode counter - 2 bits are used

6 and 7 - divider circuitry

8 and 9 - source select

Rw - read write - comes under software reset

rw-(0) - comes under hardware reset

If TAIFG = 1 , setting of TAIFG causes an interrupt to the CPU; TAIFG has

to be explicitly cleared by the cpu - use TAIFG = 0

Usually inclk is not used as it is device specific - 32kHz

Power up and power on types of reset

TACCRx - has 5 registers - max 3 is used at a time - used to give value to

TAR

TACTL = TASSEL_2 + MC_1 ; // src from smclk , up mode -anything can

concatenated

Every timer has its own designation

Every timer has two blocks - timer , control register

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TIMER MODE:

MCx = 00: stop mode - the timer is halted

MCx = 01 : up mode - the timer repeatedly counts from 0 to TACCR0

MCx = 10 : continuous mode : the timer repeatedly counts from 0 to 0ffffh

MCx = 11 : up/down mode : the timer repeatedly counts from 0 to TACCR0

and back down to 0

UP MODE

The up mode is used if the timer period must be different from 0FFFFh
counts

1. timer period 100 -> store 99 to TACCR0

2. When TACCR0 == 99, set TACCR0 CCIFG interrupt flag

3. Reset timer to 0 and set TAIFG interrupt flag

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TAIFG is set and Timer_A interrupts the CPU

CONTINUOUS MODE

- In the continuous mode, the timer repeatedly counts up to 0FFFFh and

restarts from zero

- The TAIFG interrupt fall is set when the timer resets from 0FFFFh to
zero

UP DOWN MODE :

The up/down mode is used if the timer period must be different from
0FFFFh counts and if a symmetrical pulse generation is needed

The period is twice the value in TACCR0

MSP430 RESETS

POWER-ON RESET : POR

- caused by hardware

- Response of hardware to brownout(low-power) condition

- Hard power-on is extreme case of brownout

- can happen if physical RST pin is asserted

- Some MSP430 have a supply voltage supervisor (SVS) that can operate a
power on condition if supply voltage drops below acceptable levels

POWER-UP CLEAR (PUC)

- distinctive from power on reset

- Caused by software conditions

- watchdog timer expirations

- Software generated reset condition - bad watchdog password

- runaway flash memory programming - bad flash controller password

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- Access violation - reading IC from peripheral Registers

Conditions after reset - initial conditions for register and peripheral vary

General effects :

- RST/NMI pin configured as RST

- Most input/output pins configured as inputs : software should configure

unused pins as outputs - or otherwise ensure unused inputs are not
floating

- peripheral register set the way the data sheet says :


rw-0 notation means: readable / write and initialised to 0 on PUC 

rw-(0) notation means: readable / write and initialised to 0 only on
POR

- Status register is cleared (brought out of low-power mode if necessary)

- Watchdog timer is enabled: software should explicitly disable if not used

- Program counter R0 is loaded with the reset vector

What caused the reset ?

Can be determined through the IFG1 and perhaps other flag registers

The following bits will be set to identify the source of the reset :

WDTIFG : watchdog caused reset

OFIFG : oscillator fault - non maskable interrupt actually, not a reset. 

RSTIFG : RST pin was asserted 

PORIFG : set on power on reset (POR)

NMIIFG: NMI pin was asserted - non maskable interrupt actually, not a
reset.

On PUC: the WDTIFG bit is not cleared - so the source of the PUC can be
determined

Other flags for flash security and the supply voltage supervisor if
applicable exist elsewhere

Doesn’t appear to be a flag for an illegal opcode

A few hardware considerations :

Be careful with the RST pin - should never be left floating and decoupled
from noise as best as possible. Modern uCs/uPs can have very sensitive
RST lines

Poor quality power supplies can cause problems. A slow supply power rise
on power up (for example) can cause problems - hardware software race
condition.

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MSP430 - CLOCK SYSTEM

MASTER CLOCK : MCLK is used by the CPU and a few peripherals

SUB SYSTEM MASTER CLOCK : SMCLK is distributed to the peripherals

AUXILIARY CLOCK : ACLK is also distributed to the peripherals.

MODES OF OPERATIONS

1. Active mode: I = 300A (Approximately).

2. Low power mode.

REGISTERS FOR LOW POWER MODE

1. LPM0 : both cpu and mclk are disabled. Smclk and aclk are active

2. LPM1 : both cpu and mclk are disabled. DCO is disabled and aclk
remains active

3. LPM2 : CPU, MCLK, SMCLK, DCO are disabled, ACLK remains active.

4. LPM3: CPU, MCLK, SMCLK, DCO are disabled DC generator is enabled

and ACLK remain active

5. LPM4: all clocks are inactive.

POWER CONSUMPTION IN VARIOUS MODE:

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