See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/272885387

Digital filter in hardware loop for on line ECG signal baseline wander
reduction

Conference Paper · January 2010

CITATIONS READS

0 473

4 authors:

Andrius Petrėnas Vaidotas Marozas

Kaunas University of Technology Kaunas University of Technology
38 PUBLICATIONS   331 CITATIONS    124 PUBLICATIONS   766 CITATIONS   

SEE PROFILE SEE PROFILE

S. Daukantas Arunas Lukosevicius

Kaunas University of Technology Kaunas University of Technology
23 PUBLICATIONS   144 CITATIONS    122 PUBLICATIONS   654 CITATIONS   

SEE PROFILE SEE PROFILE

Some of the authors of this publication are also working on these related projects:

KidneyLife (Personalized wearable technologies for evaluating life-threatening health conditions in chronic kidney disease patients) View project

AFAMI (Automatic algorithms for atrial fibrillation risk prediction after acute myocardial infarction) View project

All content following this page was uploaded by Andrius Petrėnas on 28 February 2015.

The user has requested enhancement of the downloaded file.

 Digital filter in hardware loop for on line
ECG signal baseline wander reduction
A. Petrenas1, V. Marozas2, S. Daukantas1, A. Lukosevicius1
1
Biomedical engineering institute, Kaunas University of Technology, Kaunas, Lithuania
2
Signal processing department, Kaunas University of Technology, Kaunas, Lithuania

Abstract— This paper presents the method for the ECG sig- line wander reduction we used the double integrator which
nal baseline wander reduction and prevention the analog to can be interpreted as being two pole Gaussian filter. Gaus-
digital converter from saturation. The method is based on sian filters show the least possible lag introduced into the
digital low pass filter in feedback loop. The digital filter esti- signal. We present here the implementation and evaluation
mates the ECG signal low pas variation (<0,5Hz) and via digi-
of this method.
tal to analog converter feeds back the signal to reference input
of instrumentation amplifier. The change of the signal voltage
at the reference input is opposite in sign to the change of the
signal at instrumentation amplifier input. Thus the baseline II. METHOD
wander is significantly reduced. The method is suitable for on
line processing of ECG signals, is resistant to high motion A. Front end design
intensities and can be implemented using low power mixed
signal microcontrollers. A block diagram of a electrocardiograph baseline wander
reduction stage is shown in Fig. 1. It consists of 1 instru-
Keywords— low power ECG sensor, base line wander, mo-
mentation amplifier (INA333, Texas Instruments Inc.) as
tion artifacts, feedback loop.
the first stage of amplification and base line regulation, the
second stage amplifier for additional subtraction of esti-
I. INTRODUCTION
mated base line wander from ECG signal and for setting the
signal midline (1/2 Vcc), 1 operational amplifier (OPA333,
Baseline wander in electrocardiography (ECG) signal Texas Instruments Inc.) for low pass aliasing filter and mi-
(slowly changing isoelectric line or artifact) can be caused crocontroller (MSP430F618, Texas Instruments Inc.) with
by respiration or skeletal muscles, electrode impedance two ADC inputs (12bits resolution) and two integrated
change and body movements [1]. It can lead to saturation of DAC’s (12bits resolution).
signal amplifier and analog to digital converter (ADC).
Thus baseline wander makes manual or automatic analysis
of ECG signal difficult and must be somehow reduced as
early as possible in signal processing chain. The conven-
tional method to reduce the drift of the ECG signal base line
is to use signal inverting RC integrator (low pass filter) with
differential amplifier in the feedback loop from the instru-
mentation amplifier output to its reference input [2,3].
However this method has disadvantage because RC integra-
tor must have relatively large integration constant (>0,5s)
which calls for additional reset circuit. The additional cir- Fig. 1. Block diagram of ECG front end for reduction of base line wander
cuits increase the size and weight of the ECG sensor.
The limitations of analog approach can be reduced by The signal coming out of instrumentation amplifier and
moving the integrator to digital domain. Digital to analog sensed at ADC1 is composite: low pass part (<0,5Hz)
converter (DAC), which is inside the microcontroller, can represents mainly baseline wander, while higher frequen-
be used to feed back some correction signal to reference cies- ECG signal. The purpose of digital low pass filter is to
input of the instrumentation amplifier [4]. In addition, digi- select from the composite signal spectrum the lower part i.e.
tal implementation of integrator allows much more flexibili- to estimate the base line wander. This part of the signal is
ty in its design. In order to increase effectiveness of base fed via DAC1 output back to instrumentation amplifier’s

P.D. Bamidis and N. Pallikarakis (Eds.): MEDICON 2010, IFMBE Proceedings 29, pp. 554–557, 2010.
www.springerlink.com
Digital Filter in Hardware Loop for On Line ECG Signal Baseline Wander Reduction 555

reference input to automatically reduce the base line varia- Sampling frequency is F = 1 T = 500 Hz thus the differ-
tion. In addition, the signal from DAC0 is fed to negative
ence equation can be expressed as:
input of summator and thus by direct subtraction reducing
base line wander in the ECG signal even further. y[n ] = 0,0063x[n ] + 0,9937 y[n − 1] (9)

B. Digital filter design. Control theory says that system function of control loop can
be written as:
Here we will show the design of digital low pass filter.
The simple analog RC integrator was used as the model for z −1
H loop ( z ) = (10)
digital filter design. Its system function is: 1 + z −1 H ( z ) H ( z )
1 RC
H ( s) = (1) If we insert (3) into (10), we get final system function of the
s + 1 RC system:

By substitution of like terms we can obtain the digital fil- z −1 + 2(α − 1) z −2 + (α − 1) 2 z −3

H loop ( z ) = (10)
ter system function: 1 + (α 2 + 2α − 2) z −1 + (α − 1) 2 z − 2
z RC
H [ z] = (2) The magnitude frequency response of the system was
z + e −T RC found using Matlab and is shown in Fig. 3.
Here T – sampling period.
C. Simulink model.
Simplification [1 − α ] = e −T RC
leads to:
The ECG front end system behavior was analyzed by us-
αz ing simplified Simulink model (see Fig. 2):
H [ z] = (3)
z − [1 − α ]
And the frequency response of the digital filter can be writ-
ten as:

αe jωT
H [e jωT ] = (4)
e jωT − [1 − α ]
The cut off frequency of such filter is the point at which the
amplitudes of the two terms in denominator are equal:

e −ωT = [1 − α ] (5)
Fig. 2. Simulink block diagram of ECG front end for reduction of base line
Thus the cut off frequency can be estimated as: wander

ln(1 − α )
ω=− (6) Two types of signals were used in the investigation: a)
T synthetic composite signal consisting from train of 0,1s
pulse width rectangular pulses added to low frequency
Our desired cut off frequency is f = 0,5Hz thus the con- (0,05Hz) sine signal (base line wander), b) approximately
stant α can be expressed as: 2 min long real ECG signal recorded with developed ECG
sensor but disconnected feedback loop. Loop disconnection
α = 1 − e −2πfT (7) leads to DC coupled input. The simplified Simulink model
The difference equation of digital integrator can be derived models the loop: instrumentation amplifier, digital filter,
from system function in (3): reference input of instrumentation amplifier. The digital
filter is a cascade of two equal filters. Block “Unit Delay1”
y[n] = αx[n] + (1 − α ) y[n − 1] (8) is used in order to make the model realizable.

IFMBE Proceedings Vol. 29

556 A. Petrenas et al.

III. REZULTS The upper graph shows ECG signal with significant vari-
ations of the signal base line. The second graph shows the
The frequency response of the base line wandering re- signal which can be seen in instrumentation amplifier out-
duction loop is shown in Fig. 3. It can be clearly observed put. The third graph represents estimated and inverted ECG
that the ECG processing loop has a high pass character. baseline wander. Finally, the fourth graph shows the condi-
Thus it is able to reduce the low frequency base line wander tioned ECG signal which is later amplified and filtered with
and to protect ADC from saturation. antialiasing filter.
Figure 5 shows ECG processing front end behavior in
Magnitude frequency response case of synthetic signal. European standard EN 60601-2-51.
2 2003 [5] recommends testing ECG front end circuit with
rectangular pulses of 100ms duration and 3 mV in ampli-
Magnitude K, dB

-2
tude. These pulses should not produce an offset on the ECG
record from the isoelectric line. Results (see Fig. 5) show
-4
significant reduction of low frequency sine line representing
-6 base line variation. The negative offset produced by the
10
-1
10
0
10
1
10
2 circuit is not significant.
log frequency, Hz

Fig. 3. Digital integrator magnitude frequency response characteristic

Figure 4 shows an illustration of the circuit behavior du-

ring 2 min time period of ECG signal registration.

Fig. 5. Illustration of intermediate results in ECG signal

processing chain

Fig. 4. Illustration of intermediate results in ECG signal The proposed ECG base line wander reduction approach
processing chain was implemented in ECG sensor for exercise monitoring
(Fig. 6). The sensor has embedded algorithm for estimation

IFMBE Proceedings Vol. 29

Digital Filter in Hardware Loop for On Line ECG Signal Baseline Wander Reduction 557

of RR intervals. BlueTooth wireless link is used for teleme- The drawback may be compensated by increasing the time
try of RR intervals and one lead raw ECG signal to remote constant of digital integrator (decreasing α). However this
devise. measure leads to larger lag of the filter and thus decreases
responsiveness to sudden variations in the base line.
It is argued in [7] that the usage of high resolution (>20
bits) ADC in the ECG acquisition system enables DC
coupling and all the high pass filtering can be avoided.
However, most of existing low power microcontrollers has
16 bit data bus, 32 bits multiplier. Thus we believe that with
today’s microcontroller technology our approach is better.
a) b) The main advantage of the proposed circuit – it keeps the
signal steady in the middle of ADC range even at high mo-
Fig. 6. The developed ECG sensor for exercise monitoring: a) inner elec-
tronics, b) comparison setup with Polar’s WearLink+ W.I.N.D. sensor [6] tion intensity during exercises. This is very important as no
signal processing could help after signal registration with
saturated ADC. Further digital processing may be used for
In order to check effectiveness of the proposed solution
high fidelity reduction of ECG signal base line wandering,
during intensive exercising, the developed sensor was com-
for example, using these methods [8, 9].
pared with Polar’s WearLink+ W.I.N.D. sensor. The pro-
posed method helped to keep the ECG signal inside the
ADC range and resulted in less RR interval estimation er- ACKNOWLEDGMENT
rors (Fig. 7):
This work was partially supported by Lithuanian State
Science and Studies foundation, project VitaActiv.

REFERENCES
1. Rajendra Acharya U, Jasjit S. Suri, Jos A.E. Spaan, S .M. Krishnan.
Advances in Cardiac Signal Processing. Springer, 2007.
2. Raju.M. Heart-Rate and EKG Monitor Using the MSP430FG439.
Application note at http://focus.ti.com/lit/an/slaa280a/slaa280a.pdf
3. INA 333 Micro-Power, Zero-Drift, Rail-to-Rail Out Instrumentation
Amplifier data sheet at http://focus.ti.com/lit/ds/symlink/ina333.pdf
4. Bosch E.; Hartmann E. ECG Front-End Design is Simplified with
MicroConverter. Analog Dialogue 37 – 11, 2003.
5. European Standard EN 60601-2-51. 2003
6. Polar WearLink+W.I.N.D, http://www.polar.fi/us-
Fig. 7 The illustration of comparison results between developed ECG en/products/accessories/WearLink_transmitter_WIND
sensor (VitaActiv) and Polar’s Wearlink+ W.I.N.D. sensor 7. R. Abächerli, H. Schmid. Meet the challenge of high-pass filter and
ST-segment requirements with a DC-coupled digital electrocardio-
gram amplifier. Journal of Electrocardiology, 2009:574-579.
IV. DISCUSSION AND CONCLUSIONS 8. M.Mneimneh, E. Yaz,M. Johnson, and R. Povinelli, “An adaptive
Kalman filter for removing baseline wandering in ECG signals,” in
The online method for ECG signal base line wander re- Proc. 33rd Annu. Int. Conf. Comput. Cardiol., 2006:253–256.
duction and ADC saturation prevention in low power vol- 9. S. Hargittai. Efficient and fast ECG baseline wander reduction with-
out distortion of important clinical information, Computers in Cardi-
tage miniaturized sensor is proposed. The method is based ology, 14-17 Sept. 2008: 841-844.
on digital filter replacing the analog integrator in the feed-
back loop. Even simple low power microcontroller is able to Author: Vaidotas Marozas
do the processing in real time. The performance of the pro- Institute: Kaunas university of technology
posed ECG front end is satisfactory as it keeps the base line Street: Studentu 65-107
City: Kaunas
steadily in the middle of 12bits ADC range (see the lower Country: Lithuania
graph in Fig. 4). The main drawback of the approach is Email: [email protected]
reduced amplitudes in lower part of ECG signal spectrum.

IFMBE Proceedings Vol. 29

View publication stats