Independent University, Bangladesh

Department of Computer Science and Engineering

Course Outline
Course Title: Computer Organization and Architecture
Summer 2019, STs at 01:40 p.m. (section-1), Room: BC 5012,, Level 4
MWs at 03:20 p.m. (section
(section-2), Room: BC 6012, Level 4, Duration: 90 mnts
Instructor’s details:
Mohammad Noor Nabi
Senior Lecturer
Office: Room-6005B,, Visiting Hours: STs at 11:00 a.m. to 01:00 p.m. and MWs at 02:00p.m. to 04:30p.m
(or by appointment)
Cell: 01552381470, Email: [email protected]
@iub.edu.bd

Course Description
This is one of the core courses of Computer Science and Engineering with particular emphasis on
computer organization and architecture
architecture; concept of computer as hierarchical system;; and problems and
methods of designing computers. The main objective of this course is to o learn how certain operating system
functions are supported by computer hardware organization. Understanding how various performance
enhancements to computers are re achieved and tto
o be able to make an informed comparison among competing
architectures for a given purpose.

Course Policy:
1. It is the student’s responsibility to gather information about the assignments and covered topics
during the lectures missed. Regular class attendance is mandatory. Points will be taken off for
missing classes. Without 70% of attendance, sitting for final exam is NOT allowed. According to
IUB system students must enter the classroom within the first 20 minutes to get the attendance
attendan
submitted.
2. The date and syllabus of quiz, midterm and final exam is already given here, however,
announcements will be given ahead of time. There is NO provision for make-up up quizzes.
3. The reading materials for each class will be given prior to that clas
classs so that student may have a
cursory look into the materials.
4. Class participation is vital for better understanding of sociological issues. Students are invited to
raise questions.
5. Students should take tutorials with the instructor during the office hours. Prior appointment is
required.
6. Students must maintain the IUB code of conduct and ethical guidelines offered by the school of
engineering and computer sciences.
Assessment and Marks Distribution:
Students will be assessed on the basis of their overall performance in all the exams, quizzes, and class
participation. Final numeric reward will be the compilation of:
Three quizzes due in different times of the semester (30%)
Two assignment (field based) (15%)
One mid-term test (25%)
A cumulative final exam (30
(30%)
[Class attendance is mandatory; failure to do so may deduct the final marks]

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Grade Conversion Scheme plan:
The following chart will be followed for grading. This has been customized from the guideline
provided by the School of Engineering and Computer Science.

A A- B+ B B- C+ C C- D+ D F

90-100 85-89 80-84 75-79 70-74 65-69 60-64 55-59 50-54 45-49 0-44
* Numbers are inclusive
Required Text:
The course will be based mostly on the following books [some other books and journals may be referred
time to time]:
William Stallings – Computer Organization and Architecture – Design for Performance – [9th,
10th or later International Editions], Prentice Hall
John P. Hays – Computer Architecture and Organization – [3rd or later International Editions]
WCB/McGraw-Hill.

Link to Virtual Learning System:

https://piazza.com/independent_university_bangladesh/summer2019/csc311cen311cse214/resources

Audit:
Students who are willing to audit the course are welcome during the first two classes and are advised to
contact the instructor after that.

Note:
Plagiarism – that is, the presentation of another person’s thoughts or words as though they were the
student’s own – must be strictly avoided. Cheating and plagiarism on exam and assignments are
unacceptable.

University Regulation and Code of Conduct:

Please see the Green Book for further information about academic regulation and policies, including
withdrawal and grading, appeals and penalties for plagiarism and academic misconduct.

Students with Disabilities:

Students with disabilities are required to inform the Department of Law of any specific requirement for
classes or examination as soon as possible.

More Readings:
John D. Carpinelli – Computer Systems Organization and Architecture – [1st or later
International Editions] Pearson
Hennessy and Peterson – Computer Architecture, A Quantitative Approach – [4th or later
International Editions] Elsevier

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 Class & Exam Schedule plan, Topics and Readings:
Sessions Topics Learning Outcome Readings
1. Students will be able to know each other
Session – 1 Introduction 2. Students will learn about the course policy
3. Students will be able to plan for the exams
1. Students will learn the background of
organization and architecture
2. They will be able to categorize structure and Handout (available on
Session – 2 Key Concepts in Computer organization and architecture function of computer Virtual Learning System)
3. They will be able to focus on CPU and control Stallings, Ch-1
unit,

1. They will be able to learn computer evolution.

2. . They will be able to categorize design and Handout (available on
Session – 3 Key Concepts in Computer Evolution and Performance performance Virtual Learning System)
3. Students will be able to know The Von Neumann Stallings, Ch-1 & 2
Machine and structure of IAS computer.
1. Students will learn about computer components
and instruction cycle states Handout (available on
Key concepts and top level view of computer
Session – 4 2. Students will learn about interrupts systems use Virtual Learning System)
function and interconnection in efficient use of computing resources. Stallings, Ch-3
3. They will learn interconnection structures
1. The will be able know issues regarding multiple
bus hierarchies and bus arbitration.
Key concepts and top level view of computer Handout (available on
2. Students will be able to know different bus
Session – 5 function and interconnection Quiz 1 due operations
Virtual Learning System)
[ Assignment] Stallings, Ch-3
3. They will be able to know PCI and other bus
architectures.
1. Students learn about characteristics of
memory systems and the memory hierarchy Handout (available on
Session – 6 Internal Memory: Cache Memory 2. They will know about cache memory principles Virtual Learning System)
and elements of cache memory design Stallings, Ch-4
3. They will learn about cache memory mapping
1. Students will learn about direct , associative and
set associative cache memory design Handout (available on
Session – 7 Internal Memory: Cache Memory 2. They will learn about replacement algorithms Virtual Learning System)
3. They will learn about writing policies and cache Stallings, Ch-4
coherence issues in multiprocessor cache design
1. Students will learn about DRAM versus SRAM Handout (available on
Session – 8 Internal Memory: Main Memory
and use of different type of ROM. Virtual Learning System)

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 2. They will learn chip logics and packaging of RAM Stallings, Ch-5
and ROM
3. They will learn about memory module
organization
1. Students will learn error correction technique:
parity method.
2. They will learn about hamming code for single Handout (available on
Session – 9 Internal Memory: Main Memory bit error correction and double bit error detection. Virtual Learning System)
3. They will know Advance DRAM organization: Stallings, Ch-5
SDRAM, DDR1, DDR2, DDR3 DDR4 and cached
DRAM
1. Students will learn magnetic disk: Read and
Write mechanisms.
Handout (available on
2. They will learn about data organization and
Session – 10 External Memory Virtual Learning System)
formatting.
Stallings, Ch-6
3. They will learn about physical characteristics and
disk performance parameters.
1. Students learn about RAID technologies.
2. They will learn about optical memory devices: Handout (available on
Session – 11 External Memory CD, DVD, Blue ray etc. Virtual Learning System)
3. They learn about Magnetic tape memory Stallings, Ch-6
organization.
1. They will learn about generic models of I/O
module and external devices.
Handout (available on
2. Students will learn major functions and
Session – 12 Input / Output Virtual Learning System)
structure of I/O module.
Stallings, Ch-7
3. They will learn about different I/O techniques
including programmed I/O, Interrupt I/O and DMA
1. Students will learn about I/O module design
issues.
2. They will learn about programmable interrupt
Handout (available on
Session – 13 controller (8259) and programmable peripheral
Input / Output Virtual Learning System)
interface(8255)
Stallings, Ch-7
3. They will learn about DMA configuration, DMA
module (8237) and I/O channels and I/) channels
and processors.
1. Internal Memory: Cache Memory
Stallings, Chapter-4, 5 and
Session – 14 Mid-term test (Class Time) 2. External Memory
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3 Input / Output
1. Students will learn about arithmetic logic unit. Handout (available on
Session – 15 Computer Arithmetic
2. They will learn about signed and unsigned Virtual Learning System)

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 integer representation issues. Stallings, Ch-10
3. They will learn about hardware algorithms for
addition, subtraction multiplication and division.
1. Students will learn about fixed and floating point
representation. Handout (available on
Session – 16 Computer Arithmetic Quiz 2 due 2. They will learn about IEEE standard for binary Virtual Learning System)
floating point representation. Stallings, Ch-10
3. They will learn floating point arithmetic.
1. Students will learn about hardware algorithms
for floating point addition and subtraction.
Handout (available on
2. They will learn about hardware algorithms for
Session – 17 Computer Arithmetic [ Assignment] Virtual Learning System)
floating point multiplication and division
Stallings, Ch-10
3. They will learn about rounding and IEEE standard
for binary floating point arithmetic.
1. Students will learn about processor organization
and data flow during fetch cycle, indirect cycle and
Handout (available on
execute cycles.
Session – 18 Processor Structure and Function Virtual Learning System)
2. They will learn about instruction pipelining
Stallings, Ch-14
strategies.
3. They will learn about speed up using pipeline.
Handout (available on
1. Students will learn about pipeline hazards.
Session – 19 Processor Structure and Function Quiz 3 due Virtual Learning System)
2. They will learn branch prediction strategies.
Stallings, Ch-14
1. Students will learn about RISC instruction
execution characteristics. Handout (available on
Session – 20 Reduced Instruction Set Computers 2. They will learn about use larger register file Virtual Learning System)
issues and compiler-based register optimization Stallings, Ch-15
3. They will learn RISC versus CISC characteristics.
1. Students will learn about Micro-operations.
2. They will learn about micro-operations timing
Handout (available on
states during fetch, indirect, interrupt and execute
Session – 21 Control Unit design Virtual Learning System)
sub cycles.
Stallings, Ch-20
3. They will learn about flow chart of instruction
cycle micro operations.
1. Students will learn about functional requirement
of control unit design.
Handout (available on
2. They will learn about generation control unit
Session – 22 Control Unit design Virtual Learning System)
signals.
Stallings, Ch-20
3. They will learn about sequencing of control
signals.
Session – 23 Micro programmed control unit 1. Students will learn about basic concepts micro Handout (available on

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 instruction and its format in micro-programmed Virtual Learning System)
control unit. Stallings, Ch-21
2. They will learn about organization of control
memory and functioning of micro-programmed
control unit including wilkies micro-programmed
control unit.
3. They will learn about micro-instruction
sequencing and micro-instruction execution.
1. Students will learn about hardware performance
issues: pipelining, superscalar, and symmetric
multithreading.
Handout (available on
2. They will learn about Software performance
Session – 24 Multi core computers Virtual Learning System)
issues on multi-core.
Stallings, Ch-18
3. They will learn about multi-core organization
includes Intel X86 multi-core organizations: core
duo, core i3 and core i7.
Session – 25 Self Study and Revision
1. Computer Arithmetic
2. Processor Structure and Function
3. Reduced Instruction set computers Stallings, Chapter-10, 12,
Session – 26 Final Exam
4. Control Unit design 13, 15, 16 and 18
5. Micro programmed control unit
6. Multi core computers

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