CSE-332

Computer Organization
and
Architecture
Topics to be discussed Topics to be discussed
Introduction, Organization and ALU Design: Adder, Multiplier, Divisor
Architecture Booth’s Algorithm
IAS Structure Floating point Representation and Arithmetic,
Computer Evolution and Performance Hardware
Pipelining Instruction Sets: Characteristics and Functions
Superscalar and Parallel Processing Addressing Modes and Formats
Multicore Processor and system Instruction-Level Parallelism
Bus Interconnection, PCI Control Unit Operation
Cache Memory Hardware Control Design
Semiconductor Main Memory Micro-programmed control Design
DRAM Supercomputer Architecture
ROM Technology Cloud Computing Architecture
Computer Architecture: visible to programmer
How do I design a computer?
• Focuses on the structure: the way in which the components are interrelated
• Computer architecture includes many elements such as
•Instruction sets and formats
•Operation codes
•Data types & Data Representation
•Register architecture with CPU
•Addressing modes
•Input/Output Mechanism
• The architecture of a system directly affects the logical execution of programs.
• The computer architecture for a given machine is the combination of its hardware
components plus its instruction set architecture (ISA).
• The ISA is the interface between all the software that runs on the machine and the
hardware
Computer organization: How does a computer work?

•Computer Organization refers to the level of

abstraction above the digital logic level, but below
the operating system level.

•Encompasses all physical aspects of computer

systems
•Hardware details of the system
•Circuit design
•Control signals
•Memory types & Technologies
von Neumann
(1913 – 1957)
a Hungarian-American
mathematician, physicist,
computer scientist, and
polymath.

proposed STORED-PROGRAM CONCEPT: that a program be electronically

stored in binary-number format in a memory device so that
instructions could be modified by the computer as determined by
intermediate computational results.
The Institute for Advanced Study (IAS) in
Princeton, New Jersey, in the United States,
is an independent, postdoctoral research
center for theoretical research and
intellectual inquiry founded in 1930.

Among its present and past Faculty and Members

are 34 Nobel Laureates, 42 of the 60 Fields
Medalists (mathematician's Nobel Prize)

The IAS machine was built from 1942 to

1951 under von Neumann's direction
introduced the basic architecture of all
modern digital computers.
 A modern computer is an electronic, digital, general purpose
computing machine.

At the most basic level, a computer consists of 3 pieces

▪ A processor to interpret and execute programs
▪ A memory ( Includes Cache, RAM, ROM) to store both data and program instructions
▪ A mechanism for transferring data to and from the outside world.
I/O to communicate between computer and the world
Bus to move info from one computer component to another
Levels of Program code

How the machine

code is formed?

Machine code in binary Stored in RAM

0101000001111111
1100000111100000
0101010100001111
1110000000111111
0101000001111111
1100000111100000
0101010100001111
1110000000111111
Main Memory: Semiconductor ICs
RAM(Random Access Memory)
•Memory is an array of storage, each having capacity of 8 bits or so
and holds program and data in binary format
User Program Module
& Data 1 0 1 0 0 1 1 1

0101000001111111
1100000111100000 1 0 0 1 1 0 1 1
0101010100001111
1110000000111111
0101000001111111
1100000111100000
0101010100001111
1110000000111111

IC Internal of
 Address Address Contents (Machine code & data)
in HEX in Binary
Each row is 0H 0 0 0 0
uniquely 1 0 0 0 1 1 1 0
identified by a 1H 0 0 0 1 0 1 0 0 1 1
number/code, 0 1
starting from 2H 0 0 1 0
‘0’, called
Address, usually 3H 0 0 1 1
represented in
Hexadecimal
form and used
in Assembly
language
programming
7H 0 1 1 1
 Address Address Contents (Machine code or data)
in HEX in Binary
If each location 0H 0 0 0 0
1 0 0 0 1 1 1 0
of memory
contains 8 bits 1H 0 0 0 1 0 1 1 1
0 0 0 1
or 1 byte, then
it is called 2H 0 0 1 0

Byte-Addressabl 3H 0 0 1 1
e memory

7H 0 1 1 1 0
1 0 1 0 1 0 1
 Capacity of Memory
• Example: 1KB: Approximately 1 Thousand (exact value 1024) locations each having
capacity of 8 bits/1Byte

• Address starts at 0 and ends at 1 less than 1 Thousand, actually encoded in BINARY

• In Binary, first address requires 1 bit (0) and final addressable location requires 10
bits (all 1’s: 11…11), since 210 = 1K

• For ease of Decoder design, uniform address format is used for all the locations;
Maximum number of bits!

• For convenience/ease of representation/programming/discussion, Hexadecimal

number system is used to represent Memory address
 Address of Memory (for 1KB)
Address (20 bits in binary) Content (8 bits)
1111111111B 11001100 (machine code/data)
…
0000000000B 00110101(machine code/data)

Address (3 digits in hexadecimal) Content(8 bits)

3FFH 11001100 (machine code/data)

000H 00110101(machine code/data)

 Capacity of Memory
• Example: 1MB: Approximately 1 Million (exact value 1024 x 1024) locations each having
capacity of 1Byte

• Address starts at 0 and ends at 1 less than 1 Million, actually encoded in BINARY

• In Binary, first address requires 1 bit (0) and final addressable location requires 20 bits (all
1’s: 11…11), since 220 = 1M

• For ease of Decoder design, uniform address format is used for all the locations;
Maximum number of bits!

• For convenience/ease of representation/programming/discussion, Hexadecimal

number system is used to represent Memory address
 Address of Memory (for 1MB)
Address (20 bits in binary) Content (8 bits)
11111111111111111111B 11001100 (machine code/data)
…
00000000000000000000B 00110101(machine code/data)

Address (5 digits in hexadecimal) Content(8 bits)

FFFFFH 11001100 (machine code/data)

00000H 00110101(machine code/data)

CPU
• Register is an electronic
storage inside the CPU

• Used to hold data/(RAM)

address of program

• Number & size of registers

vary from CPU to CPU
Registers
• Size: 4 bits/8 bits/16 bits/32 bits/64 bits/128 bits…

• In modern processors: Register size and number both are increasing

• Register types: General purpose & special purpose

• Must know register architecture for Assembly Language Programming

• Since registers are few in numbers, they are addressed by Names in

Assembly language Programs

• Naming depends on processor series, usually upper case one/two/three

letters are used. Example: A, AX, EAX etc
 Types of Registers
• General purpose: Holds data to be used in ALU. Also holds partial results or
final results generated by ALU.

• Special Purpose:
• Holds address of main memory locations where instructions are loaded by
Operating system.
• Holds address of main memory locations where data are stored
• Holds address of main memory locations used for special purposes
• Holds machine code of Instructions
• Holds status of CPU
 CPU memory

Accumulator
General Purpose

Status register

Index register
Flag Register
Program Counter

Control, data, address bus

ALU

Control unit Types of Registers

Levels of Program code
How the
instructions are
designed?
How the machine codes are
formed?
Machine code in Stored in RAM
binary
0101000001111111
1100000111100000
0101010100001111
1110000000111111
0101000001111111
1100000111100000
0101010100001111
1110000000111111
•Two key benefits of assembly language programming
– It takes up less memory
– It executes much faster

•Assembly language is good for controlling hardware devices

Software

• The sequence of commands used to tell a

microcomputer what to do is called a program,

• Each command in a program is called an instruction

• 8086 understands and performs operations for 117 basic

instructions
The 8086 microprocessor supports 8 types of instructions −

•Data Transfer Instructions

•Arithmetic Instructions
•Bit Manipulation Instructions
•String Instructions
•Program Execution Transfer Instructions (Branch & Loop
Instructions)
•Processor Control Instructions
•Iteration Control Instructions
•Interrupt Instructions
Instruction—An operation performed by the CPU and assigned a specific number
Instruction set—The list of CPU instructions for the operations
 Instruction format
OPCODE

Example: STD ; clear direction flag bit

OPCODE OPERAND

Example: NOT AX ; complement content of AX

OPCODE OPERAND-1 OPERAND-2

Example: MOV AX, BX; copy the contents of BX into AX

 Instruction format
• Instructions having only opcodes, everything is indicated within.

• Some instructions may require only one operand

• To reduce the size of instructions, only one operand is indicated in

instructions whereas a default register/memory location is used for other
operand.

• Example: MUL BX ; AX holds other operand

• PUSH AX; contents of AX is copied into memory location within Stack

segment.
 Machine Codes
• An instruction can be coded with 1 to 6 bytes
• Byte 1 contains three kinds of information
– Opcode field (6 bits) specifies the operation (add, subtract, move)
– Register Direction Bit (D bit) Tells the register operand in REG field in byte 2
is source or destination operand
1: destination 0: source
-Data Size Bit (W bit) Specifies whether the operation will be performed on
8-bit or 16-bit data
0: 8 bits 1: 16 bits

15 ------- 10 9 8 7 ---- 6 5 ---- 3 2 ---- 0

• Byte 2 has three fields
– Mode field (MOD)
– Register field (REG) used to identify the register for the first operand
– Register/memory field (R/M)

15 ------- 10 9 8 7 ---- 6 5 ---- 3 2 ---- 0

 RAM(16 bits)
Address Contents
1256H 001010111000011
1257H 100010111001000

RAM(8 bits)
Address Contents
1256H 11000011
1257H 0010101
1258H 11001000
1259H 1000101
Computer Components Memory
CPU ADDRESS CONTENTS
125H 11001101 (Machine code of
PC
Instruction-1)
MAR
Address 126H 10001101 (Machine code of
Bus Instruction-2)
MDR 127H 11101101 (Machine code of
Data
Register Instruction-3)
File Bus
IR 128H 11011101 (Machine code of
Instruction-4)

ALU Control
Unit 200H 11000101(DATA-1)
Control
201H 11000001(DATA-1)
Bus
202H 11000111(DATA-1)
PC-Program counter Control Unit decodes
MAR-Memory Address IR-Instruction Register
Register MDR-Memory Data Register Instructions & Generates
control signals
 User program
SUB AX, BX
How does computer work? MOV CX, AX
MOV DX, 0

CPU
Address
RAM(16 bits)
PC MAR Bus Address Contents

Data
MDR
Bus 1256H 001010111000011
Register
File
IR 1257H 100010111001000

ALU 1258H 100111111001011

Control Control
Unit Bus
 User program
SUB AX, BX
STEP-1: PC is loaded with address
MOV CX, AX
of 1st instruction of program
MOV DX, 0

CPU

Address
RAM(16 bits)
PC 1256H MAR Bus Address Contents

Data
MDR
Bus 1256H 001010111000011
Register
File
IR 1257H 100010111001000

ALU 1258H 100111111001011

Control Control
Unit Bus
 User program
SUB AX, BX
STEP-2: content of PC is loaded
MOV CX, AX
into MAR
MOV DX, 0

CPU

Address
RAM(16 bits)
PC 1256H MAR 1256 Bus Address Contents

Data
MDR
Bus 1256H 001010111000011
Register
File
IR 1257H 100010111001000

ALU 1258H 100111111001011

Control Control
Unit Bus
 User program
STEP-3: content of MAR is placed SUB AX, BX
on Address bus and applied to MOV CX, AX
Memory, as a result memory MOV DX, 0
location 1256H is selected
CPU

Address
RAM(16 bits)
PC 1256H MAR 1256H Bus 1256H Address Contents

Data
MDR
Bus 1256H 001010111000011
Register
File
IR 1257H 100010111001000

ALU 1258H 100111111001011

Control Control
Unit Bus
 User program
STEP-4: Control unit send READ SUB AX, BX
control signal to RAM, as a result MOV CX, AX
machine code of 1st instruction is MOV DX, 0
available on Data Bus
CPU

Address
RAM(16 bits)
PC 1256H MAR 1256H Bus 1256H Address Contents

MDR Data 1256H 001010111000011

Register Bus
File 001010111000011
IR 1257H 100010111001000

ALU 1258H 100111111001011

Control Control
Unit Bus READ
 User program
SUB AX, BX
STEP-5: Machine code of 1st MOV CX, AX
instruction is loaded into IR MOV DX, 0

CPU

Address
RAM(16 bits)
PC 1256H MAR 1256H Bus 1256H Address Contents

MDR 1256H 001010111000011

Register Data
File IR Bus
001010111000011 1257H 100010111001000

ALU 1258H 100111111001011

Control Control
Unit Bus READ
 User program
STEP-6: PC is incremented by 1 to SUB AX, BX
point next instruction to be MOV CX, AX
executed. Contents of IR is fed to MOV DX, 0
Control Unit
CPU

Address
RAM(16 bits)
PC 1257H MAR Bus Address Contents
Data
MDR Bus 1256H 001010111000011
Register
File IR
1257H 100010111001000

Control 1258H 100111111001011

ALU
Unit Control
001010111000011 Bus
 User program
STEP-7: 1st instruction is decoded at SUB AX, BX
control unit: control signals are MOV CX, AX
generated to activate ALU for
MOV DX, 0
specific operation as per instruction

CPU

Address
RAM(16 bits)
PC 1257H MAR Bus Address Contents
Data
MDR Bus 1256H 001010111000011
Register
File IR
1257H 100010111001000

Control
ALU Unit
1258H 100111111001011
Control
001010111000011 Bus
 User program
STEP-8: 1st instruction is Executed SUB AX, BX
(that includes Data read from MOV CX, AX
RAM followed by ALU operation, MOV DX, 0
result stored as per instruction)
CPU

Address
RAM(16 bits)
PC 1257H MAR Bus Address Contents
Data
MDR Bus 1256H 001010111000011
Register
File IR
1257H 100010111001000

Control 1258H 100111111001011

ALU
Unit Control
001010111000011 Bus
 User program
SUB AX, BX
STEPS-2:8 repeated for next
instruction MOV CX, AX
content of PC is loaded into MAR MOV DX, 0

CPU

Address
RAM(16 bits)
PC 1257H MAR 1257H Bus Address Contents

Data
MDR
Bus 1256H 001010111000011
Register
File
IR 1257H 100010111001000

ALU 1258H 100111111001011

Control Control
Unit Bus
 Instruction Set Design
# Types of Operations /Instructions and
Complete list of Instructions
# Mnemonics of Instructions or operations (Usually represented by
assembly codes)
# Formats of Instructions (fields/subfields/size in binary bits/data
format/memory address formats/addressing modes etc)
# Machine Codes in Binary
Instruction Set Architecture
Instruction Set Architecture
• How many instructions and types of instructions processors can
understand/decode/process/execute
• How to perform any operation: Accumulator based or General?
• Instruction Format?
• Number of binary bits used to form Instructions
• Same number of bits for all instructions or not?
• How arithmetic/logical/data processing/data transfer operations are
encoded in instructions
• How data/main memory address/register names are indicated in
instructions
• Data types/formats/number of bits used/positive/negative
numbers/ranges of numbers etc
• Memory: Address format/addressing scheme/content of each
addressable locations etc
Instruction Set Architecture
 Instruction Formats (3-operand fields)
ADD M, D1, D2 [M] D1+ D2
Binary code for ALU Memory address to Data -1 Data-2
operation store result (Binary) (Binary) (Binary)
(Op Code)

ADD M1, M2, M3 [M1] [M2]+ [M3]

Binary code for ALU Memory address to Memory address of Memory address of
operation store result (Binary) Data -1 (Binary) Data-2 (Binary)
(Op Code)

ADD R1, R2, R3 R1 R2+ R3

Binary code for ALU CPU Register to CPU register CPU register
operation store result (Binary) containing Data -1 containing Data -1
(Op Code) (Binary) (Binary)
 Instruction Formats(2-operand field)

ADD M1, M2 [M1] [M1]+ [M2]

Binary code for ALU CPU register or memory CPU register or memory
operation address that contains address that contains
(Op Code) Data-1 (Binary) Data-2
Result is stored in same (Binary)
CPU register or memory
address after operation

ADD R1, R2 R1 R1 + R2
ADD M, R1 [M] R1 + [M]
 Instruction Formats(one-operand field)
ADD M AC [M] + AC
Binary code for ALU CPU register or
operation memory address that
(Op Code) contains Data-2
(Binary)
Here Data-1 should be loaded into a predefined register, namely Accumulator (AC)
prior to use this instruction. Moreover, the result is stored into Accumulator (AC) as
well. Interestingly, the Accumulator (AC) is not explicitly indicated in the
Instruction sub-field!

ADD R1 AC R1 + AC
Instruction Formats(Opcode only!)
CLC Clear carry Flag bit
Binary code for ALU /special
operation

Data to be used should be initially loaded into default

CPU register. Result is also stored there as well.
Example: Opcode of Instructions
Operation Mnemonic Opcode
Addition ADD 001
Subtraction SUB 010
Data Transfer MOV 011
Load Accumulator LOAD 100
Multiply MUL 101
Read from Input READ 110
device
Send to output STORE 111
device
 Format of an Instruction
OP CODE OPERAND FIELD-1 OPERAND FIELD-2 OPERAND FIELD-3
4-BITS 4-BITS 4-BITS 4-BITS

OP CODE OPERAND FIELD-1 OPERAND FIELD-2

4-BITS 4-BITS 4-BITS

OP CODE OPERAND FIELD-1 OPERAND FIELD-2

8-BITS 16-BITS 16-BITS
Sample questions
• What do you understand by computer architecture?
• What are the architectural attributes?
• What are the main features of von Neumann architecture?
• What is the concept of stored program computer?
• What is computer organization?
• What are the organizational attributes?
• State/explain difference between computer architecture and organization.
• What do you understand by Register and Register file? What do registers contain?
• State the types of register. State the functions of Registers. What do you understand by size of Register?
• What do you understand by Instruction and Instruction set and Instruction format?
• State the classification of Processors based on instruction set architecture. Give examples. Also state relative
merits and demerits.
• What do you understand by machine code? Show general format of machine code/Instruction format.
• What do you understand by main memory? Is it volatile or non volatile?
• What do you understand by Random Access Memory? Why it is named so?
• What do you understand by Memory address? How it is formed? How it is represented? Give examples.
• Show the address formats of (i) 1KB, (ii) 1MB, (iii) 1K x 16 bits, 4K x 32 bits memory
ICs.
• What do memory locations contain? Give examples
• What do you understand by Byte-addressable memory and Word-addressable
memory? State differences, if any.
• What do you understand by bus system? Discuss types, sizes of types and their
impacts on performance of a computer.
• Draw a simple schematic diagram of a computer and identify its main functional
units.
• Draw a simple schematic diagram of a CPU/Microprocessor and identify its main
functional units.
• List the steps usually followed by a general purpose processor to run a program.
• List the steps usually followed by a general purpose processor to run a program.
• List the steps usually followed by a general purpose processor to process a single
instruction. Use suitable diagram.
• What do you understand by Instruction fetch and Instruction Execution?
• How does a CPU/Microprocessor run a program? Use a suitable schematic
diagram and list the steps in chronological order.
• What is program counter (pc)? What is Instruction register (IR)? Discuss the
functions of each.
• What do you understand by Port address? Why it is used?
• Briefly explain Read / Write operation.
• List the four main structural components of a computer and briefly state their
functions.
• Briefly describe IAS structure with a suitable diagram.
• List the registers of IAS structure and state their functions.
• Show the instruction and data format of IAS structure.
• Briefly describe how IAS structure works?
• List the steps how IAS structure runs a program?