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National University of Computer and Emerging Sciences, Lahore Campus

This document contains instructions for Assignment 2 of the Computer Architecture course. It includes 5 questions about pipelining in MIPS processors, with subquestions about adding new instructions, hazards, forwarding logic, branch prediction, and execution times with different forwarding configurations.

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51 views

National University of Computer and Emerging Sciences, Lahore Campus

This document contains instructions for Assignment 2 of the Computer Architecture course. It includes 5 questions about pipelining in MIPS processors, with subquestions about adding new instructions, hazards, forwarding logic, branch prediction, and execution times with different forwarding configurations.

Uploaded by

xxx
Copyright
© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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National University of Computer and Emerging Sciences, Lahore Campus

Course: Computer Architecture Course Code: EE204


Program: BS(Computer Science) Semester: Spring 2018
Total Marks: 80
Due Date: 05-04-2018 Weight 3.3
Section: All Page(s): 4
Exam: Assignment 2
Note: Submit assignment in the hard farm during the class or in my office before 5pm.

Question1: [15 marks]


In this exercise, we examine how the ISA affects pipeline design. Problems in this exercise refer
to the following new instruction:

Bezi (RS), offset If Mem[Rs] = 0 then PC = PC + offset


Swi Rd, Rs(Rt) Mem [Rs +Rt] = Rd

a. What must be changed in the pipelined datapath to add this instruction to the MIPS ISA?
b. Which new control signals must be added to your pipeline?
c. Does support for this instruction introduce any new hazards? Are stalls due to existing
hazards made worse?

Question2: [15 marks]


We have studied multi-cycle MIPS as shown below with datapath and control unit. Forwarding
unit and Data-hazard detection unit is also implemented.

The calculation for the branch instruction has been moved to decode stage which helps to reduce
the number of stalls from 3 to 1 due to control hazard. But this move affects the existing
forwarding logic. Consider the following two cases.
add R1, R1, 8
beq R1, R2, 30

ld R1, R3, 4
beq R1, R2, 30

In class we have only implemented exe to exe and mem to exe forwarding but in these cases we
may need to extend forwarding so that we can forward to decode stage as well.
Analyze above two cases and design a new unit in decodes stage that will cater these cases.
Draw the changes required in the below MIPS architecture along-with addition in the detection
and forwarding logic.
Question3:

Consider the following MIPS assembly language loop. Assume that we run this code on the five
stages pipelined data path. [20 marks]

Instruction 1: Lw t1, t2,0


Instruction 2: Lw t2, t2,20
Instruction 3: Add t3,t1,t2
Instruction 4: Lw t4,40(t1)
Instruction 5: Add t4,t3,t4
Instruction 6: St t4, t5,15
Instruction 7: Add t4,t6,t6

a) Find all possible hazards in the above code. Fill the following table by writing lines and
register in front of particular hazard. For example if a WAR hazard exist between
instruction 1 and 2 due to register R0 then write 1 & 2 in column “Lines” and Register
number R0 in column “Register”.

Without Forwarding With Forwarding


Hazard Lines Register Hazard Lines Register
WAR

WAW
RAW

b) Add stalls in the above code to remove all hazards

Without Forwarding With Forwarding

c) Reschedule the code to remove as many stalls as possible with forwarding. How
many stalls are still required?

Question 4: 15 marks

Determine the accuracy of various branch predictors for the following pattern of branch
outcomes. These are the actual outcomes.

a. What is the accuracy of always-taken and always-not-taken predictors for this sequence
of branch outcomes?
b. What is the accuracy of the two-bit predictor for the first 4 branches in this pattern,
assuming that the predictor starts off from state (predict not taken)?
c. What is the accuracy of the two-bit predictor if this pattern is repeated forever?
Question 5: 15 marks

Consider the following code sequence

lw R2,50(R3) // Load from Memory[R3 + 50] into R2


add R3,R4,R5 //add R4 and R5 and place the result in R3
sw R3, 50(R2) // Store R3 to Memory[R2+50]

Consider the following clock cycle times for a 5-stage pipelined datapath

Without Forwarding With Full Forwarding With ALU-ALU


(ALU-ALU and MEM-ALU) forwarding only
300 ps 400ps 350ps

a. What is the total execution time of the above code sequence when pipeline without
forwarding is used? [5]

b. What is the total execution time of the above code sequence when pipeline with ALU-ALU
forwarding is used? [5]

c. What is the total execution time of the above code sequence when pipeline with full
forwarding is used? [5]

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